[PATCH] ARM: 2839/1: Remove XScale cache and TLB locking code
Patch from Deepak Saxena The XScale locking code is not something that has been validated on 2.6 and needs to be replaced with a more generic API to use with other ARMs that support locking features. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Deepak Saxena
Russell King
parent
f148af2593
commit
975ad141ee
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@ -370,142 +370,6 @@ ENTRY(cpu_xscale_dcache_clean_area)
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bhi 1b
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mov pc, lr
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/* ================================ CACHE LOCKING============================
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*
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* The XScale MicroArchitecture implements support for locking entries into
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* the data and instruction cache. The following functions implement the core
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* low level instructions needed to accomplish the locking. The developer's
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* manual states that the code that performs the locking must be in non-cached
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* memory. To accomplish this, the code in xscale-cache-lock.c copies the
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* following functions from the cache into a non-cached memory region that
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* is allocated through consistent_alloc().
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*
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*/
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.align 5
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/*
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* xscale_icache_lock
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*
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* r0: starting address to lock
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* r1: end address to lock
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*/
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ENTRY(xscale_icache_lock)
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iLockLoop:
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bic r0, r0, #CACHELINESIZE - 1
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mcr p15, 0, r0, c9, c1, 0 @ lock into cache
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cmp r0, r1 @ are we done?
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add r0, r0, #CACHELINESIZE @ advance to next cache line
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bls iLockLoop
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mov pc, lr
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/*
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* xscale_icache_unlock
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*/
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ENTRY(xscale_icache_unlock)
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mcr p15, 0, r0, c9, c1, 1 @ Unlock icache
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mov pc, lr
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/*
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* xscale_dcache_lock
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*
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* r0: starting address to lock
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* r1: end address to lock
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*/
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ENTRY(xscale_dcache_lock)
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mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
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mov r2, #1
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mcr p15, 0, r2, c9, c2, 0 @ Put dcache in lock mode
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cpwait ip @ Wait for completion
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mrs r2, cpsr
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orr r3, r2, #PSR_F_BIT | PSR_I_BIT
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dLockLoop:
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msr cpsr_c, r3
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mcr p15, 0, r0, c7, c10, 1 @ Write back line if it is dirty
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mcr p15, 0, r0, c7, c6, 1 @ Flush/invalidate line
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msr cpsr_c, r2
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ldr ip, [r0], #CACHELINESIZE @ Preload 32 bytes into cache from
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@ location [r0]. Post-increment
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@ r3 to next cache line
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cmp r0, r1 @ Are we done?
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bls dLockLoop
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mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
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mov r2, #0
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mcr p15, 0, r2, c9, c2, 0 @ Get out of lock mode
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cpwait_ret lr, ip
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/*
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* xscale_dcache_unlock
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*/
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ENTRY(xscale_dcache_unlock)
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mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
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mcr p15, 0, ip, c9, c2, 1 @ Unlock cache
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mov pc, lr
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/*
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* Needed to determine the length of the code that needs to be copied.
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*/
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.align 5
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ENTRY(xscale_cache_dummy)
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mov pc, lr
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/* ================================ TLB LOCKING==============================
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*
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* The XScale MicroArchitecture implements support for locking entries into
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* the Instruction and Data TLBs. The following functions provide the
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* low level support for supporting these under Linux. xscale-lock.c
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* implements some higher level management code. Most of the following
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* is taken straight out of the Developer's Manual.
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*/
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/*
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* Lock I-TLB entry
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*
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* r0: Virtual address to translate and lock
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*/
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.align 5
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ENTRY(xscale_itlb_lock)
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mrs r2, cpsr
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orr r3, r2, #PSR_F_BIT | PSR_I_BIT
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msr cpsr_c, r3 @ Disable interrupts
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mcr p15, 0, r0, c8, c5, 1 @ Invalidate I-TLB entry
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mcr p15, 0, r0, c10, c4, 0 @ Translate and lock
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msr cpsr_c, r2 @ Restore interrupts
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cpwait_ret lr, ip
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/*
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* Lock D-TLB entry
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*
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* r0: Virtual address to translate and lock
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*/
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.align 5
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ENTRY(xscale_dtlb_lock)
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mrs r2, cpsr
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orr r3, r2, #PSR_F_BIT | PSR_I_BIT
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msr cpsr_c, r3 @ Disable interrupts
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mcr p15, 0, r0, c8, c6, 1 @ Invalidate D-TLB entry
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mcr p15, 0, r0, c10, c8, 0 @ Translate and lock
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msr cpsr_c, r2 @ Restore interrupts
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cpwait_ret lr, ip
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/*
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* Unlock all I-TLB entries
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*/
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.align 5
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ENTRY(xscale_itlb_unlock)
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mcr p15, 0, ip, c10, c4, 1 @ Unlock I-TLB
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mcr p15, 0, ip, c8, c5, 0 @ Invalidate I-TLB
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cpwait_ret lr, ip
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/*
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* Unlock all D-TLB entries
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*/
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ENTRY(xscale_dtlb_unlock)
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mcr p15, 0, ip, c10, c8, 1 @ Unlock D-TBL
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mcr p15, 0, ip, c8, c6, 0 @ Invalidate D-TLB
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cpwait_ret lr, ip
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/* =============================== PageTable ============================== */
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#define PTE_CACHE_WRITE_ALLOCATE 0
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