staging: comedi: addi_apci_3501: define the timer i/o registers
Create, and use, defines for the i/o registers used with the timer subdevice. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Cc: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -1,14 +1,5 @@
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/* Watchdog Related Defines */
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#define APCI3501_WATCHDOG 0x20
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#define APCI3501_TCW_SYNC_ENABLEDISABLE 0
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#define APCI3501_TCW_RELOAD_VALUE 4
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#define APCI3501_TCW_TIMEBASE 8
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#define APCI3501_TCW_PROG 12
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#define APCI3501_TCW_TRIG_STATUS 16
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#define APCI3501_TCW_IRQ 20
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#define APCI3501_TCW_WARN_TIMEVAL 24
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#define APCI3501_TCW_WARN_TIMEBASE 28
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#define ADDIDATA_TIMER 0
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#define ADDIDATA_WATCHDOG 2
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@ -52,69 +43,47 @@ static int i_APCI3501_ConfigTimerCounterWatchdog(struct comedi_device *dev,
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devpriv->b_TimerSelectMode = ADDIDATA_WATCHDOG;
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/* Disable the watchdog */
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outl(0x0, dev->iobase + APCI3501_WATCHDOG + APCI3501_TCW_PROG); /* disable Wa */
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outl(0x0, dev->iobase + APCI3501_TIMER_CTRL_REG);
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if (data[1] == 1) {
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/* Enable TIMER int & DISABLE ALL THE OTHER int SOURCES */
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outl(0x02,
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dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_PROG);
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outl(0x02, dev->iobase + APCI3501_TIMER_CTRL_REG);
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} else {
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outl(0x0, dev->iobase + APCI3501_WATCHDOG + APCI3501_TCW_PROG); /* disable Timer interrupt */
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/* disable Timer interrupt */
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outl(0x0, dev->iobase + APCI3501_TIMER_CTRL_REG);
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}
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/* Loading the Timebase value */
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outl(data[2],
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dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_TIMEBASE);
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outl(data[2], dev->iobase + APCI3501_TIMER_TIMEBASE_REG);
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outl(data[3], dev->iobase + APCI3501_TIMER_RELOAD_REG);
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/* Loading the Reload value */
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outl(data[3],
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dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_RELOAD_VALUE);
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/* Set the mode */
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ul_Command1 = inl(dev->iobase + APCI3501_WATCHDOG + APCI3501_TCW_PROG) | 0xFFF819E0UL; /* e2->e0 */
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outl(ul_Command1,
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dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_PROG);
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} /* end if(data[0]==ADDIDATA_WATCHDOG) */
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/* Set the mode (e2->e0) */
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ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG) | 0xFFF819E0UL;
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outl(ul_Command1, dev->iobase + APCI3501_TIMER_CTRL_REG);
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}
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else if (data[0] == ADDIDATA_TIMER) {
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/* First Stop The Timer */
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ul_Command1 =
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inl(dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_PROG);
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ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG);
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ul_Command1 = ul_Command1 & 0xFFFFF9FEUL;
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outl(ul_Command1, dev->iobase + APCI3501_WATCHDOG + APCI3501_TCW_PROG); /* Stop The Timer */
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outl(ul_Command1, dev->iobase + APCI3501_TIMER_CTRL_REG);
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devpriv->b_TimerSelectMode = ADDIDATA_TIMER;
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if (data[1] == 1) {
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/* Enable TIMER int & DISABLE ALL THE OTHER int SOURCES */
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outl(0x02,
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dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_PROG);
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outl(0x02, dev->iobase + APCI3501_TIMER_CTRL_REG);
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} else {
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outl(0x0, dev->iobase + APCI3501_WATCHDOG + APCI3501_TCW_PROG); /* disable Timer interrupt */
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/* disable Timer interrupt */
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outl(0x0, dev->iobase + APCI3501_TIMER_CTRL_REG);
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}
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/* Loading Timebase */
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outl(data[2],
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dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_TIMEBASE);
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outl(data[2], dev->iobase + APCI3501_TIMER_TIMEBASE_REG);
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outl(data[3], dev->iobase + APCI3501_TIMER_RELOAD_REG);
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/* Loading the Reload value */
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outl(data[3],
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dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_RELOAD_VALUE);
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/* printk ("\nTimer Address :: %x\n", (dev->iobase + APCI3501_WATCHDOG)); */
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ul_Command1 =
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inl(dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_PROG);
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/* mode 2 */
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ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG);
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ul_Command1 =
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(ul_Command1 & 0xFFF719E2UL) | 2UL << 13UL | 0x10UL;
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outl(ul_Command1, dev->iobase + APCI3501_WATCHDOG + APCI3501_TCW_PROG); /* mode 2 */
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} /* end if(data[0]==ADDIDATA_TIMER) */
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outl(ul_Command1, dev->iobase + APCI3501_TIMER_CTRL_REG);
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}
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return insn->n;
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}
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@ -156,73 +125,48 @@ static int i_APCI3501_StartStopWriteTimerCounterWatchdog(struct comedi_device *d
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if (devpriv->b_TimerSelectMode == ADDIDATA_WATCHDOG) {
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if (data[1] == 1) {
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ul_Command1 =
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inl(dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_PROG);
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ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG);
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ul_Command1 = (ul_Command1 & 0xFFFFF9FFUL) | 0x1UL;
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/* Enable the Watchdog */
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outl(ul_Command1,
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dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_PROG);
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outl(ul_Command1, dev->iobase + APCI3501_TIMER_CTRL_REG);
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}
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else if (data[1] == 0) /* Stop The Watchdog */
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{
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/* Stop The Watchdog */
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ul_Command1 =
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inl(dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_PROG);
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ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG);
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ul_Command1 = ul_Command1 & 0xFFFFF9FEUL;
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outl(0x0,
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dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_PROG);
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outl(0x0, dev->iobase + APCI3501_TIMER_CTRL_REG);
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} else if (data[1] == 2) {
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ul_Command1 =
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inl(dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_PROG);
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ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG);
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ul_Command1 = (ul_Command1 & 0xFFFFF9FFUL) | 0x200UL;
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outl(ul_Command1,
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dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_PROG);
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} /* if(data[1]==2) */
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} /* end if (devpriv->b_TimerSelectMode==ADDIDATA_WATCHDOG) */
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outl(ul_Command1, dev->iobase + APCI3501_TIMER_CTRL_REG);
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}
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}
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if (devpriv->b_TimerSelectMode == ADDIDATA_TIMER) {
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if (data[1] == 1) {
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ul_Command1 =
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inl(dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_PROG);
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ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG);
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ul_Command1 = (ul_Command1 & 0xFFFFF9FFUL) | 0x1UL;
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/* Enable the Timer */
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outl(ul_Command1,
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dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_PROG);
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outl(ul_Command1, dev->iobase + APCI3501_TIMER_CTRL_REG);
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} else if (data[1] == 0) {
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/* Stop The Timer */
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ul_Command1 =
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inl(dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_PROG);
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ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG);
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ul_Command1 = ul_Command1 & 0xFFFFF9FEUL;
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outl(ul_Command1,
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dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_PROG);
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outl(ul_Command1, dev->iobase + APCI3501_TIMER_CTRL_REG);
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}
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else if (data[1] == 2) {
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/* Trigger the Timer */
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ul_Command1 =
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inl(dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_PROG);
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ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG);
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ul_Command1 = (ul_Command1 & 0xFFFFF9FFUL) | 0x200UL;
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outl(ul_Command1,
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dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_PROG);
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outl(ul_Command1, dev->iobase + APCI3501_TIMER_CTRL_REG);
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}
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}
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} /* end if (devpriv->b_TimerSelectMode==ADDIDATA_TIMER) */
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i_Temp = inl(dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_TRIG_STATUS) & 0x1;
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i_Temp = inl(dev->iobase + APCI3501_TIMER_STATUS_REG) & 0x1;
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return insn->n;
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}
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@ -258,18 +202,14 @@ static int i_APCI3501_ReadTimerCounterWatchdog(struct comedi_device *dev,
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struct apci3501_private *devpriv = dev->private;
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if (devpriv->b_TimerSelectMode == ADDIDATA_WATCHDOG) {
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data[0] =
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inl(dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_TRIG_STATUS) & 0x1;
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data[1] = inl(dev->iobase + APCI3501_WATCHDOG);
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} /* end if (devpriv->b_TimerSelectMode==ADDIDATA_WATCHDOG) */
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data[0] = inl(dev->iobase + APCI3501_TIMER_STATUS_REG) & 0x1;
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data[1] = inl(dev->iobase + APCI3501_TIMER_SYNC_REG);
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}
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else if (devpriv->b_TimerSelectMode == ADDIDATA_TIMER) {
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data[0] =
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inl(dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_TRIG_STATUS) & 0x1;
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data[1] = inl(dev->iobase + APCI3501_WATCHDOG);
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} /* end if (devpriv->b_TimerSelectMode==ADDIDATA_TIMER) */
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data[0] = inl(dev->iobase + APCI3501_TIMER_STATUS_REG) & 0x1;
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data[1] = inl(dev->iobase + APCI3501_TIMER_SYNC_REG);
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}
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else if ((devpriv->b_TimerSelectMode != ADDIDATA_TIMER)
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&& (devpriv->b_TimerSelectMode != ADDIDATA_WATCHDOG)) {
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@ -44,6 +44,14 @@
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#define APCI3501_AO_DATA_VAL(x) ((x) << 8)
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#define APCI3501_AO_DATA_BIPOLAR (1 << 31)
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#define APCI3501_AO_TRIG_SCS_REG 0x08
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#define APCI3501_TIMER_SYNC_REG 0x20
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#define APCI3501_TIMER_RELOAD_REG 0x24
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#define APCI3501_TIMER_TIMEBASE_REG 0x28
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#define APCI3501_TIMER_CTRL_REG 0x2c
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#define APCI3501_TIMER_STATUS_REG 0x30
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#define APCI3501_TIMER_IRQ_REG 0x34
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#define APCI3501_TIMER_WARN_RELOAD_REG 0x38
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#define APCI3501_TIMER_WARN_TIMEBASE_REG 0x3c
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#define APCI3501_DO_REG 0x40
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#define APCI3501_DI_REG 0x50
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@ -268,17 +276,11 @@ static irqreturn_t apci3501_interrupt(int irq, void *d)
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int i_temp;
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/* Disable Interrupt */
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ul_Command1 =
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inl(dev->iobase + APCI3501_WATCHDOG + APCI3501_TCW_PROG);
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ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG);
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ul_Command1 = (ul_Command1 & 0xFFFFF9FDul);
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outl(ul_Command1,
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dev->iobase + APCI3501_WATCHDOG + APCI3501_TCW_PROG);
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ui_Timer_AOWatchdog =
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inl(dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_IRQ) & 0x1;
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outl(ul_Command1, dev->iobase + APCI3501_TIMER_CTRL_REG);
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ui_Timer_AOWatchdog = inl(dev->iobase + APCI3501_TIMER_IRQ_REG) & 0x1;
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if ((!ui_Timer_AOWatchdog)) {
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comedi_error(dev, "IRQ from unknown source");
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return IRQ_NONE;
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@ -286,13 +288,10 @@ static irqreturn_t apci3501_interrupt(int irq, void *d)
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/* Enable Interrupt Send a signal to from kernel to user space */
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send_sig(SIGIO, devpriv->tsk_Current, 0);
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ul_Command1 =
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inl(dev->iobase + APCI3501_WATCHDOG + APCI3501_TCW_PROG);
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ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG);
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ul_Command1 = ((ul_Command1 & 0xFFFFF9FDul) | 1 << 1);
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outl(ul_Command1,
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dev->iobase + APCI3501_WATCHDOG + APCI3501_TCW_PROG);
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i_temp = inl(dev->iobase + APCI3501_WATCHDOG +
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APCI3501_TCW_TRIG_STATUS) & 0x1;
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outl(ul_Command1, dev->iobase + APCI3501_TIMER_CTRL_REG);
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i_temp = inl(dev->iobase + APCI3501_TIMER_STATUS_REG) & 0x1;
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return IRQ_HANDLED;
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}
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