tg3: Provide full regdump on tx timeout
The current amount of information provided in the output of a tx timeout is insufficient to determine a root cause. This patch replaces the terse, four-register status output with a more complete body of information. For PCIe devices, the full register space is dumped. For other devices, select registers are dumped instead. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Reviewed-by: Benjamin Li <benli@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>hifive-unleashed-5.1
Matt Carlson
David S. Miller
parent
4d42d417be
commit
97bd8e491d
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@ -4459,6 +4459,123 @@ static inline int tg3_irq_sync(struct tg3 *tp)
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return tp->irq_sync;
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}
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static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
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{
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int i;
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dst = (u32 *)((u8 *)dst + off);
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for (i = 0; i < len; i += sizeof(u32))
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*dst++ = tr32(off + i);
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}
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static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
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{
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tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
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tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
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tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
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tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
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tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
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tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
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tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
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tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
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tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
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tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
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tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
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tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
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tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
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tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
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tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
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tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
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tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
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tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
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tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
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if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX)
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tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
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tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
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tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
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tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
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tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
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tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
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tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
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tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
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tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
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if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
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tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
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tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
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tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
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}
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tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
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tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
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tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
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tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
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tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
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if (tp->tg3_flags & TG3_FLAG_NVRAM)
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tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
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}
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static void tg3_dump_state(struct tg3 *tp)
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{
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int i;
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u32 *regs;
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regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
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if (!regs) {
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netdev_err(tp->dev, "Failed allocating register dump buffer\n");
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return;
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}
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if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
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/* Read up to but not including private PCI registers */
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for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
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regs[i / sizeof(u32)] = tr32(i);
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} else
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tg3_dump_legacy_regs(tp, regs);
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for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
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if (!regs[i + 0] && !regs[i + 1] &&
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!regs[i + 2] && !regs[i + 3])
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continue;
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netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
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i * 4,
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regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
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}
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kfree(regs);
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for (i = 0; i < tp->irq_cnt; i++) {
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struct tg3_napi *tnapi = &tp->napi[i];
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/* SW status block */
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netdev_err(tp->dev,
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"%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
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i,
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tnapi->hw_status->status,
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tnapi->hw_status->status_tag,
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tnapi->hw_status->rx_jumbo_consumer,
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tnapi->hw_status->rx_consumer,
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tnapi->hw_status->rx_mini_consumer,
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tnapi->hw_status->idx[0].rx_producer,
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tnapi->hw_status->idx[0].tx_consumer);
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netdev_err(tp->dev,
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"%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
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i,
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tnapi->last_tag, tnapi->last_irq_tag,
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tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
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tnapi->rx_rcb_ptr,
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tnapi->prodring.rx_std_prod_idx,
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tnapi->prodring.rx_std_cons_idx,
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tnapi->prodring.rx_jmb_prod_idx,
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tnapi->prodring.rx_jmb_cons_idx);
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}
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}
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/* This is called whenever we suspect that the system chipset is re-
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* ordering the sequence of MMIO to the tx send mailbox. The symptom
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* is bogus tx completions. We try to recover by setting the
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@ -5516,21 +5633,13 @@ out:
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tg3_phy_start(tp);
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}
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static void tg3_dump_short_state(struct tg3 *tp)
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{
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netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
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tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
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netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
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tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
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}
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static void tg3_tx_timeout(struct net_device *dev)
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{
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struct tg3 *tp = netdev_priv(dev);
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if (netif_msg_tx_err(tp)) {
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netdev_err(dev, "transmit timed out, resetting\n");
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tg3_dump_short_state(tp);
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tg3_dump_state(tp);
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}
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schedule_work(&tp->reset_task);
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@ -9624,82 +9733,26 @@ static void tg3_set_rx_mode(struct net_device *dev)
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tg3_full_unlock(tp);
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}
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#define TG3_REGDUMP_LEN (32 * 1024)
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static int tg3_get_regs_len(struct net_device *dev)
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{
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return TG3_REGDUMP_LEN;
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return TG3_REG_BLK_SIZE;
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}
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static void tg3_get_regs(struct net_device *dev,
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struct ethtool_regs *regs, void *_p)
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{
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u32 *p = _p;
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struct tg3 *tp = netdev_priv(dev);
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u8 *orig_p = _p;
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int i;
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regs->version = 0;
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memset(p, 0, TG3_REGDUMP_LEN);
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memset(_p, 0, TG3_REG_BLK_SIZE);
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if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
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return;
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tg3_full_lock(tp, 0);
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#define __GET_REG32(reg) (*(p)++ = tr32(reg))
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#define GET_REG32_LOOP(base, len) \
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do { p = (u32 *)(orig_p + (base)); \
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for (i = 0; i < len; i += 4) \
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__GET_REG32((base) + i); \
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} while (0)
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#define GET_REG32_1(reg) \
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do { p = (u32 *)(orig_p + (reg)); \
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__GET_REG32((reg)); \
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} while (0)
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GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
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GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
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GET_REG32_LOOP(MAC_MODE, 0x4f0);
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GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
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GET_REG32_1(SNDDATAC_MODE);
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GET_REG32_LOOP(SNDBDS_MODE, 0x80);
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GET_REG32_LOOP(SNDBDI_MODE, 0x48);
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GET_REG32_1(SNDBDC_MODE);
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GET_REG32_LOOP(RCVLPC_MODE, 0x20);
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GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
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GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
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GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
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GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
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GET_REG32_1(RCVDCC_MODE);
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GET_REG32_LOOP(RCVBDI_MODE, 0x20);
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GET_REG32_LOOP(RCVCC_MODE, 0x14);
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GET_REG32_LOOP(RCVLSC_MODE, 0x08);
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GET_REG32_1(MBFREE_MODE);
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GET_REG32_LOOP(HOSTCC_MODE, 0x100);
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GET_REG32_LOOP(MEMARB_MODE, 0x10);
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GET_REG32_LOOP(BUFMGR_MODE, 0x58);
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GET_REG32_LOOP(RDMAC_MODE, 0x08);
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GET_REG32_LOOP(WDMAC_MODE, 0x08);
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GET_REG32_1(RX_CPU_MODE);
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GET_REG32_1(RX_CPU_STATE);
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GET_REG32_1(RX_CPU_PGMCTR);
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GET_REG32_1(RX_CPU_HWBKPT);
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GET_REG32_1(TX_CPU_MODE);
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GET_REG32_1(TX_CPU_STATE);
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GET_REG32_1(TX_CPU_PGMCTR);
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GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
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GET_REG32_LOOP(FTQ_RESET, 0x120);
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GET_REG32_LOOP(MSGINT_MODE, 0x0c);
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GET_REG32_1(DMAC_MODE);
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GET_REG32_LOOP(GRC_MODE, 0x4c);
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if (tp->tg3_flags & TG3_FLAG_NVRAM)
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GET_REG32_LOOP(NVRAM_CMD, 0x24);
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#undef __GET_REG32
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#undef GET_REG32_LOOP
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#undef GET_REG32_1
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tg3_dump_legacy_regs(tp, (u32 *)_p);
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tg3_full_unlock(tp);
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}
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@ -1954,6 +1954,8 @@
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#define TG3_PCIE_PL_LO_PHYCTL5 0x00000014
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#define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000
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#define TG3_REG_BLK_SIZE 0x00008000
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/* OTP bit definitions */
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#define TG3_OTP_AGCTGT_MASK 0x000000e0
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#define TG3_OTP_AGCTGT_SHIFT 1
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