cpufreq: Add i.MX7ULP cpufreq support
Add i.MX7ULP cpufreq driver support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>5.4-rM2-2.2.x-imx-squashed
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2ec28b6d49
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97e757069d
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@ -114,6 +114,14 @@ config ARM_IMX_CPUFREQ_DT
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If in doubt, say N.
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config ARM_IMX7ULP_CPUFREQ
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tristate "NXP i.MX7ULP cpufreq support"
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depends on ARCH_MXC
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help
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This adds cpufreq driver support for NXP i.MX7ULP series SoCs.
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If in doubt, say N.
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config ARM_KIRKWOOD_CPUFREQ
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def_bool MACH_KIRKWOOD
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help
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@ -57,6 +57,7 @@ obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o
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obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
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obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o
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obj-$(CONFIG_ARM_IMX_CPUFREQ_DT) += imx-cpufreq-dt.o
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obj-$(CONFIG_ARM_IMX7ULP_CPUFREQ) += imx7ulp-cpufreq.o
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obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o
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obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ) += mediatek-cpufreq.o
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obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o
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@ -0,0 +1,260 @@
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/*
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* Copyright 2017 NXP.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/cpu.h>
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#include <linux/cpufreq.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/pm_opp.h>
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#include <linux/pm_qos.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/suspend.h>
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#define MAX_RUN_FREQ 528000
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static struct clk *arm_clk;
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static struct clk *core_div;
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static struct clk *sys_sel;
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static struct clk *hsrun_sys_sel;
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static struct clk *hsrun_core;
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static struct clk *spll_pfd0;
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static struct clk *spll_sel;
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static struct clk *firc_clk;
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static struct clk *spll;
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static struct pm_qos_request pm_qos_hsrun;
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static struct regulator *arm_reg;
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static struct device *cpu_dev;
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static struct cpufreq_frequency_table *freq_table;
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static unsigned int transition_latency;
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static int imx7ulp_set_target(struct cpufreq_policy *policy, unsigned int index)
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{
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struct dev_pm_opp *opp;
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unsigned long freq_hz, volt, volt_old;
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unsigned int old_freq, new_freq;
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int ret;
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new_freq = freq_table[index].frequency;
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freq_hz = new_freq * 1000;
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old_freq = clk_get_rate(arm_clk) / 1000;
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if (new_freq == 0 || old_freq == 0)
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return -EINVAL;
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opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
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if (IS_ERR(opp)) {
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dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
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return PTR_ERR(opp);
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}
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volt = dev_pm_opp_get_voltage(opp);
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dev_pm_opp_put(opp);
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volt_old = regulator_get_voltage(arm_reg);
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dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
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old_freq / 1000, volt_old / 1000,
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new_freq / 1000, volt / 1000);
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/* Scaling up? scale voltage before frequency */
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if (new_freq > old_freq) {
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ret = regulator_set_voltage_tol(arm_reg, volt, 0);
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if (ret) {
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dev_err(cpu_dev, "failed to scale vddarm up: %d\n", ret);
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return ret;
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}
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}
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/* before changing pll_arm rate, change the arm_src's soure
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* to firc clk first.
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*/
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if (new_freq > MAX_RUN_FREQ) {
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pm_qos_add_request(&pm_qos_hsrun, PM_QOS_CPU_DMA_LATENCY, 0);
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/* change the RUN clock to firc */
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clk_set_parent(sys_sel, firc_clk);
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/* change the clock rate in HSRUN */
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clk_set_rate(spll, 480000000);
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clk_set_rate(spll_pfd0, new_freq * 1000);
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clk_set_parent(hsrun_sys_sel, spll_sel);
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clk_set_parent(arm_clk, hsrun_core);
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} else {
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/* change the HSRUN clock to firc */
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clk_set_parent(hsrun_sys_sel, firc_clk);
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/* change the clock rate in RUN */
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clk_set_rate(spll, 528000000);
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clk_set_rate(spll_pfd0, new_freq * 1000);
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clk_set_parent(sys_sel, spll_sel);
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clk_set_parent(arm_clk, core_div);
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if (old_freq > MAX_RUN_FREQ)
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pm_qos_remove_request(&pm_qos_hsrun);
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}
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/* scaling down? scaling voltage after frequency */
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if (new_freq < old_freq) {
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ret = regulator_set_voltage_tol(arm_reg, volt, 0);
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if (ret) {
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dev_warn(cpu_dev, "failed to scale vddarm down: %d\n", ret);
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ret = 0;
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}
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}
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return 0;
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}
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static int imx7ulp_cpufreq_init(struct cpufreq_policy *policy)
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{
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policy->clk = arm_clk;
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policy->cur = clk_get_rate(arm_clk) / 1000;
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policy->suspend_freq = freq_table[0].frequency;
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cpufreq_generic_init(policy, freq_table, transition_latency);
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return 0;
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}
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static struct cpufreq_driver imx7ulp_cpufreq_driver = {
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.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
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.verify = cpufreq_generic_frequency_table_verify,
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.target_index = imx7ulp_set_target,
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.get = cpufreq_generic_get,
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.init = imx7ulp_cpufreq_init,
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.name = "imx7ulp-cpufreq",
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.attr = cpufreq_generic_attr,
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#ifdef CONFIG_PM
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.suspend = cpufreq_generic_suspend,
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#endif
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};
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static int imx7ulp_cpufreq_probe(struct platform_device *pdev)
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{
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struct device_node *np;
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int ret;
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cpu_dev = get_cpu_device(0);
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if (!cpu_dev) {
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pr_err("failed to get cpu0 device\n");
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return -ENOENT;
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}
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np = of_node_get(cpu_dev->of_node);
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if (!np) {
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dev_err(cpu_dev, "failed to find the cpu0 node\n");
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return -ENOENT;
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}
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arm_clk = clk_get(cpu_dev, "arm");
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sys_sel = clk_get(cpu_dev, "sys_sel");
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core_div = clk_get(cpu_dev, "core_div");
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hsrun_sys_sel = clk_get(cpu_dev, "hsrun_sys_sel");
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hsrun_core = clk_get(cpu_dev, "hsrun_core");
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spll_pfd0 = clk_get(cpu_dev, "spll_pfd0");
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spll_sel = clk_get(cpu_dev, "spll_sel");
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firc_clk = clk_get(cpu_dev, "firc");
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spll = clk_get(cpu_dev, "spll");
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if (IS_ERR(arm_clk) || IS_ERR(sys_sel) || IS_ERR(spll_sel) ||
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IS_ERR(spll_sel) || IS_ERR(firc_clk) || IS_ERR(hsrun_sys_sel) ||
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IS_ERR(hsrun_core) || IS_ERR(spll)) {
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dev_err(cpu_dev, "failed to get cpu clock\n");
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ret = -ENOENT;
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goto put_clk;
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}
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arm_reg = regulator_get(cpu_dev, "arm");
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if (IS_ERR(arm_reg)) {
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dev_err(cpu_dev, "failed to get regulator\n");
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ret = -ENOENT;
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goto put_reg;
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}
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ret = dev_pm_opp_of_add_table(cpu_dev);
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if (ret < 0) {
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dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
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goto put_reg;
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}
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ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
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if (ret) {
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dev_err(cpu_dev, "failed to init cpufreq table\n");
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goto put_reg;
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}
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if (of_property_read_u32(np, "clock-latency", &transition_latency))
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transition_latency = CPUFREQ_ETERNAL;
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ret = cpufreq_register_driver(&imx7ulp_cpufreq_driver);
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if (ret) {
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dev_err(cpu_dev, "failed to register driver\n");
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goto free_opp_table;
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}
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return 0;
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free_opp_table:
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dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
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put_reg:
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regulator_put(arm_reg);
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put_clk:
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if (!IS_ERR(arm_clk))
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clk_put(arm_clk);
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if (!IS_ERR(sys_sel))
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clk_put(sys_sel);
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if (!IS_ERR(core_div))
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clk_put(core_div);
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if (!IS_ERR(hsrun_sys_sel))
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clk_put(hsrun_sys_sel);
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if (!IS_ERR(hsrun_core))
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clk_put(hsrun_core);
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if (!IS_ERR(spll_pfd0))
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clk_put(spll_pfd0);
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if (!IS_ERR(spll_sel))
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clk_put(spll_sel);
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if (!IS_ERR(firc_clk))
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clk_put(firc_clk);
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if (!IS_ERR(spll))
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clk_put(spll);
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return ret;
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}
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static int imx7ulp_cpufreq_remove(struct platform_device *pdev)
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{
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cpufreq_unregister_driver(&imx7ulp_cpufreq_driver);
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dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
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regulator_put(arm_reg);
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clk_put(arm_clk);
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clk_put(sys_sel);
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clk_put(core_div);
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clk_put(hsrun_sys_sel);
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clk_put(hsrun_core);
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clk_put(spll_pfd0);
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clk_put(spll_sel);
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clk_put(firc_clk);
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clk_put(spll);
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return 0;
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}
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static struct platform_driver imx7ulp_cpufreq_platdrv = {
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.driver = {
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.name = "imx7ulp-cpufreq",
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.owner = THIS_MODULE,
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},
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.probe = imx7ulp_cpufreq_probe,
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.remove = imx7ulp_cpufreq_remove,
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};
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module_platform_driver(imx7ulp_cpufreq_platdrv);
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MODULE_DESCRIPTION("NXP i.MX7ULP cpufreq driver");
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MODULE_LICENSE("GPL v2");
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