pinctrl: sh-pfc: Updates for v5.5
- Split R-Car H3 support in two independent drivers, - Miscellaneous fixes and cleanups. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCXhZAzwAKCRCKwlD9ZEnx cHpkAQCrz7kaC9rIRMO9eRZLV6sX6M+PeFw3DXKjm8N0qxG8hQD6AtKl5Gl/CAoq RSO/0PpVIp97A904MJt+EOkX6eSBhwc= =LEq1 -----END PGP SIGNATURE----- Merge tag 'sh-pfc-for-v5.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v5.5 - Split R-Car H3 support in two independent drivers, - Miscellaneous fixes and cleanups.
This commit is contained in:
commit
97f7d41ff8
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@ -112,12 +112,6 @@ enum {
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GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A,
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GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA,
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/* SSU */
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GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD,
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GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF,
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GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD,
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GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF,
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/* SCIF */
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GPIO_FN_SCK0, GPIO_FN_SCK1, GPIO_FN_SCK2, GPIO_FN_SCK3,
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GPIO_FN_RXD0, GPIO_FN_RXD1, GPIO_FN_RXD2, GPIO_FN_RXD3,
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@ -78,8 +78,15 @@ enum {
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GPIO_FN_WDTOVF,
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/* CAN */
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GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1,
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GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1, GPIO_FN_CRX0_CRX1_CRX2,
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GPIO_FN_CTX2, GPIO_FN_CRX2,
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GPIO_FN_CTX1, GPIO_FN_CRX1,
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GPIO_FN_CTX0, GPIO_FN_CRX0,
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GPIO_FN_CTX0_CTX1, GPIO_FN_CRX0_CRX1,
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GPIO_FN_CTX0_CTX1_CTX2, GPIO_FN_CRX0_CRX1_CRX2,
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GPIO_FN_CTX2_PJ21, GPIO_FN_CRX2_PJ20,
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GPIO_FN_CTX1_PJ23, GPIO_FN_CRX1_PJ22,
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GPIO_FN_CTX0_CTX1_PJ23, GPIO_FN_CRX0_CRX1_PJ22,
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GPIO_FN_CTX0_CTX1_CTX2_PJ21, GPIO_FN_CRX0_CRX1_CRX2_PJ20,
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/* DMAC */
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GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0,
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@ -119,12 +126,6 @@ enum {
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GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A,
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GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA,
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/* SSU */
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GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD,
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GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF,
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GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD,
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GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF,
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/* SCIF */
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GPIO_FN_SCK0, GPIO_FN_RXD0, GPIO_FN_TXD0,
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GPIO_FN_SCK1, GPIO_FN_RXD1, GPIO_FN_TXD1, GPIO_FN_RTS1, GPIO_FN_CTS1,
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@ -1229,8 +1229,8 @@ static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl,
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pinctrl_add_gpio_range(rza1_pctl->pctl, range);
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dev_info(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n",
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chip->label, chip->ngpio);
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dev_dbg(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n",
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chip->label, chip->ngpio);
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return 0;
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}
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@ -26,8 +26,9 @@ config PINCTRL_SH_PFC
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select PINCTRL_PFC_R8A7792 if ARCH_R8A7792
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select PINCTRL_PFC_R8A7793 if ARCH_R8A7793
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select PINCTRL_PFC_R8A7794 if ARCH_R8A7794
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select PINCTRL_PFC_R8A7795 if ARCH_R8A7795
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select PINCTRL_PFC_R8A77960 if ARCH_R8A77960 || ARCH_R8A7796
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select PINCTRL_PFC_R8A77950 if ARCH_R8A77950 || ARCH_R8A7795
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select PINCTRL_PFC_R8A77951 if ARCH_R8A77951 || ARCH_R8A7795
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select PINCTRL_PFC_R8A77960 if ARCH_R8A77960
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select PINCTRL_PFC_R8A77961 if ARCH_R8A77961
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select PINCTRL_PFC_R8A77965 if ARCH_R8A77965
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select PINCTRL_PFC_R8A77970 if ARCH_R8A77970
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@ -115,8 +116,11 @@ config PINCTRL_PFC_R8A7793
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config PINCTRL_PFC_R8A7794
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bool "R-Car E2 pin control support" if COMPILE_TEST
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config PINCTRL_PFC_R8A7795
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bool "R-Car H3 pin control support" if COMPILE_TEST
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config PINCTRL_PFC_R8A77950
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bool "R-Car H3 ES1.x pin control support" if COMPILE_TEST
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config PINCTRL_PFC_R8A77951
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bool "R-Car H3 ES2.0+ pin control support" if COMPILE_TEST
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config PINCTRL_PFC_R8A77960
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bool "R-Car M3-W pin control support" if COMPILE_TEST
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@ -18,8 +18,8 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o
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obj-$(CONFIG_PINCTRL_PFC_R8A77950) += pfc-r8a77950.o
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obj-$(CONFIG_PINCTRL_PFC_R8A77951) += pfc-r8a77951.o
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obj-$(CONFIG_PINCTRL_PFC_R8A77960) += pfc-r8a7796.o
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obj-$(CONFIG_PINCTRL_PFC_R8A77961) += pfc-r8a7796.o
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obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
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@ -23,6 +23,7 @@
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#include <linux/platform_device.h>
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#include <linux/psci.h>
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#include <linux/slab.h>
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#include <linux/sys_soc.h>
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#include "core.h"
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@ -568,18 +569,18 @@ static const struct of_device_id sh_pfc_of_table[] = {
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.data = &r8a7794_pinmux_info,
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},
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A7795
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/* Both r8a7795 entries must be present to make sanity checks work */
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#ifdef CONFIG_PINCTRL_PFC_R8A77950
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{
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.compatible = "renesas,pfc-r8a7795",
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.data = &r8a7795_pinmux_info,
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.data = &r8a77950_pinmux_info,
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},
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#ifdef DEBUG
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A77951
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{
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/* For sanity checks only (nothing matches against this) */
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.compatible = "renesas,pfc-r8a77950", /* R-Car H3 ES1.0 */
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.data = &r8a7795es1_pinmux_info,
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.compatible = "renesas,pfc-r8a7795",
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.data = &r8a77951_pinmux_info,
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},
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#endif /* DEBUG */
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A77960
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{
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@ -886,19 +887,49 @@ static void __init sh_pfc_check_driver(const struct platform_driver *pdrv)
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static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}
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#endif /* !DEBUG */
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#ifdef CONFIG_OF
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static const void *sh_pfc_quirk_match(void)
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{
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#if defined(CONFIG_PINCTRL_PFC_R8A77950) || \
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defined(CONFIG_PINCTRL_PFC_R8A77951)
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const struct soc_device_attribute *match;
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static const struct soc_device_attribute quirks[] = {
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{
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.soc_id = "r8a7795", .revision = "ES1.*",
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.data = &r8a77950_pinmux_info,
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},
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{
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.soc_id = "r8a7795",
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.data = &r8a77951_pinmux_info,
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},
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{ /* sentinel */ }
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};
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match = soc_device_match(quirks);
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if (match)
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return match->data ?: ERR_PTR(-ENODEV);
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#endif /* CONFIG_PINCTRL_PFC_R8A77950 || CONFIG_PINCTRL_PFC_R8A77951 */
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return NULL;
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}
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#endif /* CONFIG_OF */
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static int sh_pfc_probe(struct platform_device *pdev)
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{
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#ifdef CONFIG_OF
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struct device_node *np = pdev->dev.of_node;
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#endif
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const struct sh_pfc_soc_info *info;
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struct sh_pfc *pfc;
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int ret;
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#ifdef CONFIG_OF
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if (np)
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info = of_device_get_match_data(&pdev->dev);
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else
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if (pdev->dev.of_node) {
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info = sh_pfc_quirk_match();
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if (IS_ERR(info))
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return PTR_ERR(info);
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if (!info)
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info = of_device_get_match_data(&pdev->dev);
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} else
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#endif
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info = (const void *)platform_get_device_id(pdev)->driver_data;
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@ -386,12 +386,11 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
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}
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/* Register the function GPIOs chip. */
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if (pfc->info->nr_func_gpios == 0)
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return 0;
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chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
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if (IS_ERR(chip))
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return PTR_ERR(chip);
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if (pfc->info->nr_func_gpios) {
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chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
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if (IS_ERR(chip))
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return PTR_ERR(chip);
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}
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#endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
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return 0;
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@ -2305,7 +2305,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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FN_ATAG0_A, 0, FN_REMOCON_B, 0,
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/* IP0_11_8 [4] */
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FN_SD1_DAT2_A, FN_MMC_D2, 0, FN_BS,
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FN_ATADIR0_A, 0, FN_SDSELF_B, 0,
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FN_ATADIR0_A, 0, FN_SDSELF_A, 0,
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FN_PWM4_B, 0, 0, 0,
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0, 0, 0, 0,
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/* IP0_7_5 [3] */
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@ -2349,7 +2349,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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FN_TS_SDAT0_A, 0, 0, 0,
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0, 0, 0, 0,
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/* IP1_10_8 [3] */
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FN_SD1_CLK_B, FN_MMC_D6, 0, FN_A24,
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FN_SD1_CD_A, FN_MMC_D6, 0, FN_A24,
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FN_DREQ1_A, 0, FN_HRX0_B, FN_TS_SPSYNC0_A,
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/* IP1_7_5 [3] */
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FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A,
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* R8A7795 ES1.x processor support - PFC hardware block.
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* R8A77950 processor support - PFC hardware block.
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*
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* Copyright (C) 2015-2017 Renesas Electronics Corporation
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*/
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@ -5562,8 +5562,8 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
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{ /* sentinel */ },
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};
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static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
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u32 *pocctrl)
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static int r8a77950_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
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u32 *pocctrl)
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{
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int bit = -EINVAL;
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@ -5820,8 +5820,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
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{ /* sentinel */ },
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};
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static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc,
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unsigned int pin)
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static unsigned int r8a77950_pinmux_get_bias(struct sh_pfc *pfc,
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unsigned int pin)
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{
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const struct pinmux_bias_reg *reg;
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unsigned int bit;
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@ -5838,8 +5838,8 @@ static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc,
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return PIN_CONFIG_BIAS_PULL_DOWN;
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}
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static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
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unsigned int bias)
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static void r8a77950_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
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unsigned int bias)
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{
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const struct pinmux_bias_reg *reg;
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u32 enable, updown;
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@ -5861,15 +5861,15 @@ static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
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sh_pfc_write(pfc, reg->puen, enable);
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}
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static const struct sh_pfc_soc_operations r8a7795es1_pinmux_ops = {
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.pin_to_pocctrl = r8a7795es1_pin_to_pocctrl,
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.get_bias = r8a7795es1_pinmux_get_bias,
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.set_bias = r8a7795es1_pinmux_set_bias,
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static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = {
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.pin_to_pocctrl = r8a77950_pin_to_pocctrl,
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.get_bias = r8a77950_pinmux_get_bias,
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.set_bias = r8a77950_pinmux_set_bias,
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};
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const struct sh_pfc_soc_info r8a7795es1_pinmux_info = {
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const struct sh_pfc_soc_info r8a77950_pinmux_info = {
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.name = "r8a77950_pfc",
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.ops = &r8a7795es1_pinmux_ops,
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.ops = &r8a77950_pinmux_ops,
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.unlock_reg = 0xe6060000, /* PMMR */
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.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* R8A7795 ES2.0+ processor support - PFC hardware block.
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* R8A77951 processor support - PFC hardware block.
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*
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* Copyright (C) 2015-2019 Renesas Electronics Corporation
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*/
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@ -5915,7 +5915,8 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
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{ /* sentinel */ },
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};
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static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
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static int r8a77951_pin_to_pocctrl(struct sh_pfc *pfc,
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unsigned int pin, u32 *pocctrl)
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{
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int bit = -EINVAL;
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|
@ -6172,8 +6173,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
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{ /* sentinel */ },
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};
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static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
|
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unsigned int pin)
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static unsigned int r8a77951_pinmux_get_bias(struct sh_pfc *pfc,
|
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unsigned int pin)
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{
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const struct pinmux_bias_reg *reg;
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unsigned int bit;
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|
@ -6190,8 +6191,8 @@ static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
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return PIN_CONFIG_BIAS_PULL_DOWN;
|
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}
|
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|
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static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
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unsigned int bias)
|
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static void r8a77951_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
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unsigned int bias)
|
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{
|
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const struct pinmux_bias_reg *reg;
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u32 enable, updown;
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|
@ -6213,29 +6214,15 @@ static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
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sh_pfc_write(pfc, reg->puen, enable);
|
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}
|
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|
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static const struct soc_device_attribute r8a7795es1[] = {
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{ .soc_id = "r8a7795", .revision = "ES1.*" },
|
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{ /* sentinel */ }
|
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static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = {
|
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.pin_to_pocctrl = r8a77951_pin_to_pocctrl,
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.get_bias = r8a77951_pinmux_get_bias,
|
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.set_bias = r8a77951_pinmux_set_bias,
|
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};
|
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|
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static int r8a7795_pinmux_init(struct sh_pfc *pfc)
|
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{
|
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if (soc_device_match(r8a7795es1))
|
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pfc->info = &r8a7795es1_pinmux_info;
|
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|
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return 0;
|
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}
|
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|
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static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
|
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.init = r8a7795_pinmux_init,
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.pin_to_pocctrl = r8a7795_pin_to_pocctrl,
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.get_bias = r8a7795_pinmux_get_bias,
|
||||
.set_bias = r8a7795_pinmux_set_bias,
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info r8a7795_pinmux_info = {
|
||||
const struct sh_pfc_soc_info r8a77951_pinmux_info = {
|
||||
.name = "r8a77951_pfc",
|
||||
.ops = &r8a7795_pinmux_ops,
|
||||
.ops = &r8a77951_pinmux_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
|
@ -5998,7 +5998,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
|
||||
{ PIN_DU_DOTCLKIN3, 28, 2 }, /* DU_DOTCLKIN3 */
|
||||
{ PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
|
||||
{ PIN_FSCLKST, 20, 2 }, /* FSCLKST */
|
||||
{ PIN_TMS, 4, 2 }, /* TMS */
|
||||
} },
|
||||
|
@ -6254,8 +6254,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
|
||||
[ 0] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
|
||||
[ 1] = SH_PFC_PIN_NONE,
|
||||
[ 0] = SH_PFC_PIN_NONE,
|
||||
[ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
|
||||
[ 2] = PIN_FSCLKST, /* FSCLKST */
|
||||
[ 3] = PIN_EXTALR, /* EXTALR*/
|
||||
[ 4] = PIN_TRST_N, /* TRST# */
|
||||
|
|
|
@ -497,17 +497,15 @@ enum {
|
|||
SD_WP_MARK, SD_CLK_MARK, SD_CMD_MARK,
|
||||
CRX0_MARK, CRX1_MARK,
|
||||
CTX0_MARK, CTX1_MARK,
|
||||
CRX0_CRX1_MARK, CTX0_CTX1_MARK,
|
||||
|
||||
PWM1A_MARK, PWM1B_MARK, PWM1C_MARK, PWM1D_MARK,
|
||||
PWM1E_MARK, PWM1F_MARK, PWM1G_MARK, PWM1H_MARK,
|
||||
PWM2A_MARK, PWM2B_MARK, PWM2C_MARK, PWM2D_MARK,
|
||||
PWM2E_MARK, PWM2F_MARK, PWM2G_MARK, PWM2H_MARK,
|
||||
IERXD_MARK, IETXD_MARK,
|
||||
CRX0_CRX1_MARK,
|
||||
WDTOVF_MARK,
|
||||
|
||||
CRX0X1_MARK,
|
||||
|
||||
/* DMAC */
|
||||
TEND0_MARK, DACK0_MARK, DREQ0_MARK,
|
||||
TEND1_MARK, DACK1_MARK, DREQ1_MARK,
|
||||
|
@ -995,12 +993,12 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_DATA(PJ3_DATA, PJ3MD_00),
|
||||
PINMUX_DATA(CRX1_MARK, PJ3MD_01),
|
||||
PINMUX_DATA(CRX0X1_MARK, PJ3MD_10),
|
||||
PINMUX_DATA(CRX0_CRX1_MARK, PJ3MD_10),
|
||||
PINMUX_DATA(IRQ1_PJ_MARK, PJ3MD_11),
|
||||
|
||||
PINMUX_DATA(PJ2_DATA, PJ2MD_000),
|
||||
PINMUX_DATA(CTX1_MARK, PJ2MD_001),
|
||||
PINMUX_DATA(CRX0_CRX1_MARK, PJ2MD_010),
|
||||
PINMUX_DATA(CTX0_CTX1_MARK, PJ2MD_010),
|
||||
PINMUX_DATA(CS2_MARK, PJ2MD_011),
|
||||
PINMUX_DATA(SCK0_MARK, PJ2MD_100),
|
||||
PINMUX_DATA(LCD_M_DISP_MARK, PJ2MD_101),
|
||||
|
@ -1245,6 +1243,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
|
|||
GPIO_FN(CTX1),
|
||||
GPIO_FN(CRX1),
|
||||
GPIO_FN(CTX0),
|
||||
GPIO_FN(CTX0_CTX1),
|
||||
GPIO_FN(CRX0),
|
||||
GPIO_FN(CRX0_CRX1),
|
||||
|
||||
|
@ -2020,18 +2019,18 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
|
||||
{ PINMUX_CFG_REG("PKIOR0", 0xfffe3932, 16, 1, GROUP(
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PJ11_IN, PJ11_OUT,
|
||||
PJ10_IN, PJ10_OUT,
|
||||
PJ9_IN, PJ9_OUT,
|
||||
PJ8_IN, PJ8_OUT,
|
||||
PJ7_IN, PJ7_OUT,
|
||||
PJ6_IN, PJ6_OUT,
|
||||
PJ5_IN, PJ5_OUT,
|
||||
PJ4_IN, PJ4_OUT,
|
||||
PJ3_IN, PJ3_OUT,
|
||||
PJ2_IN, PJ2_OUT,
|
||||
PJ1_IN, PJ1_OUT,
|
||||
PJ0_IN, PJ0_OUT ))
|
||||
PK11_IN, PK11_OUT,
|
||||
PK10_IN, PK10_OUT,
|
||||
PK9_IN, PK9_OUT,
|
||||
PK8_IN, PK8_OUT,
|
||||
PK7_IN, PK7_OUT,
|
||||
PK6_IN, PK6_OUT,
|
||||
PK5_IN, PK5_OUT,
|
||||
PK4_IN, PK4_OUT,
|
||||
PK3_IN, PK3_OUT,
|
||||
PK2_IN, PK2_OUT,
|
||||
PK1_IN, PK1_OUT,
|
||||
PK0_IN, PK0_OUT ))
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
|
|
@ -737,13 +737,12 @@ enum {
|
|||
CRX0_MARK, CTX0_MARK,
|
||||
CRX1_MARK, CTX1_MARK,
|
||||
CRX2_MARK, CTX2_MARK,
|
||||
CRX0_CRX1_MARK,
|
||||
CRX0_CRX1_CRX2_MARK,
|
||||
CTX0CTX1CTX2_MARK,
|
||||
CRX0_CRX1_MARK, CTX0_CTX1_MARK,
|
||||
CRX0_CRX1_CRX2_MARK, CTX0_CTX1_CTX2_MARK,
|
||||
CRX1_PJ22_MARK, CTX1_PJ23_MARK,
|
||||
CRX2_PJ20_MARK, CTX2_PJ21_MARK,
|
||||
CRX0CRX1_PJ22_MARK,
|
||||
CRX0CRX1CRX2_PJ20_MARK,
|
||||
CRX0_CRX1_PJ22_MARK, CTX0_CTX1_PJ23_MARK,
|
||||
CRX0_CRX1_CRX2_PJ20_MARK, CTX0_CTX1_CTX2_PJ21_MARK,
|
||||
|
||||
/* VDC */
|
||||
DV_CLK_MARK,
|
||||
|
@ -821,6 +820,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_DATA(CS3_MARK, PC8MD_001),
|
||||
PINMUX_DATA(TXD7_MARK, PC8MD_010),
|
||||
PINMUX_DATA(CTX1_MARK, PC8MD_011),
|
||||
PINMUX_DATA(CTX0_CTX1_MARK, PC8MD_100),
|
||||
|
||||
PINMUX_DATA(PC7_DATA, PC7MD_000),
|
||||
PINMUX_DATA(CKE_MARK, PC7MD_001),
|
||||
|
@ -833,11 +833,12 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_DATA(CAS_MARK, PC6MD_001),
|
||||
PINMUX_DATA(SCK7_MARK, PC6MD_010),
|
||||
PINMUX_DATA(CTX0_MARK, PC6MD_011),
|
||||
PINMUX_DATA(CTX0_CTX1_CTX2_MARK, PC6MD_100),
|
||||
|
||||
PINMUX_DATA(PC5_DATA, PC5MD_000),
|
||||
PINMUX_DATA(RAS_MARK, PC5MD_001),
|
||||
PINMUX_DATA(CRX0_MARK, PC5MD_011),
|
||||
PINMUX_DATA(CTX0CTX1CTX2_MARK, PC5MD_100),
|
||||
PINMUX_DATA(CTX0_CTX1_CTX2_MARK, PC5MD_100),
|
||||
PINMUX_DATA(IRQ0_PC_MARK, PC5MD_101),
|
||||
|
||||
PINMUX_DATA(PC4_DATA, PC4MD_00),
|
||||
|
@ -1289,30 +1290,32 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_DATA(LCD_DATA23_PJ23_MARK, PJ23MD_010),
|
||||
PINMUX_DATA(LCD_TCON6_MARK, PJ23MD_011),
|
||||
PINMUX_DATA(IRQ3_PJ_MARK, PJ23MD_100),
|
||||
PINMUX_DATA(CTX1_MARK, PJ23MD_101),
|
||||
PINMUX_DATA(CTX1_PJ23_MARK, PJ23MD_101),
|
||||
PINMUX_DATA(CTX0_CTX1_PJ23_MARK, PJ23MD_110),
|
||||
|
||||
PINMUX_DATA(PJ22_DATA, PJ22MD_000),
|
||||
PINMUX_DATA(DV_DATA22_MARK, PJ22MD_001),
|
||||
PINMUX_DATA(LCD_DATA22_PJ22_MARK, PJ22MD_010),
|
||||
PINMUX_DATA(LCD_TCON5_MARK, PJ22MD_011),
|
||||
PINMUX_DATA(IRQ2_PJ_MARK, PJ22MD_100),
|
||||
PINMUX_DATA(CRX1_MARK, PJ22MD_101),
|
||||
PINMUX_DATA(CRX0_CRX1_MARK, PJ22MD_110),
|
||||
PINMUX_DATA(CRX1_PJ22_MARK, PJ22MD_101),
|
||||
PINMUX_DATA(CRX0_CRX1_PJ22_MARK, PJ22MD_110),
|
||||
|
||||
PINMUX_DATA(PJ21_DATA, PJ21MD_000),
|
||||
PINMUX_DATA(DV_DATA21_MARK, PJ21MD_001),
|
||||
PINMUX_DATA(LCD_DATA21_PJ21_MARK, PJ21MD_010),
|
||||
PINMUX_DATA(LCD_TCON4_MARK, PJ21MD_011),
|
||||
PINMUX_DATA(IRQ1_PJ_MARK, PJ21MD_100),
|
||||
PINMUX_DATA(CTX2_MARK, PJ21MD_101),
|
||||
PINMUX_DATA(CTX2_PJ21_MARK, PJ21MD_101),
|
||||
PINMUX_DATA(CTX0_CTX1_CTX2_PJ21_MARK, PJ21MD_110),
|
||||
|
||||
PINMUX_DATA(PJ20_DATA, PJ20MD_000),
|
||||
PINMUX_DATA(DV_DATA20_MARK, PJ20MD_001),
|
||||
PINMUX_DATA(LCD_DATA20_PJ20_MARK, PJ20MD_010),
|
||||
PINMUX_DATA(LCD_TCON3_MARK, PJ20MD_011),
|
||||
PINMUX_DATA(IRQ0_PJ_MARK, PJ20MD_100),
|
||||
PINMUX_DATA(CRX2_MARK, PJ20MD_101),
|
||||
PINMUX_DATA(CRX0CRX1CRX2_PJ20_MARK, PJ20MD_110),
|
||||
PINMUX_DATA(CRX2_PJ20_MARK, PJ20MD_101),
|
||||
PINMUX_DATA(CRX0_CRX1_CRX2_PJ20_MARK, PJ20MD_110),
|
||||
|
||||
PINMUX_DATA(PJ19_DATA, PJ19MD_000),
|
||||
PINMUX_DATA(DV_DATA19_MARK, PJ19MD_001),
|
||||
|
@ -1663,12 +1666,24 @@ static const struct pinmux_func pinmux_func_gpios[] = {
|
|||
GPIO_FN(WDTOVF),
|
||||
|
||||
/* CAN */
|
||||
GPIO_FN(CTX2),
|
||||
GPIO_FN(CRX2),
|
||||
GPIO_FN(CTX1),
|
||||
GPIO_FN(CRX1),
|
||||
GPIO_FN(CTX0),
|
||||
GPIO_FN(CRX0),
|
||||
GPIO_FN(CTX0_CTX1),
|
||||
GPIO_FN(CRX0_CRX1),
|
||||
GPIO_FN(CTX0_CTX1_CTX2),
|
||||
GPIO_FN(CRX0_CRX1_CRX2),
|
||||
GPIO_FN(CTX2_PJ21),
|
||||
GPIO_FN(CRX2_PJ20),
|
||||
GPIO_FN(CTX1_PJ23),
|
||||
GPIO_FN(CRX1_PJ22),
|
||||
GPIO_FN(CTX0_CTX1_PJ23),
|
||||
GPIO_FN(CRX0_CRX1_PJ22),
|
||||
GPIO_FN(CTX0_CTX1_CTX2_PJ21),
|
||||
GPIO_FN(CRX0_CRX1_CRX2_PJ20),
|
||||
|
||||
/* DMAC */
|
||||
GPIO_FN(TEND0),
|
||||
|
|
|
@ -318,8 +318,8 @@ extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
|
|||
extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77950_pinmux_info __weak;
|
||||
extern const struct sh_pfc_soc_info r8a77951_pinmux_info __weak;
|
||||
extern const struct sh_pfc_soc_info r8a77960_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77961_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
|
||||
|
|
Loading…
Reference in a new issue