drm/i915/chv: Don't use PCS group access reads
All PCS groups access reads return 0xffffffff, so we can't use group access for RMW cycles. Instead target each spline separately. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> [danvet: Fight conflict with misplaced ; .... ARGH!] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -659,6 +659,13 @@ enum punit_power_well {
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#define DPIO_PCS_TX_LANE1_RESET (1<<7)
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#define DPIO_PCS_TX_LANE1_RESET (1<<7)
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#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
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#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
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#define _VLV_PCS01_DW0_CH0 0x200
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#define _VLV_PCS23_DW0_CH0 0x400
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#define _VLV_PCS01_DW0_CH1 0x2600
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#define _VLV_PCS23_DW0_CH1 0x2800
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#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
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#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
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#define _VLV_PCS_DW1_CH0 0x8204
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#define _VLV_PCS_DW1_CH0 0x8204
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#define _VLV_PCS_DW1_CH1 0x8404
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#define _VLV_PCS_DW1_CH1 0x8404
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#define CHV_PCS_REQ_SOFTRESET_EN (1<<23)
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#define CHV_PCS_REQ_SOFTRESET_EN (1<<23)
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@ -668,6 +675,13 @@ enum punit_power_well {
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#define DPIO_PCS_CLK_SOFT_RESET (1<<5)
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#define DPIO_PCS_CLK_SOFT_RESET (1<<5)
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#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
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#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
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#define _VLV_PCS01_DW1_CH0 0x204
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#define _VLV_PCS23_DW1_CH0 0x404
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#define _VLV_PCS01_DW1_CH1 0x2604
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#define _VLV_PCS23_DW1_CH1 0x2804
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#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
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#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
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#define _VLV_PCS_DW8_CH0 0x8220
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#define _VLV_PCS_DW8_CH0 0x8220
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#define _VLV_PCS_DW8_CH1 0x8420
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#define _VLV_PCS_DW8_CH1 0x8420
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#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
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#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
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@ -1882,13 +1882,21 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->dpio_lock);
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/* Propagate soft reset to data lane reset */
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/* Propagate soft reset to data lane reset */
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
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val |= CHV_PCS_REQ_SOFTRESET_EN;
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val |= CHV_PCS_REQ_SOFTRESET_EN;
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vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
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vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
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val |= CHV_PCS_REQ_SOFTRESET_EN;
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vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
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val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
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val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
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vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
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vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
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val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
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vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
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mutex_unlock(&dev_priv->dpio_lock);
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mutex_unlock(&dev_priv->dpio_lock);
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}
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}
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@ -2027,13 +2035,21 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->dpio_lock);
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/* Deassert soft data lane reset*/
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/* Deassert soft data lane reset*/
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
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val |= CHV_PCS_REQ_SOFTRESET_EN;
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val |= CHV_PCS_REQ_SOFTRESET_EN;
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vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
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vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
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val |= CHV_PCS_REQ_SOFTRESET_EN;
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vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
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val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
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val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
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vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
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vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
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val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
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vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
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/* Program Tx lane latency optimal setting*/
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/* Program Tx lane latency optimal setting*/
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for (i = 0; i < 4; i++) {
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for (i = 0; i < 4; i++) {
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@ -1259,13 +1259,21 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder)
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->dpio_lock);
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/* Propagate soft reset to data lane reset */
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/* Propagate soft reset to data lane reset */
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
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val |= CHV_PCS_REQ_SOFTRESET_EN;
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val |= CHV_PCS_REQ_SOFTRESET_EN;
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vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
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vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
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val |= CHV_PCS_REQ_SOFTRESET_EN;
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vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
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val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
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val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
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vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
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vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
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val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
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vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
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mutex_unlock(&dev_priv->dpio_lock);
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mutex_unlock(&dev_priv->dpio_lock);
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}
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}
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@ -1285,13 +1293,21 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->dpio_lock);
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/* Deassert soft data lane reset*/
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/* Deassert soft data lane reset*/
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
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val |= CHV_PCS_REQ_SOFTRESET_EN;
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val |= CHV_PCS_REQ_SOFTRESET_EN;
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vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
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vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
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val |= CHV_PCS_REQ_SOFTRESET_EN;
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vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
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val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
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val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
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vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
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vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
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val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
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vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
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/* Program Tx latency optimal setting */
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/* Program Tx latency optimal setting */
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for (i = 0; i < 4; i++) {
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for (i = 0; i < 4; i++) {
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