mtd: spinand: Use the spi-mem dirmap API
Make use of the spi-mem direct mapping API to let advanced controllers optimize read/write operations when they support direct mapping. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Stefan Roese <sr@denx.de>hifive-unleashed-5.2
Boris Brezillon
Miquel Raynal
parent
9e98c678c2
commit
981d1aa069
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@ -19,21 +19,6 @@
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#include <linux/spi/spi.h>
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#include <linux/spi/spi-mem.h>
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static void spinand_cache_op_adjust_colum(struct spinand_device *spinand,
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const struct nand_page_io_req *req,
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u16 *column)
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{
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struct nand_device *nand = spinand_to_nand(spinand);
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unsigned int shift;
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if (nand->memorg.planes_per_lun < 2)
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return;
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/* The plane number is passed in MSB just above the column address */
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shift = fls(nand->memorg.pagesize);
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*column |= req->pos.plane << shift;
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}
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static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
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{
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struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg,
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@ -227,27 +212,21 @@ static int spinand_load_page_op(struct spinand_device *spinand,
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static int spinand_read_from_cache_op(struct spinand_device *spinand,
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const struct nand_page_io_req *req)
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{
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struct spi_mem_op op = *spinand->op_templates.read_cache;
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struct nand_device *nand = spinand_to_nand(spinand);
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struct mtd_info *mtd = nanddev_to_mtd(nand);
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struct nand_page_io_req adjreq = *req;
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struct spi_mem_dirmap_desc *rdesc;
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unsigned int nbytes = 0;
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void *buf = NULL;
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u16 column = 0;
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int ret;
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ssize_t ret;
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if (req->datalen) {
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adjreq.datalen = nanddev_page_size(nand);
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adjreq.dataoffs = 0;
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adjreq.databuf.in = spinand->databuf;
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buf = spinand->databuf;
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nbytes = adjreq.datalen;
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nbytes = nanddev_page_size(nand);
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column = 0;
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}
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if (req->ooblen) {
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adjreq.ooblen = nanddev_per_page_oobsize(nand);
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adjreq.ooboffs = 0;
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adjreq.oobbuf.in = spinand->oobbuf;
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nbytes += nanddev_per_page_oobsize(nand);
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if (!buf) {
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buf = spinand->oobbuf;
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@ -255,28 +234,19 @@ static int spinand_read_from_cache_op(struct spinand_device *spinand,
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}
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}
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spinand_cache_op_adjust_colum(spinand, &adjreq, &column);
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op.addr.val = column;
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rdesc = spinand->dirmaps[req->pos.plane].rdesc;
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/*
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* Some controllers are limited in term of max RX data size. In this
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* case, just repeat the READ_CACHE operation after updating the
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* column.
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*/
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while (nbytes) {
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op.data.buf.in = buf;
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op.data.nbytes = nbytes;
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ret = spi_mem_adjust_op_size(spinand->spimem, &op);
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if (ret)
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ret = spi_mem_dirmap_read(rdesc, column, nbytes, buf);
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if (ret < 0)
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return ret;
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ret = spi_mem_exec_op(spinand->spimem, &op);
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if (ret)
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return ret;
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if (!ret || ret > nbytes)
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return -EIO;
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buf += op.data.nbytes;
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nbytes -= op.data.nbytes;
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op.addr.val += op.data.nbytes;
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nbytes -= ret;
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column += ret;
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buf += ret;
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}
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if (req->datalen)
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@ -300,14 +270,12 @@ static int spinand_read_from_cache_op(struct spinand_device *spinand,
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static int spinand_write_to_cache_op(struct spinand_device *spinand,
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const struct nand_page_io_req *req)
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{
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struct spi_mem_op op = *spinand->op_templates.write_cache;
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struct nand_device *nand = spinand_to_nand(spinand);
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struct mtd_info *mtd = nanddev_to_mtd(nand);
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struct nand_page_io_req adjreq = *req;
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struct spi_mem_dirmap_desc *wdesc;
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unsigned int nbytes, column = 0;
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void *buf = spinand->databuf;
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unsigned int nbytes;
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u16 column = 0;
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int ret;
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ssize_t ret;
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/*
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* Looks like PROGRAM LOAD (AKA write cache) does not necessarily reset
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@ -318,12 +286,6 @@ static int spinand_write_to_cache_op(struct spinand_device *spinand,
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*/
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nbytes = nanddev_page_size(nand) + nanddev_per_page_oobsize(nand);
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memset(spinand->databuf, 0xff, nbytes);
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adjreq.dataoffs = 0;
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adjreq.datalen = nanddev_page_size(nand);
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adjreq.databuf.out = spinand->databuf;
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adjreq.ooblen = nanddev_per_page_oobsize(nand);
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adjreq.ooboffs = 0;
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adjreq.oobbuf.out = spinand->oobbuf;
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if (req->datalen)
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memcpy(spinand->databuf + req->dataoffs, req->databuf.out,
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@ -340,42 +302,19 @@ static int spinand_write_to_cache_op(struct spinand_device *spinand,
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req->ooblen);
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}
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spinand_cache_op_adjust_colum(spinand, &adjreq, &column);
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wdesc = spinand->dirmaps[req->pos.plane].wdesc;
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op = *spinand->op_templates.write_cache;
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op.addr.val = column;
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/*
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* Some controllers are limited in term of max TX data size. In this
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* case, split the operation into one LOAD CACHE and one or more
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* LOAD RANDOM CACHE.
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*/
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while (nbytes) {
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op.data.buf.out = buf;
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op.data.nbytes = nbytes;
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ret = spi_mem_adjust_op_size(spinand->spimem, &op);
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if (ret)
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ret = spi_mem_dirmap_write(wdesc, column, nbytes, buf);
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if (ret < 0)
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return ret;
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ret = spi_mem_exec_op(spinand->spimem, &op);
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if (ret)
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return ret;
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if (!ret || ret > nbytes)
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return -EIO;
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buf += op.data.nbytes;
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nbytes -= op.data.nbytes;
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op.addr.val += op.data.nbytes;
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/*
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* We need to use the RANDOM LOAD CACHE operation if there's
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* more than one iteration, because the LOAD operation might
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* reset the cache to 0xff.
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*/
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if (nbytes) {
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column = op.addr.val;
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op = *spinand->op_templates.update_cache;
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op.addr.val = column;
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}
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nbytes -= ret;
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column += ret;
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buf += ret;
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}
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return 0;
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@ -755,6 +694,59 @@ static int spinand_mtd_block_isreserved(struct mtd_info *mtd, loff_t offs)
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return ret;
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}
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static int spinand_create_dirmap(struct spinand_device *spinand,
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unsigned int plane)
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{
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struct nand_device *nand = spinand_to_nand(spinand);
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struct spi_mem_dirmap_info info = {
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.length = nanddev_page_size(nand) +
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nanddev_per_page_oobsize(nand),
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};
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struct spi_mem_dirmap_desc *desc;
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/* The plane number is passed in MSB just above the column address */
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info.offset = plane << fls(nand->memorg.pagesize);
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info.op_tmpl = *spinand->op_templates.update_cache;
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desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
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spinand->spimem, &info);
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if (IS_ERR(desc))
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return PTR_ERR(desc);
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spinand->dirmaps[plane].wdesc = desc;
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info.op_tmpl = *spinand->op_templates.read_cache;
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desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
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spinand->spimem, &info);
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if (IS_ERR(desc))
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return PTR_ERR(desc);
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spinand->dirmaps[plane].rdesc = desc;
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return 0;
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}
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static int spinand_create_dirmaps(struct spinand_device *spinand)
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{
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struct nand_device *nand = spinand_to_nand(spinand);
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int i, ret;
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spinand->dirmaps = devm_kzalloc(&spinand->spimem->spi->dev,
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sizeof(*spinand->dirmaps) *
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nand->memorg.planes_per_lun,
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GFP_KERNEL);
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if (!spinand->dirmaps)
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return -ENOMEM;
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for (i = 0; i < nand->memorg.planes_per_lun; i++) {
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ret = spinand_create_dirmap(spinand, i);
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if (ret)
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return ret;
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}
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return 0;
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}
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static const struct nand_ops spinand_ops = {
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.erase = spinand_erase,
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.markbad = spinand_markbad,
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@ -1012,6 +1004,14 @@ static int spinand_init(struct spinand_device *spinand)
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goto err_free_bufs;
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}
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ret = spinand_create_dirmaps(spinand);
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if (ret) {
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dev_err(dev,
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"Failed to create direct mappings for read/write operations (err = %d)\n",
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ret);
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goto err_manuf_cleanup;
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}
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/* After power up, all blocks are locked, so unlock them here. */
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for (i = 0; i < nand->memorg.ntargets; i++) {
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ret = spinand_select_target(spinand, i);
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@ -302,6 +302,11 @@ struct spinand_info {
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__VA_ARGS__ \
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}
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struct spinand_dirmap {
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struct spi_mem_dirmap_desc *wdesc;
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struct spi_mem_dirmap_desc *rdesc;
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};
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/**
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* struct spinand_device - SPI NAND device instance
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* @base: NAND device instance
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@ -341,6 +346,8 @@ struct spinand_device {
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const struct spi_mem_op *update_cache;
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} op_templates;
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struct spinand_dirmap *dirmaps;
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int (*select_target)(struct spinand_device *spinand,
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unsigned int target);
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unsigned int cur_target;
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