redonkable
/
alistair23-linux
1
0
Fork 0
Code Releases Activity

ARM: dts: calxeda: move memory-controller node out of ecx-common.dtsi 

The DDR controller is slightly different in ECX-2000 and ECX-1000, so we
need to have different nodes for each platform.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
[Device Tree documentation updated.]
Signed-off-by: Robert Richter <rric@kernel.org>
hifive-unleashed-5.1
Rob Herring 2013-07-23 14:04:44 -05:00 committed by Robert Richter
parent a72b8859fd
commit 982ac2a7b7
4 changed files with 15 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/arm/calxeda/mem-ctrlr.txt
View File

@ -1,7 +1,9 @@
Calxeda DDR memory controller
Properties:
- compatible : Should be "calxeda,hb-ddr-ctrl"
- compatible : Should be:
- "calxeda,hb-ddr-ctrl" for ECX-1000
- "calxeda,ecx-2000-ddr-ctrl" for ECX-2000
- reg : Address and size for DDR controller registers.
- interrupts : Interrupt for DDR controller.

6
arch/arm/boot/dts/ecx-2000.dts
View File

@ -85,6 +85,12 @@
<1 10 0xf08>;
};
memory-controller@fff00000 {
compatible = "calxeda,ecx-2000-ddr-ctrl";
reg = <0xfff00000 0x1000>;
interrupts = <0 91 4>;
};
intc: interrupt-controller@fff11000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;

6
arch/arm/boot/dts/ecx-common.dtsi
View File

@ -45,12 +45,6 @@
status = "disabled";
};
memory-controller@fff00000 {
compatible = "calxeda,hb-ddr-ctrl";
reg = <0xfff00000 0x1000>;
interrupts = <0 91 4>;
};
ipc@fff20000 {
compatible = "arm,pl320", "arm,primecell";
reg = <0xfff20000 0x1000>;

6
arch/arm/boot/dts/highbank.dts
View File

@ -86,6 +86,12 @@
soc {
ranges = <0x00000000 0x00000000 0xffffffff>;
memory-controller@fff00000 {
compatible = "calxeda,hb-ddr-ctrl";
reg = <0xfff00000 0x1000>;
interrupts = <0 91 4>;
};
timer@fff10600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xfff10600 0x20>;