ARM: shmobile: r8a73a4 IRQC support V2
Add IRQC interrupt controller support to r8a73a4 by hooking up two IRQC instances to handle 58 external IRQ signals. There IRQC controllers are tied to SPIs of the GIC. On r8a73a4 exact IRQ pin routing is handled by the PFC which is excluded from this patch. Both platform devices and DT devices are added in this patch. The platform device versions are used to provide a static interrupt map configuration for board code written in C. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>hifive-unleashed-5.1
Magnus Damm
Simon Horman
parent
e481a52890
commit
984ca29501
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@ -52,4 +52,36 @@
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<1 11 0xf08>,
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<1 10 0xf08>;
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};
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irqc0: interrupt-controller@e61c0000 {
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compatible = "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe61c0000 0x200>;
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interrupt-parent = <&gic>;
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interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>,
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<0 4 4>, <0 5 4>, <0 6 4>, <0 7 4>,
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<0 8 4>, <0 9 4>, <0 10 4>, <0 11 4>,
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<0 12 4>, <0 13 4>, <0 14 4>, <0 15 4>,
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<0 16 4>, <0 17 4>, <0 18 4>, <0 19 4>,
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<0 20 4>, <0 21 4>, <0 22 4>, <0 23 4>,
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<0 24 4>, <0 25 4>, <0 26 4>, <0 27 4>,
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<0 28 4>, <0 29 4>, <0 30 4>, <0 31 4>;
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};
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irqc1: interrupt-controller@e61c0200 {
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compatible = "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe61c0200 0x200>;
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interrupt-parent = <&gic>;
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interrupts = <0 32 4>, <0 33 4>, <0 34 4>, <0 35 4>,
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<0 36 4>, <0 37 4>, <0 38 4>, <0 39 4>,
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<0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>,
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<0 44 4>, <0 45 4>, <0 46 4>, <0 47 4>,
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<0 48 4>, <0 49 4>, <0 50 4>, <0 51 4>,
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<0 52 4>, <0 53 4>, <0 54 4>, <0 55 4>,
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<0 56 4>, <0 57 4>;
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};
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};
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@ -24,6 +24,7 @@ config ARCH_R8A73A4
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select CPU_V7
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select ARM_ARCH_TIMER
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select SH_CLK_CPG
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select RENESAS_IRQC
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config ARCH_R8A7740
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bool "R-Mobile A1 (R8A77400)"
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@ -21,6 +21,7 @@
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#include <linux/irqchip.h>
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#include <linux/kernel.h>
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#include <linux/of_platform.h>
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#include <linux/platform_data/irq-renesas-irqc.h>
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#include <linux/serial_sci.h>
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#include <mach/common.h>
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#include <mach/irqs.h>
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@ -63,6 +64,87 @@ static inline void r8a73a4_register_scif(int idx)
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sizeof(struct plat_sci_port));
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}
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static const struct renesas_irqc_config irqc0_data = {
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.irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
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};
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static const struct resource irqc0_resources[] = {
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DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
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DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
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DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
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DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
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DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
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DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */
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DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */
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DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */
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DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */
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DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */
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DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */
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DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */
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DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */
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DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */
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DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */
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DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */
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DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */
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DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */
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DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */
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DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */
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DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */
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DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */
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DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */
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DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */
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DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */
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DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */
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DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */
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DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */
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DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */
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DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */
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DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */
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DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */
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DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */
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};
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static const struct renesas_irqc_config irqc1_data = {
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.irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */
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};
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static const struct resource irqc1_resources[] = {
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DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */
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DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */
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DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */
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DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */
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DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */
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DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */
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DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */
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DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */
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DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */
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DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */
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DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */
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DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */
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DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */
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DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */
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DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */
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DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */
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DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */
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DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */
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DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */
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DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */
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DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */
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DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */
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DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */
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DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */
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DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */
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DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */
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DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */
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};
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#define r8a73a4_register_irqc(idx) \
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platform_device_register_resndata(&platform_bus, "renesas_irqc", \
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idx, irqc##idx##_resources, \
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ARRAY_SIZE(irqc##idx##_resources), \
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&irqc##idx##_data, \
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sizeof(struct renesas_irqc_config))
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void __init r8a73a4_add_standard_devices(void)
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{
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r8a73a4_register_scif(SCIFA0);
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@ -71,6 +153,8 @@ void __init r8a73a4_add_standard_devices(void)
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r8a73a4_register_scif(SCIFB1);
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r8a73a4_register_scif(SCIFB2);
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r8a73a4_register_scif(SCIFB3);
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r8a73a4_register_irqc(0);
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r8a73a4_register_irqc(1);
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}
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#ifdef CONFIG_USE_OF
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