phy: rockchip-inno-usb2: support otg-port for rk3399
The rk3399 SoC USB2 PHY is comprised of one Host port and one OTG port. And OTG port is for USB2.0 part of USB3.0 OTG controller, as a part to construct a fully feature Type-C subsystem. With this patch, we can support OTG port with the following functions: - Support BC1.2 charger detect, and use extcon notifier to send USB charger types to power driver. - Support PHY suspend for power management. - Support OTG Host only mode. Signed-off-by: William Wu <wulf@rock-chips.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>hifive-unleashed-5.1
William Wu
Kishon Vijay Abraham I
parent
5acefd4aed
commit
98898f3bc8
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@ -17,6 +17,7 @@
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/extcon.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/gpio/consumer.h>
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@ -30,11 +31,15 @@
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#include <linux/of_platform.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/power_supply.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <linux/usb/of.h>
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#include <linux/usb/otg.h>
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#define BIT_WRITEABLE_SHIFT 16
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#define SCHEDULE_DELAY (60 * HZ)
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#define SCHEDULE_DELAY (60 * HZ)
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#define OTG_SCHEDULE_DELAY (2 * HZ)
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enum rockchip_usb2phy_port_id {
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USB2PHY_PORT_OTG,
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@ -49,6 +54,37 @@ enum rockchip_usb2phy_host_state {
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PHY_STATE_FS_LS_ONLINE = 4,
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};
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/**
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* Different states involved in USB charger detection.
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* USB_CHG_STATE_UNDEFINED USB charger is not connected or detection
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* process is not yet started.
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* USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact.
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* USB_CHG_STATE_DCD_DONE Data pin contact is detected.
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* USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects
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* between SDP and DCP/CDP).
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* USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
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* between DCP and CDP).
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* USB_CHG_STATE_DETECTED USB charger type is determined.
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*/
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enum usb_chg_state {
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USB_CHG_STATE_UNDEFINED = 0,
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USB_CHG_STATE_WAIT_FOR_DCD,
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USB_CHG_STATE_DCD_DONE,
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USB_CHG_STATE_PRIMARY_DONE,
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USB_CHG_STATE_SECONDARY_DONE,
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USB_CHG_STATE_DETECTED,
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};
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static const unsigned int rockchip_usb2phy_extcon_cable[] = {
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EXTCON_USB,
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EXTCON_USB_HOST,
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EXTCON_CHG_USB_SDP,
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EXTCON_CHG_USB_CDP,
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EXTCON_CHG_USB_DCP,
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EXTCON_CHG_USB_SLOW,
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EXTCON_NONE,
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};
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struct usb2phy_reg {
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unsigned int offset;
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unsigned int bitend;
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@ -57,20 +93,56 @@ struct usb2phy_reg {
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unsigned int enable;
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};
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/**
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* struct rockchip_chg_det_reg: usb charger detect registers
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* @cp_det: charging port detected successfully.
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* @dcp_det: dedicated charging port detected successfully.
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* @dp_det: assert data pin connect successfully.
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* @idm_sink_en: open dm sink curren.
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* @idp_sink_en: open dp sink current.
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* @idp_src_en: open dm source current.
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* @rdm_pdwn_en: open dm pull down resistor.
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* @vdm_src_en: open dm voltage source.
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* @vdp_src_en: open dp voltage source.
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* @opmode: utmi operational mode.
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*/
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struct rockchip_chg_det_reg {
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struct usb2phy_reg cp_det;
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struct usb2phy_reg dcp_det;
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struct usb2phy_reg dp_det;
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struct usb2phy_reg idm_sink_en;
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struct usb2phy_reg idp_sink_en;
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struct usb2phy_reg idp_src_en;
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struct usb2phy_reg rdm_pdwn_en;
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struct usb2phy_reg vdm_src_en;
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struct usb2phy_reg vdp_src_en;
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struct usb2phy_reg opmode;
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};
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/**
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* struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
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* @phy_sus: phy suspend register.
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* @bvalid_det_en: vbus valid rise detection enable register.
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* @bvalid_det_st: vbus valid rise detection status register.
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* @bvalid_det_clr: vbus valid rise detection clear register.
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* @ls_det_en: linestate detection enable register.
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* @ls_det_st: linestate detection state register.
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* @ls_det_clr: linestate detection clear register.
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* @utmi_avalid: utmi vbus avalid status register.
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* @utmi_bvalid: utmi vbus bvalid status register.
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* @utmi_ls: utmi linestate state register.
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* @utmi_hstdet: utmi host disconnect register.
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*/
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struct rockchip_usb2phy_port_cfg {
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struct usb2phy_reg phy_sus;
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struct usb2phy_reg bvalid_det_en;
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struct usb2phy_reg bvalid_det_st;
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struct usb2phy_reg bvalid_det_clr;
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struct usb2phy_reg ls_det_en;
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struct usb2phy_reg ls_det_st;
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struct usb2phy_reg ls_det_clr;
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struct usb2phy_reg utmi_avalid;
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struct usb2phy_reg utmi_bvalid;
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struct usb2phy_reg utmi_ls;
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struct usb2phy_reg utmi_hstdet;
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};
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@ -80,31 +152,51 @@ struct rockchip_usb2phy_port_cfg {
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* @reg: the address offset of grf for usb-phy config.
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* @num_ports: specify how many ports that the phy has.
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* @clkout_ctl: keep on/turn off output clk of phy.
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* @chg_det: charger detection registers.
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*/
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struct rockchip_usb2phy_cfg {
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unsigned int reg;
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unsigned int num_ports;
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struct usb2phy_reg clkout_ctl;
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const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
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const struct rockchip_chg_det_reg chg_det;
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};
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/**
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* struct rockchip_usb2phy_port: usb-phy port data.
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* @port_id: flag for otg port or host port.
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* @suspended: phy suspended flag.
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* @utmi_avalid: utmi avalid status usage flag.
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* true - use avalid to get vbus status
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* flase - use bvalid to get vbus status
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* @vbus_attached: otg device vbus status.
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* @bvalid_irq: IRQ number assigned for vbus valid rise detection.
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* @ls_irq: IRQ number assigned for linestate detection.
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* @mutex: for register updating in sm_work.
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* @sm_work: OTG state machine work.
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* @chg_work: charge detect work.
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* @otg_sm_work: OTG state machine work.
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* @sm_work: HOST state machine work.
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* @phy_cfg: port register configuration, assigned by driver data.
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* @event_nb: hold event notification callback.
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* @state: define OTG enumeration states before device reset.
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* @mode: the dr_mode of the controller.
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*/
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struct rockchip_usb2phy_port {
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struct phy *phy;
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unsigned int port_id;
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bool suspended;
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bool utmi_avalid;
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bool vbus_attached;
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int bvalid_irq;
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int ls_irq;
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struct mutex mutex;
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struct delayed_work chg_work;
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struct delayed_work otg_sm_work;
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struct delayed_work sm_work;
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const struct rockchip_usb2phy_port_cfg *port_cfg;
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struct notifier_block event_nb;
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enum usb_otg_state state;
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enum usb_dr_mode mode;
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};
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/**
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@ -113,6 +205,11 @@ struct rockchip_usb2phy_port {
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* @clk: clock struct of phy input clk.
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* @clk480m: clock struct of phy output clk.
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* @clk_hw: clock struct of phy output clk management.
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* @chg_state: states involved in USB charger detection.
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* @chg_type: USB charger types.
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* @dcd_retries: The retry count used to track Data contact
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* detection process.
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* @edev: extcon device for notification registration
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* @phy_cfg: phy register configuration, assigned by driver data.
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* @ports: phy port instance.
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*/
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@ -122,6 +219,10 @@ struct rockchip_usb2phy {
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struct clk *clk;
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struct clk *clk480m;
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struct clk_hw clk480m_hw;
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enum usb_chg_state chg_state;
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enum power_supply_type chg_type;
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u8 dcd_retries;
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struct extcon_dev *edev;
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const struct rockchip_usb2phy_cfg *phy_cfg;
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struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
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};
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@ -263,33 +364,84 @@ err_ret:
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return ret;
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}
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static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
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{
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int ret;
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struct device_node *node = rphy->dev->of_node;
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struct extcon_dev *edev;
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if (of_property_read_bool(node, "extcon")) {
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edev = extcon_get_edev_by_phandle(rphy->dev, 0);
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if (IS_ERR(edev)) {
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if (PTR_ERR(edev) != -EPROBE_DEFER)
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dev_err(rphy->dev, "Invalid or missing extcon\n");
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return PTR_ERR(edev);
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}
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} else {
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/* Initialize extcon device */
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edev = devm_extcon_dev_allocate(rphy->dev,
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rockchip_usb2phy_extcon_cable);
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if (IS_ERR(edev))
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return -ENOMEM;
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ret = devm_extcon_dev_register(rphy->dev, edev);
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if (ret) {
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dev_err(rphy->dev, "failed to register extcon device\n");
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return ret;
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}
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}
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rphy->edev = edev;
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return 0;
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}
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static int rockchip_usb2phy_init(struct phy *phy)
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{
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struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
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struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
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int ret;
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int ret = 0;
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if (rport->port_id == USB2PHY_PORT_HOST) {
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/* clear linestate and enable linestate detect irq */
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mutex_lock(&rport->mutex);
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mutex_lock(&rport->mutex);
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ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
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if (ret) {
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mutex_unlock(&rport->mutex);
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return ret;
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if (rport->port_id == USB2PHY_PORT_OTG) {
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if (rport->mode != USB_DR_MODE_HOST) {
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/* clear bvalid status and enable bvalid detect irq */
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ret = property_enable(rphy,
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&rport->port_cfg->bvalid_det_clr,
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true);
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if (ret)
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goto out;
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ret = property_enable(rphy,
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&rport->port_cfg->bvalid_det_en,
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true);
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if (ret)
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goto out;
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schedule_delayed_work(&rport->otg_sm_work,
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OTG_SCHEDULE_DELAY);
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} else {
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/* If OTG works in host only mode, do nothing. */
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dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
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}
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} else if (rport->port_id == USB2PHY_PORT_HOST) {
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/* clear linestate and enable linestate detect irq */
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ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
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if (ret)
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goto out;
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ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true);
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if (ret) {
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mutex_unlock(&rport->mutex);
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return ret;
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}
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if (ret)
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goto out;
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mutex_unlock(&rport->mutex);
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schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
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}
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return 0;
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out:
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mutex_unlock(&rport->mutex);
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return ret;
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}
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static int rockchip_usb2phy_power_on(struct phy *phy)
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@ -340,7 +492,11 @@ static int rockchip_usb2phy_exit(struct phy *phy)
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{
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struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
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if (rport->port_id == USB2PHY_PORT_HOST)
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if (rport->port_id == USB2PHY_PORT_OTG &&
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rport->mode != USB_DR_MODE_HOST) {
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cancel_delayed_work_sync(&rport->otg_sm_work);
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cancel_delayed_work_sync(&rport->chg_work);
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} else if (rport->port_id == USB2PHY_PORT_HOST)
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cancel_delayed_work_sync(&rport->sm_work);
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return 0;
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@ -354,6 +510,249 @@ static const struct phy_ops rockchip_usb2phy_ops = {
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.owner = THIS_MODULE,
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};
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static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
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{
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struct rockchip_usb2phy_port *rport =
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container_of(work, struct rockchip_usb2phy_port,
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otg_sm_work.work);
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struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
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static unsigned int cable;
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unsigned long delay;
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bool vbus_attach, sch_work, notify_charger;
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if (rport->utmi_avalid)
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vbus_attach =
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property_enabled(rphy, &rport->port_cfg->utmi_avalid);
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else
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vbus_attach =
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property_enabled(rphy, &rport->port_cfg->utmi_bvalid);
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sch_work = false;
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notify_charger = false;
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delay = OTG_SCHEDULE_DELAY;
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dev_dbg(&rport->phy->dev, "%s otg sm work\n",
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usb_otg_state_string(rport->state));
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switch (rport->state) {
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case OTG_STATE_UNDEFINED:
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rport->state = OTG_STATE_B_IDLE;
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if (!vbus_attach)
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rockchip_usb2phy_power_off(rport->phy);
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/* fall through */
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case OTG_STATE_B_IDLE:
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if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) > 0) {
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dev_dbg(&rport->phy->dev, "usb otg host connect\n");
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rport->state = OTG_STATE_A_HOST;
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rockchip_usb2phy_power_on(rport->phy);
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return;
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} else if (vbus_attach) {
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dev_dbg(&rport->phy->dev, "vbus_attach\n");
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switch (rphy->chg_state) {
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case USB_CHG_STATE_UNDEFINED:
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schedule_delayed_work(&rport->chg_work, 0);
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return;
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case USB_CHG_STATE_DETECTED:
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switch (rphy->chg_type) {
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case POWER_SUPPLY_TYPE_USB:
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dev_dbg(&rport->phy->dev,
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"sdp cable is connecetd\n");
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rockchip_usb2phy_power_on(rport->phy);
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rport->state = OTG_STATE_B_PERIPHERAL;
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notify_charger = true;
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sch_work = true;
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cable = EXTCON_CHG_USB_SDP;
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break;
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case POWER_SUPPLY_TYPE_USB_DCP:
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dev_dbg(&rport->phy->dev,
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"dcp cable is connecetd\n");
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rockchip_usb2phy_power_off(rport->phy);
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notify_charger = true;
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sch_work = true;
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cable = EXTCON_CHG_USB_DCP;
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break;
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case POWER_SUPPLY_TYPE_USB_CDP:
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dev_dbg(&rport->phy->dev,
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"cdp cable is connecetd\n");
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rockchip_usb2phy_power_on(rport->phy);
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rport->state = OTG_STATE_B_PERIPHERAL;
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notify_charger = true;
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sch_work = true;
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cable = EXTCON_CHG_USB_CDP;
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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} else {
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notify_charger = true;
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rphy->chg_state = USB_CHG_STATE_UNDEFINED;
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rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
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}
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if (rport->vbus_attached != vbus_attach) {
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rport->vbus_attached = vbus_attach;
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if (notify_charger && rphy->edev)
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extcon_set_cable_state_(rphy->edev,
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cable, vbus_attach);
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}
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break;
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case OTG_STATE_B_PERIPHERAL:
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if (!vbus_attach) {
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dev_dbg(&rport->phy->dev, "usb disconnect\n");
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rphy->chg_state = USB_CHG_STATE_UNDEFINED;
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rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
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rport->state = OTG_STATE_B_IDLE;
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delay = 0;
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rockchip_usb2phy_power_off(rport->phy);
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}
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sch_work = true;
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break;
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case OTG_STATE_A_HOST:
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if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) == 0) {
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dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
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rport->state = OTG_STATE_B_IDLE;
|
||||
rockchip_usb2phy_power_off(rport->phy);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (sch_work)
|
||||
schedule_delayed_work(&rport->otg_sm_work, delay);
|
||||
}
|
||||
|
||||
static const char *chg_to_string(enum power_supply_type chg_type)
|
||||
{
|
||||
switch (chg_type) {
|
||||
case POWER_SUPPLY_TYPE_USB:
|
||||
return "USB_SDP_CHARGER";
|
||||
case POWER_SUPPLY_TYPE_USB_DCP:
|
||||
return "USB_DCP_CHARGER";
|
||||
case POWER_SUPPLY_TYPE_USB_CDP:
|
||||
return "USB_CDP_CHARGER";
|
||||
default:
|
||||
return "INVALID_CHARGER";
|
||||
}
|
||||
}
|
||||
|
||||
static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
|
||||
bool en)
|
||||
{
|
||||
property_enable(rphy, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
|
||||
property_enable(rphy, &rphy->phy_cfg->chg_det.idp_src_en, en);
|
||||
}
|
||||
|
||||
static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
|
||||
bool en)
|
||||
{
|
||||
property_enable(rphy, &rphy->phy_cfg->chg_det.vdp_src_en, en);
|
||||
property_enable(rphy, &rphy->phy_cfg->chg_det.idm_sink_en, en);
|
||||
}
|
||||
|
||||
static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
|
||||
bool en)
|
||||
{
|
||||
property_enable(rphy, &rphy->phy_cfg->chg_det.vdm_src_en, en);
|
||||
property_enable(rphy, &rphy->phy_cfg->chg_det.idp_sink_en, en);
|
||||
}
|
||||
|
||||
#define CHG_DCD_POLL_TIME (100 * HZ / 1000)
|
||||
#define CHG_DCD_MAX_RETRIES 6
|
||||
#define CHG_PRIMARY_DET_TIME (40 * HZ / 1000)
|
||||
#define CHG_SECONDARY_DET_TIME (40 * HZ / 1000)
|
||||
static void rockchip_chg_detect_work(struct work_struct *work)
|
||||
{
|
||||
struct rockchip_usb2phy_port *rport =
|
||||
container_of(work, struct rockchip_usb2phy_port, chg_work.work);
|
||||
struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
|
||||
bool is_dcd, tmout, vout;
|
||||
unsigned long delay;
|
||||
|
||||
dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
|
||||
rphy->chg_state);
|
||||
switch (rphy->chg_state) {
|
||||
case USB_CHG_STATE_UNDEFINED:
|
||||
if (!rport->suspended)
|
||||
rockchip_usb2phy_power_off(rport->phy);
|
||||
/* put the controller in non-driving mode */
|
||||
property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, false);
|
||||
/* Start DCD processing stage 1 */
|
||||
rockchip_chg_enable_dcd(rphy, true);
|
||||
rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
|
||||
rphy->dcd_retries = 0;
|
||||
delay = CHG_DCD_POLL_TIME;
|
||||
break;
|
||||
case USB_CHG_STATE_WAIT_FOR_DCD:
|
||||
/* get data contact detection status */
|
||||
is_dcd = property_enabled(rphy, &rphy->phy_cfg->chg_det.dp_det);
|
||||
tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
|
||||
/* stage 2 */
|
||||
if (is_dcd || tmout) {
|
||||
/* stage 4 */
|
||||
/* Turn off DCD circuitry */
|
||||
rockchip_chg_enable_dcd(rphy, false);
|
||||
/* Voltage Source on DP, Probe on DM */
|
||||
rockchip_chg_enable_primary_det(rphy, true);
|
||||
delay = CHG_PRIMARY_DET_TIME;
|
||||
rphy->chg_state = USB_CHG_STATE_DCD_DONE;
|
||||
} else {
|
||||
/* stage 3 */
|
||||
delay = CHG_DCD_POLL_TIME;
|
||||
}
|
||||
break;
|
||||
case USB_CHG_STATE_DCD_DONE:
|
||||
vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.cp_det);
|
||||
rockchip_chg_enable_primary_det(rphy, false);
|
||||
if (vout) {
|
||||
/* Voltage Source on DM, Probe on DP */
|
||||
rockchip_chg_enable_secondary_det(rphy, true);
|
||||
delay = CHG_SECONDARY_DET_TIME;
|
||||
rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
|
||||
} else {
|
||||
if (tmout) {
|
||||
/* floating charger found */
|
||||
rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
|
||||
rphy->chg_state = USB_CHG_STATE_DETECTED;
|
||||
delay = 0;
|
||||
} else {
|
||||
rphy->chg_type = POWER_SUPPLY_TYPE_USB;
|
||||
rphy->chg_state = USB_CHG_STATE_DETECTED;
|
||||
delay = 0;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case USB_CHG_STATE_PRIMARY_DONE:
|
||||
vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.dcp_det);
|
||||
/* Turn off voltage source */
|
||||
rockchip_chg_enable_secondary_det(rphy, false);
|
||||
if (vout)
|
||||
rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
|
||||
else
|
||||
rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
|
||||
/* fall through */
|
||||
case USB_CHG_STATE_SECONDARY_DONE:
|
||||
rphy->chg_state = USB_CHG_STATE_DETECTED;
|
||||
delay = 0;
|
||||
/* fall through */
|
||||
case USB_CHG_STATE_DETECTED:
|
||||
/* put the controller in normal mode */
|
||||
property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, true);
|
||||
rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
|
||||
dev_info(&rport->phy->dev, "charger = %s\n",
|
||||
chg_to_string(rphy->chg_type));
|
||||
return;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
schedule_delayed_work(&rport->chg_work, delay);
|
||||
}
|
||||
|
||||
/*
|
||||
* The function manage host-phy port state and suspend/resume phy port
|
||||
* to save power.
|
||||
|
|
@ -485,6 +884,26 @@ static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
|
|||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
|
||||
{
|
||||
struct rockchip_usb2phy_port *rport = data;
|
||||
struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
|
||||
|
||||
if (!property_enabled(rphy, &rport->port_cfg->bvalid_det_st))
|
||||
return IRQ_NONE;
|
||||
|
||||
mutex_lock(&rport->mutex);
|
||||
|
||||
/* clear bvalid detect irq pending status */
|
||||
property_enable(rphy, &rport->port_cfg->bvalid_det_clr, true);
|
||||
|
||||
mutex_unlock(&rport->mutex);
|
||||
|
||||
rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
|
||||
struct rockchip_usb2phy_port *rport,
|
||||
struct device_node *child_np)
|
||||
|
|
@ -509,13 +928,86 @@ static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
|
|||
IRQF_ONESHOT,
|
||||
"rockchip_usb2phy", rport);
|
||||
if (ret) {
|
||||
dev_err(rphy->dev, "failed to request irq handle\n");
|
||||
dev_err(rphy->dev, "failed to request linestate irq handle\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_otg_event(struct notifier_block *nb,
|
||||
unsigned long event, void *ptr)
|
||||
{
|
||||
struct rockchip_usb2phy_port *rport =
|
||||
container_of(nb, struct rockchip_usb2phy_port, event_nb);
|
||||
|
||||
schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
|
||||
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
|
||||
struct rockchip_usb2phy_port *rport,
|
||||
struct device_node *child_np)
|
||||
{
|
||||
int ret;
|
||||
|
||||
rport->port_id = USB2PHY_PORT_OTG;
|
||||
rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
|
||||
rport->state = OTG_STATE_UNDEFINED;
|
||||
|
||||
/*
|
||||
* set suspended flag to true, but actually don't
|
||||
* put phy in suspend mode, it aims to enable usb
|
||||
* phy and clock in power_on() called by usb controller
|
||||
* driver during probe.
|
||||
*/
|
||||
rport->suspended = true;
|
||||
rport->vbus_attached = false;
|
||||
|
||||
mutex_init(&rport->mutex);
|
||||
|
||||
rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
|
||||
if (rport->mode == USB_DR_MODE_HOST) {
|
||||
ret = 0;
|
||||
goto out;
|
||||
}
|
||||
|
||||
INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
|
||||
INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
|
||||
|
||||
rport->utmi_avalid =
|
||||
of_property_read_bool(child_np, "rockchip,utmi-avalid");
|
||||
|
||||
rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
|
||||
if (rport->bvalid_irq < 0) {
|
||||
dev_err(rphy->dev, "no vbus valid irq provided\n");
|
||||
ret = rport->bvalid_irq;
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, NULL,
|
||||
rockchip_usb2phy_bvalid_irq,
|
||||
IRQF_ONESHOT,
|
||||
"rockchip_usb2phy_bvalid", rport);
|
||||
if (ret) {
|
||||
dev_err(rphy->dev, "failed to request otg-bvalid irq handle\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (!IS_ERR(rphy->edev)) {
|
||||
rport->event_nb.notifier_call = rockchip_otg_event;
|
||||
|
||||
ret = extcon_register_notifier(rphy->edev, EXTCON_USB_HOST,
|
||||
&rport->event_nb);
|
||||
if (ret)
|
||||
dev_err(rphy->dev, "register USB HOST notifier failed\n");
|
||||
}
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rockchip_usb2phy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
|
|
@ -553,8 +1045,14 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev)
|
|||
|
||||
rphy->dev = dev;
|
||||
phy_cfgs = match->data;
|
||||
rphy->chg_state = USB_CHG_STATE_UNDEFINED;
|
||||
rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
|
||||
platform_set_drvdata(pdev, rphy);
|
||||
|
||||
ret = rockchip_usb2phy_extcon_register(rphy);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* find out a proper config which can be matched with dt. */
|
||||
index = 0;
|
||||
while (phy_cfgs[index].reg) {
|
||||
|
|
@ -591,13 +1089,9 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev)
|
|||
struct rockchip_usb2phy_port *rport = &rphy->ports[index];
|
||||
struct phy *phy;
|
||||
|
||||
/*
|
||||
* This driver aim to support both otg-port and host-port,
|
||||
* but unfortunately, the otg part is not ready in current,
|
||||
* so this comments and below codes are interim, which should
|
||||
* be changed after otg-port is supplied soon.
|
||||
*/
|
||||
if (of_node_cmp(child_np->name, "host-port"))
|
||||
/* This driver aims to support both otg-port and host-port */
|
||||
if (of_node_cmp(child_np->name, "host-port") &&
|
||||
of_node_cmp(child_np->name, "otg-port"))
|
||||
goto next_child;
|
||||
|
||||
phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
|
||||
|
|
@ -610,9 +1104,18 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev)
|
|||
rport->phy = phy;
|
||||
phy_set_drvdata(rport->phy, rport);
|
||||
|
||||
ret = rockchip_usb2phy_host_port_init(rphy, rport, child_np);
|
||||
if (ret)
|
||||
goto put_child;
|
||||
/* initialize otg/host port separately */
|
||||
if (!of_node_cmp(child_np->name, "host-port")) {
|
||||
ret = rockchip_usb2phy_host_port_init(rphy, rport,
|
||||
child_np);
|
||||
if (ret)
|
||||
goto put_child;
|
||||
} else {
|
||||
ret = rockchip_usb2phy_otg_port_init(rphy, rport,
|
||||
child_np);
|
||||
if (ret)
|
||||
goto put_child;
|
||||
}
|
||||
|
||||
next_child:
|
||||
/* to prevent out of boundary */
|
||||
|
|
@ -654,10 +1157,18 @@ static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
|
|||
|
||||
static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
|
||||
{
|
||||
.reg = 0xe450,
|
||||
.reg = 0xe450,
|
||||
.num_ports = 2,
|
||||
.clkout_ctl = { 0xe450, 4, 4, 1, 0 },
|
||||
.port_cfgs = {
|
||||
[USB2PHY_PORT_OTG] = {
|
||||
.phy_sus = { 0xe454, 1, 0, 2, 1 },
|
||||
.bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 },
|
||||
.bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 },
|
||||
.bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
|
||||
.utmi_avalid = { 0xe2ac, 7, 7, 0, 1 },
|
||||
.utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 },
|
||||
},
|
||||
[USB2PHY_PORT_HOST] = {
|
||||
.phy_sus = { 0xe458, 1, 0, 0x2, 0x1 },
|
||||
.ls_det_en = { 0xe3c0, 6, 6, 0, 1 },
|
||||
|
|
@ -667,12 +1178,32 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
|
|||
.utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 }
|
||||
}
|
||||
},
|
||||
.chg_det = {
|
||||
.opmode = { 0xe454, 3, 0, 5, 1 },
|
||||
.cp_det = { 0xe2ac, 2, 2, 0, 1 },
|
||||
.dcp_det = { 0xe2ac, 1, 1, 0, 1 },
|
||||
.dp_det = { 0xe2ac, 0, 0, 0, 1 },
|
||||
.idm_sink_en = { 0xe450, 8, 8, 0, 1 },
|
||||
.idp_sink_en = { 0xe450, 7, 7, 0, 1 },
|
||||
.idp_src_en = { 0xe450, 9, 9, 0, 1 },
|
||||
.rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 },
|
||||
.vdm_src_en = { 0xe450, 12, 12, 0, 1 },
|
||||
.vdp_src_en = { 0xe450, 11, 11, 0, 1 },
|
||||
},
|
||||
},
|
||||
{
|
||||
.reg = 0xe460,
|
||||
.reg = 0xe460,
|
||||
.num_ports = 2,
|
||||
.clkout_ctl = { 0xe460, 4, 4, 1, 0 },
|
||||
.port_cfgs = {
|
||||
[USB2PHY_PORT_OTG] = {
|
||||
.phy_sus = { 0xe464, 1, 0, 2, 1 },
|
||||
.bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 },
|
||||
.bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 },
|
||||
.bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
|
||||
.utmi_avalid = { 0xe2ac, 10, 10, 0, 1 },
|
||||
.utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 },
|
||||
},
|
||||
[USB2PHY_PORT_HOST] = {
|
||||
.phy_sus = { 0xe468, 1, 0, 0x2, 0x1 },
|
||||
.ls_det_en = { 0xe3c0, 11, 11, 0, 1 },
|
||||
|
|
|
|||
Loading…
Reference in New Issue