clk: samsung: exynos5433: Add clocks for CMU_MFC domain
This patch adds the mux/divider/gate clocks for CMU_MFC domain which generates the clocks for MFC(Multi-Format Codec) IP. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>hifive-unleashed-5.1
Chanwoo Choi
Sylwester Nawrocki
parent
b274bbfd8b
commit
9910b6bbaa
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@ -39,6 +39,8 @@ Required Properties:
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L2 cache controller.
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- "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL
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which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs.
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- "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC
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which generates clocks for MFC(Multi-Format Codec) IP.
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- reg: physical base address of the controller and length of memory mapped
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region.
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@ -125,6 +127,10 @@ Required Properties:
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- sclk_jpeg_mscl
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- aclk_mscl_400
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Input clocks for mfc clock controller:
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- oscclk
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- aclk_mfc_400
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume.
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@ -340,6 +346,15 @@ Example 2: Examples of clock controller nodes are listed below.
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<&cmu_top CLK_ACLK_MSCL_400>;
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};
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cmu_mfc: clock-controller@15280000 {
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compatible = "samsung,exynos5433-cmu-mfc";
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reg = <0x15280000 0x0b08>;
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#clock-cells = <1>;
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clock-names = "oscclk", "aclk_mfc_400";
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clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
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};
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Example 3: UART controller node that consumes the clock generated by the clock
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controller.
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@ -560,6 +560,9 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
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GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
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ENABLE_ACLK_TOP, 14,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
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ENABLE_ACLK_TOP, 3,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
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ENABLE_ACLK_TOP, 2,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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@ -3990,3 +3993,113 @@ static void __init exynos5433_cmu_mscl_init(struct device_node *np)
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}
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CLK_OF_DECLARE(exynos5433_cmu_mscl, "samsung,exynos5433-cmu-mscl",
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exynos5433_cmu_mscl_init);
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/*
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* Register offset definitions for CMU_MFC
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*/
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#define MUX_SEL_MFC 0x0200
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#define MUX_ENABLE_MFC 0x0300
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#define MUX_STAT_MFC 0x0400
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#define DIV_MFC 0x0600
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#define DIV_STAT_MFC 0x0700
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#define ENABLE_ACLK_MFC 0x0800
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#define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804
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#define ENABLE_PCLK_MFC 0x0900
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#define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904
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#define ENABLE_IP_MFC0 0x0b00
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#define ENABLE_IP_MFC1 0x0b04
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#define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08
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static unsigned long mfc_clk_regs[] __initdata = {
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MUX_SEL_MFC,
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MUX_ENABLE_MFC,
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MUX_STAT_MFC,
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DIV_MFC,
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DIV_STAT_MFC,
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ENABLE_ACLK_MFC,
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ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
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ENABLE_PCLK_MFC,
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ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
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ENABLE_IP_MFC0,
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ENABLE_IP_MFC1,
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ENABLE_IP_MFC_SECURE_SMMU_MFC,
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};
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PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", };
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static struct samsung_mux_clock mfc_mux_clks[] __initdata = {
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/* MUX_SEL_MFC */
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MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user",
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mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
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};
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static struct samsung_div_clock mfc_div_clks[] __initdata = {
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/* DIV_MFC */
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DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user",
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DIV_MFC, 0, 2),
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};
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static struct samsung_gate_clock mfc_gate_clks[] __initdata = {
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/* ENABLE_ACLK_MFC */
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GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
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ENABLE_ACLK_MFC, 6, 0, 0),
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GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user",
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ENABLE_ACLK_MFC, 5, 0, 0),
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GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc",
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ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user",
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ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc",
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ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user",
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ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user",
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ENABLE_ACLK_MFC, 0, 0, 0),
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/* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */
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GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user",
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ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
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1, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user",
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ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
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0, CLK_IGNORE_UNUSED, 0),
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/* ENABLE_PCLK_MFC */
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GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc",
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ENABLE_PCLK_MFC, 4, 0, 0),
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GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc",
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ENABLE_PCLK_MFC, 3, 0, 0),
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GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc",
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ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc",
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ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc",
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ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
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/* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */
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GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc",
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ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
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1, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc",
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ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
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0, CLK_IGNORE_UNUSED, 0),
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};
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static struct samsung_cmu_info mfc_cmu_info __initdata = {
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.mux_clks = mfc_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
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.div_clks = mfc_div_clks,
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.nr_div_clks = ARRAY_SIZE(mfc_div_clks),
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.gate_clks = mfc_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
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.nr_clk_ids = MFC_NR_CLK,
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.clk_regs = mfc_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
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};
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static void __init exynos5433_cmu_mfc_init(struct device_node *np)
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{
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samsung_cmu_register_one(np, &mfc_cmu_info);
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}
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CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc",
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exynos5433_cmu_mfc_init);
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@ -153,8 +153,9 @@
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#define CLK_ACLK_GSCL_333 233
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#define CLK_SCLK_JPEG_MSCL 234
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#define CLK_ACLK_MSCL_400 235
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#define CLK_ACLK_MFC_400 236
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#define TOP_NR_CLK 236
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#define TOP_NR_CLK 237
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/* CMU_CPIF */
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#define CLK_FOUT_MPHY_PLL 1
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@ -976,4 +977,28 @@
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#define MSCL_NR_CLK 30
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/* CMU_MFC */
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#define CLK_MOUT_ACLK_MFC_400_USER 1
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#define CLK_DIV_PCLK_MFC 2
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#define CLK_ACLK_BTS_MFC_1 3
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#define CLK_ACLK_BTS_MFC_0 4
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#define CLK_ACLK_AHB2APB_MFCP 5
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#define CLK_ACLK_XIU_MFCX 6
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#define CLK_ACLK_MFCNP_100 7
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#define CLK_ACLK_MFCND_400 8
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#define CLK_ACLK_MFC 9
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#define CLK_ACLK_SMMU_MFC_1 10
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#define CLK_ACLK_SMMU_MFC_0 11
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#define CLK_PCLK_BTS_MFC_1 12
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#define CLK_PCLK_BTS_MFC_0 13
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#define CLK_PCLK_PMU_MFC 14
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#define CLK_PCLK_SYSREG_MFC 15
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#define CLK_PCLK_MFC 16
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#define CLK_PCLK_SMMU_MFC_1 17
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#define CLK_PCLK_SMMU_MFC_0 18
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#define MFC_NR_CLK 19
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
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