drm/i915: only check for irqs_disabled when disabling LCPLL
Because if we keep the current code, we'll get tons of WARNs on Broadwell, since the code is Haswell-specific. We could have also added a Broadwell-specific code there, but it's not really needed since we never disable LCPLL with the hotplug interrupts still enabled. So keep the easy-and-simple-to-maintain solution until we actually need something else. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -6853,8 +6853,6 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
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struct drm_device *dev = dev_priv->dev;
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struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
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struct intel_crtc *crtc;
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unsigned long irqflags;
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uint32_t val;
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
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WARN(crtc->active, "CRTC for pipe %c enabled\n",
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@ -6875,14 +6873,13 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
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"Utility pin enabled\n");
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WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
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spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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val = I915_READ(DEIMR);
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WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff,
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"Unexpected DEIMR bits enabled: 0x%x\n", val);
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val = I915_READ(SDEIMR);
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WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
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"Unexpected SDEIMR bits enabled: 0x%x\n", val);
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spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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/*
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* In theory we can still leave IRQs enabled, as long as only the HPD
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* interrupts remain enabled. We used to check for that, but since it's
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* gen-specific and since we only disable LCPLL after we fully disable
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* the interrupts, the check below should be enough.
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*/
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WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
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}
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static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
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