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[PATCH] EDAC: e752x byte access fix 

The reading of the DRA registers should be a byte at a time (one register at a
time) instead of 4 bytes at a time (four registers).  Reading a dword at a
time retrieves erroneous information from all but the first register.  A
change was made to read in each register in a loop prior to using the data in
those registers.

Signed-off-by: Brian Pomerantz <bapper@mvista.com>
Signed-off-by: Dave Jiang <djiang@mvista.com>
Signed-off-by: Doug Thompson <norsk5@xmission.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: Andi Kleen <ak@suse.de>
Cc: "Eric W. Biederman" <ebiederm@xmission.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
hifive-unleashed-5.1
Brian Pomerantz 2007-02-12 00:53:05 -08:00 committed by Linus Torvalds
parent dfb2a76378
commit 9962fd017b
1 changed files with 6 additions and 1 deletions
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7
drivers/edac/e752x_edac.c
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@ -782,7 +782,12 @@ static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
u8 value;
u32 dra, drc, cumul_size;
pci_read_config_dword(pdev, E752X_DRA, &dra);
dra = 0;
for (index=0; index < 4; index++) {
u8 dra_reg;
pci_read_config_byte(pdev, E752X_DRA+index, &dra_reg);
dra |= dra_reg << (index * 8);
}
pci_read_config_dword(pdev, E752X_DRC, &drc);
drc_chan = dual_channel_active(ddrcsr);
drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */