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ARM: dts: imx7ulp-evk: enable lpuart and edma 

Enable lpuart and edma.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Fugang Duan 2019-07-22 10:20:31 +08:00 committed by Dong Aisheng
parent 0a6ce67012
commit 996554bb19
5 changed files with 166 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/Makefile
View File

@ -609,7 +609,9 @@ dtb-$(CONFIG_SOC_IMX7D) += \
imx7s-mba7.dtb \
imx7s-warp.dtb
dtb-$(CONFIG_SOC_IMX7ULP) += \
imx7ulp-evk.dtb
imx7ulp-evk.dtb \
imx7ulp-evkb.dtb \
imx7ulp-evkb-lpuart.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-moxa-uc-8410a.dtb \
ls1021a-qds.dtb \

72
arch/arm/boot/dts/imx7ulp-evk.dts
View File

@ -13,6 +13,11 @@
model = "NXP i.MX7ULP EVK";
compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
aliases {
gpio4 = &rpmsg_gpio0;
gpio5 = &rpmsg_gpio1;
};
chosen {
stdout-path = &lpuart4;
};
@ -30,6 +35,13 @@
status = "okay";
};
modem_reset: modem-reset {
compatible = "gpio-reset";
reset-gpios = <&rpmsg_gpio0 15 GPIO_ACTIVE_LOW>;
reset-delay-us = <1000>;
#reset-cells = <0>;
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -51,14 +63,53 @@
gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
rpmsg_gpio0: rpmsg-gpio0 {
compatible = "fsl,imx-rpmsg-gpio";
port_idx = <0>;
gpio-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&rpmsg_gpio0>;
status = "okay";
};
rpmsg_gpio1: rpmsg-gpio1 {
compatible = "fsl,imx-rpmsg-gpio";
port_idx = <1>;
gpio-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&rpmsg_gpio1>;
status = "okay";
};
};
&lpuart4 {
pinctrl-names = "default";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpuart4>;
pinctrl-1 = <&pinctrl_lpuart4>;
status = "okay";
};
&lpuart6 { /* BT */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpuart6>;
pinctrl-1 = <&pinctrl_lpuart6>;
resets = <&modem_reset>;
status = "okay";
};
&lpuart7 { /* Uart test */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpuart7>;
pinctrl-1 = <&pinctrl_lpuart7>;
status = "disabled";
};
&rpmsg{
/*
* 64K for one rpmsg instance, default using 2 rpmsg instances:
@ -104,6 +155,25 @@
bias-pull-up;
};
pinctrl_lpuart6: lpuart6grp {
fsl,pins = <
IMX7ULP_PAD_PTE10__LPUART6_TX 0x3
IMX7ULP_PAD_PTE11__LPUART6_RX 0x3
IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x3
IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x3
IMX7ULP_PAD_PTE7__PTE7 0x20000 /* BT_REG_ON */
>;
};
pinctrl_lpuart7: lpuart7grp {
fsl,pins = <
IMX7ULP_PAD_PTF14__LPUART7_TX 0x3
IMX7ULP_PAD_PTF15__LPUART7_RX 0x3
IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x3
IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x3
>;
};
pinctrl_pwm0: pwm0grp {
fsl,pins = <
IMX7ULP_PAD_PTF2__TPM4_CH1 0x2

17
arch/arm/boot/dts/imx7ulp-evkb-lpuart.dts 100644
View File

@ -0,0 +1,17 @@
/*
* Copyright 2019 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx7ulp-evkb.dts"
&lpi2c7 {
status = "disabled";
};
&lpuart7 { /* Uart test */
status = "okay";
};

39
arch/arm/boot/dts/imx7ulp-evkb.dts 100644
View File

@ -0,0 +1,39 @@
/*
* Copyright 2019 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx7ulp-evk.dts"
/ {
model = "NXP i.MX7ULP EVKB";
compatible = "fsl,imx7ulp-evkb", "fsl,imx7ulp", "Generic DT based system";
regulators {
reg_sd1_vmmc: sd1_regulator {
status = "disabled";
};
};
usdhc1_pwrseq: usdhc1_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&rpmsg_gpio0 14 GPIO_ACTIVE_LOW>;
post-power-on-delay-ms = <80>;
};
};
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
/delete-property/ vmmc-supply;
mmc-pwrseq = <&usdhc1_pwrseq>;
cap-power-off-card;
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};

39
arch/arm/boot/dts/imx7ulp.dtsi
View File

@ -178,8 +178,10 @@
clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
clock-names = "ipg";
assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
assigned-clock-rates = <48000000>;
dmas = <&edma0 0 20>, <&edma0 0 19>;
dma-names = "tx","rx";
status = "disabled";
};
@ -334,6 +336,33 @@
reg = <0x40800000 0x800000>;
ranges;
edma0: dma-controller@40080000 {
#dma-cells = <2>;
compatible = "nxp,imx7ulp-edma";
reg = <0x40080000 0x2000>,
<0x40210000 0x1000>;
dma-channels = <32>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dma", "dmamux0";
clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
};
lpi2c6: i2c@40a40000 {
compatible = "fsl,imx7ulp-lpi2c";
reg = <0x40a40000 0x10000>;
@ -365,8 +394,10 @@
clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
clock-names = "ipg";
assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
assigned-clock-rates = <48000000>;
dmas = <&edma0 0 22>, <&edma0 0 21>;
dma-names = "tx","rx";
status = "disabled";
};
@ -377,8 +408,10 @@
clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
clock-names = "ipg";
assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
assigned-clock-rates = <48000000>;
dmas = <&edma0 0 24>, <&edma0 0 23>;
dma-names = "tx","rx";
status = "disabled";
};