OMAP2420: hwmod data: add DSS DISPC RFBI VENC
Hwmod needs database of all IPs in a system. This patch generates the hwmod database for OMAP2420 Display Sub System,. Since DSS is also considered as an IP as DISPC, RFBI, name it as dss_core. Acked-by: Benoit Cousson <b-cousson@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>hifive-unleashed-5.1
Senthilvadivu Guruswamy
Tomi Valkeinen
parent
04aa67dec6
commit
996746ca12
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@ -19,6 +19,8 @@
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#include <plat/i2c.h>
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#include <plat/gpio.h>
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#include <plat/mcspi.h>
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#include <plat/l3_2xxx.h>
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#include <plat/l4_2xxx.h>
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#include "omap_hwmod_common_data.h"
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@ -39,6 +41,10 @@ static struct omap_hwmod omap2420_mpu_hwmod;
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static struct omap_hwmod omap2420_iva_hwmod;
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static struct omap_hwmod omap2420_l3_main_hwmod;
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static struct omap_hwmod omap2420_l4_core_hwmod;
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static struct omap_hwmod omap2420_dss_core_hwmod;
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static struct omap_hwmod omap2420_dss_dispc_hwmod;
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static struct omap_hwmod omap2420_dss_rfbi_hwmod;
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static struct omap_hwmod omap2420_dss_venc_hwmod;
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static struct omap_hwmod omap2420_wd_timer2_hwmod;
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static struct omap_hwmod omap2420_gpio1_hwmod;
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static struct omap_hwmod omap2420_gpio2_hwmod;
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@ -67,6 +73,19 @@ static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
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&omap2420_mpu__l3_main,
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};
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/* DSS -> l3 */
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static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
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.master = &omap2420_dss_core_hwmod,
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.slave = &omap2420_l3_main_hwmod,
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.fw = {
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.omap2 = {
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.l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
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.flags = OMAP_FIREWALL_L3,
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}
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},
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* Master interfaces on the L3 interconnect */
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static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
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&omap2420_l3_main__l4_core,
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@ -509,6 +528,291 @@ static struct omap_hwmod omap2420_uart3_hwmod = {
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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};
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/*
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* 'dss' class
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* display sub-system
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*/
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static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap2420_dss_hwmod_class = {
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.name = "dss",
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.sysc = &omap2420_dss_sysc,
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};
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/* dss */
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static struct omap_hwmod_irq_info omap2420_dss_irqs[] = {
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{ .irq = 25 },
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};
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static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = {
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{ .name = "dispc", .dma_req = 5 },
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};
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/* dss */
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/* dss master ports */
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static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
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&omap2420_dss__l3,
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};
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static struct omap_hwmod_addr_space omap2420_dss_addrs[] = {
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{
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.pa_start = 0x48050000,
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.pa_end = 0x480503FF,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_core -> dss */
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static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_dss_core_hwmod,
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.clk = "dss_ick",
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.addr = omap2420_dss_addrs,
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.addr_cnt = ARRAY_SIZE(omap2420_dss_addrs),
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.fw = {
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.omap2 = {
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.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
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.flags = OMAP_FIREWALL_L4,
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}
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},
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* dss slave ports */
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static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
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&omap2420_l4_core__dss,
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};
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static struct omap_hwmod_opt_clk dss_opt_clks[] = {
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{ .role = "tv_clk", .clk = "dss_54m_fck" },
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{ .role = "sys_clk", .clk = "dss2_fck" },
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};
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static struct omap_hwmod omap2420_dss_core_hwmod = {
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.name = "dss_core",
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.class = &omap2420_dss_hwmod_class,
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.main_clk = "dss1_fck", /* instead of dss_fck */
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.mpu_irqs = omap2420_dss_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap2420_dss_irqs),
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.sdma_reqs = omap2420_dss_sdma_chs,
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.sdma_reqs_cnt = ARRAY_SIZE(omap2420_dss_sdma_chs),
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_DSS1_SHIFT,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
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},
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},
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.opt_clks = dss_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
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.slaves = omap2420_dss_slaves,
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.slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves),
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.masters = omap2420_dss_masters,
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.masters_cnt = ARRAY_SIZE(omap2420_dss_masters),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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.flags = HWMOD_NO_IDLEST,
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};
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/*
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* 'dispc' class
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* display controller
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*/
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static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
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SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap2420_dispc_hwmod_class = {
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.name = "dispc",
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.sysc = &omap2420_dispc_sysc,
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};
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static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = {
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{
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.pa_start = 0x48050400,
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.pa_end = 0x480507FF,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_core -> dss_dispc */
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static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_dss_dispc_hwmod,
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.clk = "dss_ick",
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.addr = omap2420_dss_dispc_addrs,
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.addr_cnt = ARRAY_SIZE(omap2420_dss_dispc_addrs),
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.fw = {
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.omap2 = {
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.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
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.flags = OMAP_FIREWALL_L4,
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}
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},
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* dss_dispc slave ports */
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static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
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&omap2420_l4_core__dss_dispc,
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};
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static struct omap_hwmod omap2420_dss_dispc_hwmod = {
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.name = "dss_dispc",
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.class = &omap2420_dispc_hwmod_class,
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.main_clk = "dss1_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_DSS1_SHIFT,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
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},
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},
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.slaves = omap2420_dss_dispc_slaves,
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.slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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.flags = HWMOD_NO_IDLEST,
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};
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/*
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* 'rfbi' class
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* remote frame buffer interface
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*/
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static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
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SYSC_HAS_AUTOIDLE),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap2420_rfbi_hwmod_class = {
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.name = "rfbi",
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.sysc = &omap2420_rfbi_sysc,
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};
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static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = {
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{
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.pa_start = 0x48050800,
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.pa_end = 0x48050BFF,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_core -> dss_rfbi */
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static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_dss_rfbi_hwmod,
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.clk = "dss_ick",
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.addr = omap2420_dss_rfbi_addrs,
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.addr_cnt = ARRAY_SIZE(omap2420_dss_rfbi_addrs),
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.fw = {
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.omap2 = {
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.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
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.flags = OMAP_FIREWALL_L4,
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}
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},
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* dss_rfbi slave ports */
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static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
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&omap2420_l4_core__dss_rfbi,
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};
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static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
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.name = "dss_rfbi",
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.class = &omap2420_rfbi_hwmod_class,
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.main_clk = "dss1_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_DSS1_SHIFT,
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.module_offs = CORE_MOD,
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},
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},
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.slaves = omap2420_dss_rfbi_slaves,
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.slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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.flags = HWMOD_NO_IDLEST,
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};
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/*
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* 'venc' class
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* video encoder
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*/
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static struct omap_hwmod_class omap2420_venc_hwmod_class = {
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.name = "venc",
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};
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/* dss_venc */
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static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = {
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{
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.pa_start = 0x48050C00,
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.pa_end = 0x48050FFF,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_core -> dss_venc */
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static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_dss_venc_hwmod,
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.clk = "dss_54m_fck",
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.addr = omap2420_dss_venc_addrs,
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.addr_cnt = ARRAY_SIZE(omap2420_dss_venc_addrs),
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.fw = {
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.omap2 = {
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.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
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.flags = OMAP_FIREWALL_L4,
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}
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},
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* dss_venc slave ports */
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static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
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&omap2420_l4_core__dss_venc,
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};
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static struct omap_hwmod omap2420_dss_venc_hwmod = {
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.name = "dss_venc",
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.class = &omap2420_venc_hwmod_class,
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.main_clk = "dss1_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_DSS1_SHIFT,
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.module_offs = CORE_MOD,
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},
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},
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.slaves = omap2420_dss_venc_slaves,
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.slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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.flags = HWMOD_NO_IDLEST,
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};
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/* I2C common */
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static struct omap_hwmod_class_sysconfig i2c_sysc = {
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.rev_offs = 0x00,
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@ -1026,6 +1330,12 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
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&omap2420_uart1_hwmod,
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&omap2420_uart2_hwmod,
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&omap2420_uart3_hwmod,
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/* dss class */
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&omap2420_dss_core_hwmod,
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&omap2420_dss_dispc_hwmod,
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&omap2420_dss_rfbi_hwmod,
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&omap2420_dss_venc_hwmod,
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/* i2c class */
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&omap2420_i2c1_hwmod,
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&omap2420_i2c2_hwmod,
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@ -0,0 +1,20 @@
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/*
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* arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions
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*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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* Sumit Semwal
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
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#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
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/* L3 CONNIDs */
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/* Display Sub system (DSS) */
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#define OMAP2_L3_CORE_FW_CONNID_DSS 8
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#endif
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@ -0,0 +1,24 @@
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/*
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* arch/arm/plat-omap/include/plat/l4_2xxx.h - L4 firewall definitions
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*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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* Sumit Semwal
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
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#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
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/* L4 CORE */
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/* Display Sub system (DSS) */
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#define OMAP2420_L4_CORE_FW_DSS_CORE_REGION 28
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#define OMAP2420_L4_CORE_FW_DSS_DISPC_REGION 29
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#define OMAP2420_L4_CORE_FW_DSS_RFBI_REGION 30
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#define OMAP2420_L4_CORE_FW_DSS_VENC_REGION 31
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#define OMAP2420_L4_CORE_FW_DSS_TA_REGION 32
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#endif
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