arm64: dts: allwinner: a64: enable DVFS

Add CPU regulator, CPU clock and operation points to enable DVFS on A64

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>

arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts

@@ -65,6 +65,10 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&reg_dcdc2>;
+};
+
 &csi {
 	status = "okay";
 

arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts

@@ -108,6 +108,10 @@
 	status = "okay";
 };
 
+&cpu0 {
+	cpu-supply = <&reg_dcdc2>;
+};
+
 &dai {
 	status = "okay";
 };

arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts

@@ -87,6 +87,10 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&reg_dcdc2>;
+};
+
 &de {
 	status = "okay";
 };

arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts

@@ -87,6 +87,10 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&reg_dcdc2>;
+};
+
 &de {
 	status = "okay";
 };

arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts

@@ -84,6 +84,10 @@
 	status = "okay";
 };
 
+&cpu0 {
+	cpu-supply = <&reg_dcdc2>;
+};
+
 &dai {
 	status = "okay";
 };

arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts

@@ -98,6 +98,10 @@
 	status = "okay";
 };
 
+&cpu0 {
+	cpu-supply = <&reg_dcdc2>;
+};
+
 &dai {
 	status = "okay";
 };

arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts

@@ -100,6 +100,10 @@
 	status = "okay";
 };
 
+&cpu0 {
+	cpu-supply = <&reg_dcdc2>;
+};
+
 &dai {
 	status = "okay";
 };

arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi

@@ -51,6 +51,10 @@
 	cpvdd-supply = <&reg_eldo1>;
 };
 
+&cpu0 {
+	cpu-supply = <&reg_dcdc2>;
+};
+
 &mmc0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins>;

arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi

@@ -80,6 +80,52 @@
 		};
 	};
 
+	cpu0_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-648000000 {
+			opp-hz = /bits/ 64 <648000000>;
+			opp-microvolt = <1040000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-816000000 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-912000000 {
+			opp-hz = /bits/ 64 <912000000>;
+			opp-microvolt = <1120000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-960000000 {
+			opp-hz = /bits/ 64 <960000000>;
+			opp-microvolt = <1160000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-1008000000 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <1200000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-1056000000 {
+			opp-hz = /bits/ 64 <1056000000>;
+			opp-microvolt = <1240000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-1104000000 {
+			opp-hz = /bits/ 64 <1104000000>;
+			opp-microvolt = <1260000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-1152000000 {
+			opp-hz = /bits/ 64 <1152000000>;
+			opp-microvolt = <1300000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -90,6 +136,7 @@
 			reg = <0>;
 			enable-method = "psci";
 			next-level-cache = <&L2>;
+			operating-points-v2 = <&cpu0_opp_table>;
 		};
 
 		cpu1: cpu@1 {
@@ -98,6 +145,7 @@
 			reg = <1>;
 			enable-method = "psci";
 			next-level-cache = <&L2>;
+			operating-points-v2 = <&cpu0_opp_table>;
 		};
 
 		cpu2: cpu@2 {
@@ -106,6 +154,7 @@
 			reg = <2>;
 			enable-method = "psci";
 			next-level-cache = <&L2>;
+			operating-points-v2 = <&cpu0_opp_table>;
 		};
 
 		cpu3: cpu@3 {
@@ -114,6 +163,7 @@
 			reg = <3>;
 			enable-method = "psci";
 			next-level-cache = <&L2>;
+			operating-points-v2 = <&cpu0_opp_table>;
 		};
 
 		L2: l2-cache {