drm/i915: Move Haswell registers to separate whitelist table
Now that we can whitelist registers only on Haswell, move HSW_SCRATCH1 and HSW_ROW_CHICKEN3 into a separate Haswell only table. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Cc: Francisco Jerez <currojerez@riseup.net> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1457335830-30923-4-git-send-email-jordan.l.justen@intel.com
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@ -472,6 +472,9 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
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REG32(GEN7_L3SQCREG1),
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REG32(GEN7_L3CNTLREG2),
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REG32(GEN7_L3CNTLREG3),
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};
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static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
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REG32(HSW_SCRATCH1,
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.mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
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.value = 0),
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@ -519,6 +522,7 @@ static const struct drm_i915_reg_table ivb_blt_reg_tables[] = {
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static const struct drm_i915_reg_table hsw_render_reg_tables[] = {
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{ gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },
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{ hsw_render_regs, ARRAY_SIZE(hsw_render_regs), false },
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{ hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },
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};
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