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x86: unmask CPUID levels on Intel CPUs, fix 

Impact: fix boot hang on pre-model-15 Intel CPUs

rdmsrl_safe() does not work in very early bootup code yet, because we
dont have the pagefault handler installed yet so exception section
does not get parsed. rdmsr_safe() will just crash and hang the bootup.

So limit the MSR_IA32_MISC_ENABLE MSR read to those CPU types that
support it.

Signed-off-by: Ingo Molnar <mingo@elte.hu>
hifive-unleashed-5.1
Ingo Molnar 2009-01-26 04:30:41 +01:00
parent ef5fa0ab24
commit 99fb4d349d
1 changed files with 10 additions and 7 deletions
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17
arch/x86/kernel/cpu/intel.c
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@ -29,14 +29,17 @@
static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
{
u64 misc_enable;
/* Unmask CPUID levels if masked: */
if (c->x86 == 6 && c->x86_model >= 15) {
u64 misc_enable;
/* Unmask CPUID levels if masked */
if (!rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_enable) &&
(misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID)) {
misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
c->cpuid_level = cpuid_eax(0);
rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
c->cpuid_level = cpuid_eax(0);
}
}
if ((c->x86 == 0xf && c->x86_model >= 0x03) ||