Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next-queued
Backmerge request by Jani to get at
commit 249c4f538b
Author: Deepak M <m.deepak@intel.com>
Date: Wed Mar 30 17:03:39 2016 +0300
drm: Add new DCS commands in the enum list
Some simple conflicts in intel_dp.c.
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
This commit is contained in:
Daniel Vetter
commit
9a652cc01e
5
.mailmap
5
.mailmap
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|
@ -48,6 +48,9 @@ Felix Kuhling <fxkuehl@gmx.de>
|
|||
Felix Moeller <felix@derklecks.de>
|
||||
Filipe Lautert <filipe@icewall.org>
|
||||
Franck Bui-Huu <vagabon.xyz@gmail.com>
|
||||
Frank Rowand <frowand.list@gmail.com> <frowand@mvista.com>
|
||||
Frank Rowand <frowand.list@gmail.com> <frank.rowand@am.sony.com>
|
||||
Frank Rowand <frowand.list@gmail.com> <frank.rowand@sonymobile.com>
|
||||
Frank Zago <fzago@systemfabricworks.com>
|
||||
Greg Kroah-Hartman <greg@echidna.(none)>
|
||||
Greg Kroah-Hartman <gregkh@suse.de>
|
||||
|
|
@ -66,6 +69,7 @@ Jean Tourrilhes <jt@hpl.hp.com>
|
|||
Jeff Garzik <jgarzik@pretzel.yyz.us>
|
||||
Jens Axboe <axboe@suse.de>
|
||||
Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
|
||||
John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
|
||||
John Stultz <johnstul@us.ibm.com>
|
||||
<josh@joshtriplett.org> <josh@freedesktop.org>
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||||
<josh@joshtriplett.org> <josh@kernel.org>
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||||
|
|
@ -79,6 +83,7 @@ Kay Sievers <kay.sievers@vrfy.org>
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|||
Kenneth W Chen <kenneth.w.chen@intel.com>
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||||
Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com>
|
||||
Koushik <raghavendra.koushik@neterion.com>
|
||||
Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski.k@gmail.com>
|
||||
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
Leonid I Ananiev <leonid.i.ananiev@intel.com>
|
||||
Linas Vepstas <linas@austin.ibm.com>
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||||
|
|
|
|||
|
|
@ -1615,6 +1615,11 @@ void intel_crt_init(struct drm_device *dev)
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!Pdrivers/gpu/drm/drm_fb_helper.c fbdev helpers
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||||
!Edrivers/gpu/drm/drm_fb_helper.c
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!Iinclude/drm/drm_fb_helper.h
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</sect2>
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<sect2>
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<title>Framebuffer CMA Helper Functions Reference</title>
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!Pdrivers/gpu/drm/drm_fb_cma_helper.c framebuffer cma helper functions
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!Edrivers/gpu/drm/drm_fb_cma_helper.c
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</sect2>
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<sect2>
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<title>Display Port Helper Functions Reference</title>
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@ -1677,17 +1682,23 @@ void intel_crt_init(struct drm_device *dev)
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!Pdrivers/gpu/drm/drm_crtc.c Tile group
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</sect2>
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<sect2>
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<title>Bridges</title>
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<title>Bridges</title>
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<sect3>
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<title>Overview</title>
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<title>Overview</title>
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!Pdrivers/gpu/drm/drm_bridge.c overview
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</sect3>
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<sect3>
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<title>Default bridge callback sequence</title>
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<title>Default bridge callback sequence</title>
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!Pdrivers/gpu/drm/drm_bridge.c bridge callbacks
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</sect3>
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!Edrivers/gpu/drm/drm_bridge.c
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</sect2>
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<sect2>
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<title>Panel Helper Reference</title>
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!Iinclude/drm/drm_panel.h
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!Edrivers/gpu/drm/drm_panel.c
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!Pdrivers/gpu/drm/drm_panel.c drm panel
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</sect2>
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</sect1>
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<!-- Internals: kms properties -->
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@ -1823,7 +1834,7 @@ void intel_crt_init(struct drm_device *dev)
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</tr>
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<tr>
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<td rowspan="42" valign="top" >DRM</td>
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<td valign="top" >Generic</td>
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<td rowspan="2" valign="top" >Generic</td>
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<td valign="top" >“rotation”</td>
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<td valign="top" >BITMASK</td>
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<td valign="top" >{ 0, "rotate-0" },
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|
|
@ -1838,6 +1849,13 @@ void intel_crt_init(struct drm_device *dev)
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image along the specified axis prior to rotation</td>
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</tr>
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<tr>
|
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<td valign="top" >“scaling mode”</td>
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<td valign="top" >ENUM</td>
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<td valign="top" >{ "None", "Full", "Center", "Full aspect" }</td>
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<td valign="top" >Connector</td>
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<td valign="top" >Supported by: amdgpu, gma500, i915, nouveau and radeon.</td>
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</tr>
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<tr>
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<td rowspan="5" valign="top" >Connector</td>
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<td valign="top" >“EDID”</td>
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<td valign="top" >BLOB | IMMUTABLE</td>
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|
|
@ -2074,21 +2092,12 @@ void intel_crt_init(struct drm_device *dev)
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<td valign="top" >property to suggest an Y offset for a connector</td>
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</tr>
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<tr>
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<td rowspan="8" valign="top" >Optional</td>
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<td valign="top" >“scaling mode”</td>
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<td valign="top" >ENUM</td>
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<td valign="top" >{ "None", "Full", "Center", "Full aspect" }</td>
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<td valign="top" >Connector</td>
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<td valign="top" >TBD</td>
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</tr>
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<tr>
|
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<td rowspan="7" valign="top" >Optional</td>
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||||
<td valign="top" >"aspect ratio"</td>
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<td valign="top" >ENUM</td>
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||||
<td valign="top" >{ "None", "4:3", "16:9" }</td>
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<td valign="top" >Connector</td>
|
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<td valign="top" >DRM property to set aspect ratio from user space app.
|
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This enum is made generic to allow addition of custom aspect
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ratios.</td>
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<td valign="top" >TDB</td>
|
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</tr>
|
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<tr>
|
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<td valign="top" >“dirty”</td>
|
||||
|
|
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|
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@ -2,7 +2,7 @@
|
|||
|
||||
The ARC HS can be configured with a pipeline performance monitor for counting
|
||||
CPU and cache events like cache misses and hits. Like conventional PCT there
|
||||
are 100+ hardware conditions dynamically mapped to upto 32 counters.
|
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are 100+ hardware conditions dynamically mapped to up to 32 counters.
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It also supports overflow interrupts.
|
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|
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Required properties:
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||||
|
|
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|
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@ -2,7 +2,7 @@
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|||
|
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The ARC700 can be configured with a pipeline performance monitor for counting
|
||||
CPU and cache events like cache misses and hits. Like conventional PCT there
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||||
are 100+ hardware conditions dynamically mapped to upto 32 counters
|
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are 100+ hardware conditions dynamically mapped to up to 32 counters
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|
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Note that:
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* The ARC 700 PCT does not support interrupts; although HW events may be
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|
|
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@ -192,7 +192,6 @@ nodes to be present and contain the properties described below.
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can be one of:
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"allwinner,sun6i-a31"
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"allwinner,sun8i-a23"
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"arm,psci"
|
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"arm,realview-smp"
|
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"brcm,bcm-nsp-smp"
|
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"brcm,brahma-b15"
|
||||
|
|
|
|||
|
|
@ -32,6 +32,10 @@ Optional properties:
|
|||
- target-supply : regulator for SATA target power
|
||||
- phys : reference to the SATA PHY node
|
||||
- phy-names : must be "sata-phy"
|
||||
- ports-implemented : Mask that indicates which ports that the HBA supports
|
||||
are available for software to use. Useful if PORTS_IMPL
|
||||
is not programmed by the BIOS, which is true with
|
||||
some embedded SOC's.
|
||||
|
||||
Required properties when using sub-nodes:
|
||||
- #address-cells : number of cells to encode an address
|
||||
|
|
|
|||
|
|
@ -35,12 +35,22 @@ Optional properties for HDMI:
|
|||
as an interrupt/status bit in the HDMI controller
|
||||
itself). See bindings/pinctrl/brcm,bcm2835-gpio.txt
|
||||
|
||||
Required properties for DPI:
|
||||
- compatible: Should be "brcm,bcm2835-dpi"
|
||||
- reg: Physical base address and length of the registers
|
||||
- clocks: a) core: The core clock the unit runs on
|
||||
b) pixel: The pixel clock that feeds the pixelvalve
|
||||
- port: Port node with a single endpoint connecting to the panel
|
||||
device, as defined in [1]
|
||||
|
||||
Required properties for V3D:
|
||||
- compatible: Should be "brcm,bcm2835-v3d"
|
||||
- reg: Physical base address and length of the V3D's registers
|
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- interrupts: The interrupt number
|
||||
See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
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||||
|
||||
[1] Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
Example:
|
||||
pixelvalve@7e807000 {
|
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compatible = "brcm,bcm2835-pixelvalve2";
|
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|
|
@ -66,6 +76,22 @@ hdmi: hdmi@7e902000 {
|
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clock-names = "pixel", "hdmi";
|
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};
|
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|
||||
dpi: dpi@7e208000 {
|
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compatible = "brcm,bcm2835-dpi";
|
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reg = <0x7e208000 0x8c>;
|
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clocks = <&clocks BCM2835_CLOCK_VPU>,
|
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<&clocks BCM2835_CLOCK_DPI>;
|
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clock-names = "core", "pixel";
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#address-cells = <1>;
|
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#size-cells = <0>;
|
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|
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port {
|
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dpi_out: endpoint@0 {
|
||||
remote-endpoint = <&panel_in>;
|
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};
|
||||
};
|
||||
};
|
||||
|
||||
v3d: v3d@7ec00000 {
|
||||
compatible = "brcm,bcm2835-v3d";
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reg = <0x7ec00000 0x1000>;
|
||||
|
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@ -75,3 +101,13 @@ v3d: v3d@7ec00000 {
|
|||
vc4: gpu {
|
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compatible = "brcm,bcm2835-vc4";
|
||||
};
|
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|
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panel: panel {
|
||||
compatible = "ontat,yx700wv03", "simple-panel";
|
||||
|
||||
port {
|
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panel_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
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@ -0,0 +1,52 @@
|
|||
Analogix Display Port bridge bindings
|
||||
|
||||
Required properties for dp-controller:
|
||||
-compatible:
|
||||
platform specific such as:
|
||||
* "samsung,exynos5-dp"
|
||||
* "rockchip,rk3288-dp"
|
||||
-reg:
|
||||
physical base address of the controller and length
|
||||
of memory mapped region.
|
||||
-interrupts:
|
||||
interrupt combiner values.
|
||||
-clocks:
|
||||
from common clock binding: handle to dp clock.
|
||||
-clock-names:
|
||||
from common clock binding: Shall be "dp".
|
||||
-interrupt-parent:
|
||||
phandle to Interrupt combiner node.
|
||||
-phys:
|
||||
from general PHY binding: the phandle for the PHY device.
|
||||
-phy-names:
|
||||
from general PHY binding: Should be "dp".
|
||||
|
||||
Optional properties for dp-controller:
|
||||
-force-hpd:
|
||||
Indicate driver need force hpd when hpd detect failed, this
|
||||
is used for some eDP screen which don't have hpd signal.
|
||||
-hpd-gpios:
|
||||
Hotplug detect GPIO.
|
||||
Indicates which GPIO should be used for hotplug detection
|
||||
-port@[X]: SoC specific port nodes with endpoint definitions as defined
|
||||
in Documentation/devicetree/bindings/media/video-interfaces.txt,
|
||||
please refer to the SoC specific binding document:
|
||||
* Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
|
||||
* Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
|
||||
|
||||
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Example:
|
||||
|
||||
dp-controller {
|
||||
compatible = "samsung,exynos5-dp";
|
||||
reg = <0x145b0000 0x10000>;
|
||||
interrupts = <10 3>;
|
||||
interrupt-parent = <&combiner>;
|
||||
clocks = <&clock 342>;
|
||||
clock-names = "dp";
|
||||
|
||||
phys = <&dp_phy>;
|
||||
phy-names = "dp";
|
||||
};
|
||||
|
|
@ -5,7 +5,8 @@ Exynos series of SoCs which transfers the image data from a video memory
|
|||
buffer to an external LCD interface.
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be "samsung,exynos5433-decon";
|
||||
- compatible: value should be one of:
|
||||
"samsung,exynos5433-decon", "samsung,exynos5433-decon-tv";
|
||||
- reg: physical base address and length of the DECON registers set.
|
||||
- interrupts: should contain a list of all DECON IP block interrupts in the
|
||||
order: VSYNC, LCD_SYSTEM. The interrupt specifier format
|
||||
|
|
@ -16,7 +17,7 @@ Required properties:
|
|||
- clocks: must include clock specifiers corresponding to entries in the
|
||||
clock-names property.
|
||||
- clock-names: list of clock names sorted in the same order as the clocks
|
||||
property. Must contain "aclk_decon", "aclk_smmu_decon0x",
|
||||
property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x",
|
||||
"aclk_xiu_decon0x", "pclk_smmu_decon0x", clk_decon_vclk",
|
||||
"sclk_decon_eclk"
|
||||
- ports: contains a port which is connected to mic node. address-cells and
|
||||
|
|
|
|||
|
|
@ -1,20 +1,3 @@
|
|||
Device-Tree bindings for Samsung Exynos Embedded DisplayPort Transmitter(eDP)
|
||||
|
||||
DisplayPort is industry standard to accommodate the growing board adoption
|
||||
of digital display technology within the PC and CE industries.
|
||||
It consolidates the internal and external connection methods to reduce device
|
||||
complexity and cost. It also supports necessary features for important cross
|
||||
industry applications and provides performance scalability to enable the next
|
||||
generation of displays that feature higher color depths, refresh rates, and
|
||||
display resolutions.
|
||||
|
||||
eDP (embedded display port) device is compliant with Embedded DisplayPort
|
||||
standard as follows,
|
||||
- DisplayPort standard 1.1a for Exynos5250 and Exynos5260.
|
||||
- DisplayPort standard 1.3 for Exynos5422s and Exynos5800.
|
||||
|
||||
eDP resides between FIMD and panel or FIMD and bridge such as LVDS.
|
||||
|
||||
The Exynos display port interface should be configured based on
|
||||
the type of panel connected to it.
|
||||
|
||||
|
|
@ -48,26 +31,6 @@ Required properties for dp-controller:
|
|||
from general PHY binding: the phandle for the PHY device.
|
||||
-phy-names:
|
||||
from general PHY binding: Should be "dp".
|
||||
-samsung,color-space:
|
||||
input video data format.
|
||||
COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
|
||||
-samsung,dynamic-range:
|
||||
dynamic range for input video data.
|
||||
VESA = 0, CEA = 1
|
||||
-samsung,ycbcr-coeff:
|
||||
YCbCr co-efficients for input video.
|
||||
COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
|
||||
-samsung,color-depth:
|
||||
number of bits per colour component.
|
||||
COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
|
||||
-samsung,link-rate:
|
||||
link rate supported by the panel.
|
||||
LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
|
||||
-samsung,lane-count:
|
||||
number of lanes supported by the panel.
|
||||
LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
|
||||
- display-timings: timings for the connected panel as described by
|
||||
Documentation/devicetree/bindings/display/display-timing.txt
|
||||
|
||||
Optional properties for dp-controller:
|
||||
-interlaced:
|
||||
|
|
@ -83,17 +46,31 @@ Optional properties for dp-controller:
|
|||
Hotplug detect GPIO.
|
||||
Indicates which GPIO should be used for hotplug
|
||||
detection
|
||||
Video interfaces:
|
||||
Device node can contain video interface port nodes according to [1].
|
||||
The following are properties specific to those nodes:
|
||||
-video interfaces: Device node can contain video interface port
|
||||
nodes according to [1].
|
||||
- display-timings: timings for the connected panel as described by
|
||||
Documentation/devicetree/bindings/display/panel/display-timing.txt
|
||||
|
||||
endpoint node connected to bridge or panel node:
|
||||
- remote-endpoint: specifies the endpoint in panel or bridge node.
|
||||
This node is required in all kinds of exynos dp
|
||||
to represent the connection between dp and bridge
|
||||
or dp and panel.
|
||||
For the below properties, please refer to Analogix DP binding document:
|
||||
* Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
|
||||
-phys (required)
|
||||
-phy-names (required)
|
||||
-hpd-gpios (optional)
|
||||
force-hpd (optional)
|
||||
|
||||
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
Deprecated properties for DisplayPort:
|
||||
-interlaced: deprecated prop that can parsed from drm_display_mode.
|
||||
-vsync-active-high: deprecated prop that can parsed from drm_display_mode.
|
||||
-hsync-active-high: deprecated prop that can parsed from drm_display_mode.
|
||||
-samsung,ycbcr-coeff: deprecated prop that can parsed from drm_display_mode.
|
||||
-samsung,dynamic-range: deprecated prop that can parsed from drm_display_mode.
|
||||
-samsung,color-space: deprecated prop that can parsed from drm_display_info.
|
||||
-samsung,color-depth: deprecated prop that can parsed from drm_display_info.
|
||||
-samsung,link-rate: deprecated prop that can reading from monitor by dpcd method.
|
||||
-samsung,lane-count: deprecated prop that can reading from monitor by dpcd method.
|
||||
-samsung,hpd-gpio: deprecated name for hpd-gpios.
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Example:
|
||||
|
||||
|
|
@ -112,13 +89,6 @@ SOC specific portion:
|
|||
|
||||
Board Specific portion:
|
||||
dp-controller {
|
||||
samsung,color-space = <0>;
|
||||
samsung,dynamic-range = <0>;
|
||||
samsung,ycbcr-coeff = <0>;
|
||||
samsung,color-depth = <1>;
|
||||
samsung,link-rate = <0x0a>;
|
||||
samsung,lane-count = <4>;
|
||||
|
||||
display-timings {
|
||||
native-mode = <&lcd_timing>;
|
||||
lcd_timing: 1366x768 {
|
||||
|
|
@ -135,18 +105,9 @@ Board Specific portion:
|
|||
};
|
||||
|
||||
ports {
|
||||
port {
|
||||
port@0 {
|
||||
dp_out: endpoint {
|
||||
remote-endpoint = <&dp_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel {
|
||||
...
|
||||
port {
|
||||
dp_in: endpoint {
|
||||
remote-endpoint = <&dp_out>;
|
||||
remote-endpoint = <&bridge_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@ Required properties:
|
|||
1) "samsung,exynos4210-hdmi"
|
||||
2) "samsung,exynos4212-hdmi"
|
||||
3) "samsung,exynos5420-hdmi"
|
||||
4) "samsung,exynos5433-hdmi"
|
||||
- reg: physical base address of the hdmi and length of memory mapped
|
||||
region.
|
||||
- interrupts: interrupt number to the cpu.
|
||||
|
|
@ -12,6 +13,11 @@ Required properties:
|
|||
a) phandle of the gpio controller node.
|
||||
b) pin number within the gpio controller.
|
||||
c) optional flags and pull up/down.
|
||||
- ddc: phandle to the hdmi ddc node
|
||||
- phy: phandle to the hdmi phy node
|
||||
- samsung,syscon-phandle: phandle for system controller node for PMU.
|
||||
|
||||
Required properties for Exynos 4210, 4212, 5420 and 5433:
|
||||
- clocks: list of clock IDs from SoC clock driver.
|
||||
a) hdmi: Gate of HDMI IP bus clock.
|
||||
b) sclk_hdmi: Gate of HDMI special clock.
|
||||
|
|
@ -25,9 +31,24 @@ Required properties:
|
|||
sclk_pixel.
|
||||
- clock-names: aliases as per driver requirements for above clock IDs:
|
||||
"hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy" and "mout_hdmi".
|
||||
- ddc: phandle to the hdmi ddc node
|
||||
- phy: phandle to the hdmi phy node
|
||||
- samsung,syscon-phandle: phandle for system controller node for PMU.
|
||||
|
||||
Required properties for Exynos 5433:
|
||||
- clocks: list of clock specifiers according to common clock bindings.
|
||||
a) hdmi_pclk: Gate of HDMI IP APB bus.
|
||||
b) hdmi_i_pclk: Gate of HDMI-PHY IP APB bus.
|
||||
d) i_tmds_clk: Gate of HDMI TMDS clock.
|
||||
e) i_pixel_clk: Gate of HDMI pixel clock.
|
||||
f) i_spdif_clk: Gate of HDMI SPDIF clock.
|
||||
g) oscclk: Oscillator clock, used as parent of following *_user clocks
|
||||
in case HDMI-PHY is not operational.
|
||||
h) tmds_clko: TMDS clock generated by HDMI-PHY.
|
||||
i) tmds_clko_user: MUX used to switch between oscclk and tmds_clko,
|
||||
respectively if HDMI-PHY is off and operational.
|
||||
j) pixel_clko: Pixel clock generated by HDMI-PHY.
|
||||
k) pixel_clko_user: MUX used to switch between oscclk and pixel_clko,
|
||||
respectively if HDMI-PHY is off and operational.
|
||||
- clock-names: aliases for above clock specfiers.
|
||||
- samsung,sysreg: handle to syscon used to control the system registers.
|
||||
|
||||
Example:
|
||||
|
||||
|
|
|
|||
|
|
@ -6,17 +6,24 @@ Required properties:
|
|||
* "fsl,vf610-dcu".
|
||||
|
||||
- reg: Address and length of the register set for dcu.
|
||||
- clocks: From common clock binding: handle to dcu clock.
|
||||
- clock-names: From common clock binding: Shall be "dcu".
|
||||
- clocks: Handle to "dcu" and "pix" clock (in the order below)
|
||||
This can be the same clock (e.g. LS1021a)
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Should be "dcu" and "pix"
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- big-endian Boolean property, LS1021A DCU registers are big-endian.
|
||||
- fsl,panel: The phandle to panel node.
|
||||
|
||||
Optional properties:
|
||||
- fsl,tcon: The phandle to the timing controller node.
|
||||
|
||||
Examples:
|
||||
dcu: dcu@2ce0000 {
|
||||
compatible = "fsl,ls1021a-dcu";
|
||||
reg = <0x0 0x2ce0000 0x0 0x10000>;
|
||||
clocks = <&platform_clk 0>;
|
||||
clock-names = "dcu";
|
||||
clocks = <&platform_clk 0>, <&platform_clk 0>;
|
||||
clock-names = "dcu", "pix";
|
||||
big-endian;
|
||||
fsl,panel = <&panel>;
|
||||
fsl,tcon = <&tcon>;
|
||||
};
|
||||
|
|
|
|||
18
Documentation/devicetree/bindings/display/fsl,tcon.txt
Normal file
18
Documentation/devicetree/bindings/display/fsl,tcon.txt
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
Device Tree bindings for Freescale TCON Driver
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of
|
||||
* "fsl,vf610-tcon".
|
||||
|
||||
- reg: Address and length of the register set for tcon.
|
||||
- clocks: From common clock binding: handle to tcon ipg clock.
|
||||
- clock-names: From common clock binding: Shall be "ipg".
|
||||
|
||||
Examples:
|
||||
timing-controller@4003d000 {
|
||||
compatible = "fsl,vf610-tcon";
|
||||
reg = <0x4003d000 0x1000>;
|
||||
clocks = <&clks VF610_CLK_TCON0>;
|
||||
clock-names = "ipg";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver
|
||||
|
||||
A DSI Host Controller resides in the middle of display controller and external
|
||||
HDMI converter or panel.
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be "hisilicon,hi6220-dsi".
|
||||
- reg: physical base address and length of dsi controller's registers.
|
||||
- clocks: contains APB clock phandle + clock-specifier pair.
|
||||
- clock-names: should be "pclk".
|
||||
- ports: contains DSI controller input and output sub port.
|
||||
The input port connects to ADE output port with the reg value "0".
|
||||
The output port with the reg value "1", it could connect to panel or
|
||||
any other bridge endpoints.
|
||||
See Documentation/devicetree/bindings/graph.txt for more device graph info.
|
||||
|
||||
A example of HiKey board hi6220 SoC and board specific DT entry:
|
||||
Example:
|
||||
|
||||
SoC specific:
|
||||
dsi: dsi@f4107800 {
|
||||
compatible = "hisilicon,hi6220-dsi";
|
||||
reg = <0x0 0xf4107800 0x0 0x100>;
|
||||
clocks = <&media_ctrl HI6220_DSI_PCLK>;
|
||||
clock-names = "pclk";
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* 0 for input port */
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi_in: endpoint {
|
||||
remote-endpoint = <&ade_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Board specific:
|
||||
&dsi {
|
||||
status = "ok";
|
||||
|
||||
ports {
|
||||
/* 1 for output port */
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
dsi_out0: endpoint@0 {
|
||||
remote-endpoint = <&adv7533_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
...
|
||||
|
||||
adv7533: adv7533@39 {
|
||||
...
|
||||
|
||||
port {
|
||||
adv7533_in: endpoint {
|
||||
remote-endpoint = <&dsi_out0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
Device-Tree bindings for hisilicon ADE display controller driver
|
||||
|
||||
ADE (Advanced Display Engine) is the display controller which grab image
|
||||
data from memory, do composition, do post image processing, generate RGB
|
||||
timing stream and transfer to DSI.
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be "hisilicon,hi6220-ade".
|
||||
- reg: physical base address and length of the ADE controller's registers.
|
||||
- hisilicon,noc-syscon: ADE NOC QoS syscon.
|
||||
- resets: The ADE reset controller node.
|
||||
- interrupt: the ldi vblank interrupt number used.
|
||||
- clocks: a list of phandle + clock-specifier pairs, one for each entry
|
||||
in clock-names.
|
||||
- clock-names: should contain:
|
||||
"clk_ade_core" for the ADE core clock.
|
||||
"clk_codec_jpeg" for the media NOC QoS clock, which use the same clock with
|
||||
jpeg codec.
|
||||
"clk_ade_pix" for the ADE pixel clok.
|
||||
- assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
|
||||
phandle + clock-specifier pairs.
|
||||
- assigned-clock-rates: clock rates, one for each entry in assigned-clocks.
|
||||
The rate of "clk_ade_core" could be "360000000" or "180000000";
|
||||
The rate of "clk_codec_jpeg" could be or less than "1440000000".
|
||||
These rate values could be configured according to performance and power
|
||||
consumption.
|
||||
- port: the output port. This contains one endpoint subnode, with its
|
||||
remote-endpoint set to the phandle of the connected DSI input endpoint.
|
||||
See Documentation/devicetree/bindings/graph.txt for more device graph info.
|
||||
|
||||
Optional properties:
|
||||
- dma-coherent: Present if dma operations are coherent.
|
||||
|
||||
|
||||
A example of HiKey board hi6220 SoC specific DT entry:
|
||||
Example:
|
||||
|
||||
ade: ade@f4100000 {
|
||||
compatible = "hisilicon,hi6220-ade";
|
||||
reg = <0x0 0xf4100000 0x0 0x7800>;
|
||||
reg-names = "ade_base";
|
||||
hisilicon,noc-syscon = <&medianoc_ade>;
|
||||
resets = <&media_ctrl MEDIA_ADE>;
|
||||
interrupts = <0 115 4>; /* ldi interrupt */
|
||||
|
||||
clocks = <&media_ctrl HI6220_ADE_CORE>,
|
||||
<&media_ctrl HI6220_CODEC_JPEG>,
|
||||
<&media_ctrl HI6220_ADE_PIX_SRC>;
|
||||
/*clock name*/
|
||||
clock-names = "clk_ade_core",
|
||||
"clk_codec_jpeg",
|
||||
"clk_ade_pix";
|
||||
|
||||
assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
|
||||
<&media_ctrl HI6220_CODEC_JPEG>;
|
||||
assigned-clock-rates = <360000000>, <288000000>;
|
||||
dma-coherent;
|
||||
|
||||
port {
|
||||
ade_out: endpoint {
|
||||
remote-endpoint = <&dsi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,203 @@
|
|||
Mediatek display subsystem
|
||||
==========================
|
||||
|
||||
The Mediatek display subsystem consists of various DISP function blocks in the
|
||||
MMSYS register space. The connections between them can be configured by output
|
||||
and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
|
||||
of frame signal are distributed to the other function blocks by a DISP_MUTEX
|
||||
function block.
|
||||
|
||||
All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt.
|
||||
|
||||
DISP function blocks
|
||||
====================
|
||||
|
||||
A display stream starts at a source function block that reads pixel data from
|
||||
memory and ends with a sink function block that drives pixels on a display
|
||||
interface, or writes pixels back to memory. All DISP function blocks have
|
||||
their own register space, interrupt, and clock gate. The blocks that can
|
||||
access memory additionally have to list the IOMMU and local arbiter they are
|
||||
connected to.
|
||||
|
||||
For a description of the display interface sink function blocks, see
|
||||
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
|
||||
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt.
|
||||
|
||||
Required properties (all function blocks):
|
||||
- compatible: "mediatek,<chip>-disp-<function>", one of
|
||||
"mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
|
||||
"mediatek,<chip>-disp-rdma" - read DMA / line buffer
|
||||
"mediatek,<chip>-disp-wdma" - write DMA
|
||||
"mediatek,<chip>-disp-color" - color processor
|
||||
"mediatek,<chip>-disp-aal" - adaptive ambient light controller
|
||||
"mediatek,<chip>-disp-gamma" - gamma correction
|
||||
"mediatek,<chip>-disp-merge" - merge streams from two RDMA sources
|
||||
"mediatek,<chip>-disp-split" - split stream to two encoders
|
||||
"mediatek,<chip>-disp-ufoe" - data compression engine
|
||||
"mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt
|
||||
"mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
|
||||
"mediatek,<chip>-disp-mutex" - display mutex
|
||||
"mediatek,<chip>-disp-od" - overdrive
|
||||
- reg: Physical base address and length of the function block register space
|
||||
- interrupts: The interrupt signal from the function block (required, except for
|
||||
merge and split function blocks).
|
||||
- clocks: device clocks
|
||||
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
|
||||
For most function blocks this is just a single clock input. Only the DSI and
|
||||
DPI controller nodes have multiple clock inputs. These are documented in
|
||||
mediatek,dsi.txt and mediatek,dpi.txt, respectively.
|
||||
|
||||
Required properties (DMA function blocks):
|
||||
- compatible: Should be one of
|
||||
"mediatek,<chip>-disp-ovl"
|
||||
"mediatek,<chip>-disp-rdma"
|
||||
"mediatek,<chip>-disp-wdma"
|
||||
- larb: Should contain a phandle pointing to the local arbiter device as defined
|
||||
in Documentation/devicetree/bindings/soc/mediatek/mediatek,smi-larb.txt
|
||||
- iommus: Should point to the respective IOMMU block with master port as
|
||||
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
|
||||
for details.
|
||||
|
||||
Examples:
|
||||
|
||||
mmsys: clock-controller@14000000 {
|
||||
compatible = "mediatek,mt8173-mmsys", "syscon";
|
||||
reg = <0 0x14000000 0 0x1000>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
ovl0: ovl@1400c000 {
|
||||
compatible = "mediatek,mt8173-disp-ovl";
|
||||
reg = <0 0x1400c000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OVL0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_OVL0>;
|
||||
mediatek,larb = <&larb0>;
|
||||
};
|
||||
|
||||
ovl1: ovl@1400d000 {
|
||||
compatible = "mediatek,mt8173-disp-ovl";
|
||||
reg = <0 0x1400d000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OVL1>;
|
||||
iommus = <&iommu M4U_PORT_DISP_OVL1>;
|
||||
mediatek,larb = <&larb4>;
|
||||
};
|
||||
|
||||
rdma0: rdma@1400e000 {
|
||||
compatible = "mediatek,mt8173-disp-rdma";
|
||||
reg = <0 0x1400e000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
|
||||
mediatek,larb = <&larb0>;
|
||||
};
|
||||
|
||||
rdma1: rdma@1400f000 {
|
||||
compatible = "mediatek,mt8173-disp-rdma";
|
||||
reg = <0 0x1400f000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
|
||||
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
|
||||
mediatek,larb = <&larb4>;
|
||||
};
|
||||
|
||||
rdma2: rdma@14010000 {
|
||||
compatible = "mediatek,mt8173-disp-rdma";
|
||||
reg = <0 0x14010000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_RDMA2>;
|
||||
iommus = <&iommu M4U_PORT_DISP_RDMA2>;
|
||||
mediatek,larb = <&larb4>;
|
||||
};
|
||||
|
||||
wdma0: wdma@14011000 {
|
||||
compatible = "mediatek,mt8173-disp-wdma";
|
||||
reg = <0 0x14011000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_WDMA0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_WDMA0>;
|
||||
mediatek,larb = <&larb0>;
|
||||
};
|
||||
|
||||
wdma1: wdma@14012000 {
|
||||
compatible = "mediatek,mt8173-disp-wdma";
|
||||
reg = <0 0x14012000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_WDMA1>;
|
||||
iommus = <&iommu M4U_PORT_DISP_WDMA1>;
|
||||
mediatek,larb = <&larb4>;
|
||||
};
|
||||
|
||||
color0: color@14013000 {
|
||||
compatible = "mediatek,mt8173-disp-color";
|
||||
reg = <0 0x14013000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
|
||||
};
|
||||
|
||||
color1: color@14014000 {
|
||||
compatible = "mediatek,mt8173-disp-color";
|
||||
reg = <0 0x14014000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_COLOR1>;
|
||||
};
|
||||
|
||||
aal@14015000 {
|
||||
compatible = "mediatek,mt8173-disp-aal";
|
||||
reg = <0 0x14015000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_AAL>;
|
||||
};
|
||||
|
||||
gamma@14016000 {
|
||||
compatible = "mediatek,mt8173-disp-gamma";
|
||||
reg = <0 0x14016000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_GAMMA>;
|
||||
};
|
||||
|
||||
ufoe@1401a000 {
|
||||
compatible = "mediatek,mt8173-disp-ufoe";
|
||||
reg = <0 0x1401a000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_UFOE>;
|
||||
};
|
||||
|
||||
dsi0: dsi@1401b000 {
|
||||
/* See mediatek,dsi.txt for details */
|
||||
};
|
||||
|
||||
dpi0: dpi@1401d000 {
|
||||
/* See mediatek,dpi.txt for details */
|
||||
};
|
||||
|
||||
mutex: mutex@14020000 {
|
||||
compatible = "mediatek,mt8173-disp-mutex";
|
||||
reg = <0 0x14020000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_MUTEX_32K>;
|
||||
};
|
||||
|
||||
od@14023000 {
|
||||
compatible = "mediatek,mt8173-disp-od";
|
||||
reg = <0 0x14023000 0 0x1000>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OD>;
|
||||
};
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
Mediatek DPI Device
|
||||
===================
|
||||
|
||||
The Mediatek DPI function block is a sink of the display subsystem and
|
||||
provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
|
||||
output bus.
|
||||
|
||||
Required properties:
|
||||
- compatible: "mediatek,<chip>-dpi"
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- interrupts: The interrupt signal from the function block.
|
||||
- clocks: device clocks
|
||||
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
|
||||
- clock-names: must contain "pixel", "engine", and "pll"
|
||||
- port: Output port node with endpoint definitions as described in
|
||||
Documentation/devicetree/bindings/graph.txt. This port should be connected
|
||||
to the input port of an attached HDMI or LVDS encoder chip.
|
||||
|
||||
Example:
|
||||
|
||||
dpi0: dpi@1401d000 {
|
||||
compatible = "mediatek,mt8173-dpi";
|
||||
reg = <0 0x1401d000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&mmsys CLK_MM_DPI_PIXEL>,
|
||||
<&mmsys CLK_MM_DPI_ENGINE>,
|
||||
<&apmixedsys CLK_APMIXED_TVDPLL>;
|
||||
clock-names = "pixel", "engine", "pll";
|
||||
|
||||
port {
|
||||
dpi0_out: endpoint {
|
||||
remote-endpoint = <&hdmi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
Mediatek DSI Device
|
||||
===================
|
||||
|
||||
The Mediatek DSI function block is a sink of the display subsystem and can
|
||||
drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
|
||||
channel output.
|
||||
|
||||
Required properties:
|
||||
- compatible: "mediatek,<chip>-dsi"
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- interrupts: The interrupt signal from the function block.
|
||||
- clocks: device clocks
|
||||
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
|
||||
- clock-names: must contain "engine", "digital", and "hs"
|
||||
- phys: phandle link to the MIPI D-PHY controller.
|
||||
- phy-names: must contain "dphy"
|
||||
- port: Output port node with endpoint definitions as described in
|
||||
Documentation/devicetree/bindings/graph.txt. This port should be connected
|
||||
to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
|
||||
|
||||
MIPI TX Configuration Module
|
||||
============================
|
||||
|
||||
The MIPI TX configuration module controls the MIPI D-PHY.
|
||||
|
||||
Required properties:
|
||||
- compatible: "mediatek,<chip>-mipi-tx"
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- clocks: PLL reference clock
|
||||
- clock-output-names: name of the output clock line to the DSI encoder
|
||||
- #clock-cells: must be <0>;
|
||||
- #phy-cells: must be <0>.
|
||||
|
||||
Example:
|
||||
|
||||
mipi_tx0: mipi-dphy@10215000 {
|
||||
compatible = "mediatek,mt8173-mipi-tx";
|
||||
reg = <0 0x10215000 0 0x1000>;
|
||||
clocks = <&clk26m>;
|
||||
clock-output-names = "mipi_tx0_pll";
|
||||
#clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
dsi0: dsi@1401b000 {
|
||||
compatible = "mediatek,mt8173-dsi";
|
||||
reg = <0 0x1401b000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
|
||||
<&mipi_tx0>;
|
||||
clock-names = "engine", "digital", "hs";
|
||||
phys = <&mipi_tx0>;
|
||||
phy-names = "dphy";
|
||||
|
||||
port {
|
||||
dsi0_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
Innolux AT070TN92 7.0" WQVGA TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "innolux,at070tn92"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
Olimex 4.3" TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "olimex,lcd-olinuxino-43-ts"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
On Tat Industrial Company 7" DPI TFT panel.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "ontat,yx700wv03"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
TPK U.S.A. LLC Fusion 7" integrated projected capacitive touch display with,
|
||||
800 x 480 (WVGA) LCD panel.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "tpk,f07a-0102"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
TPK U.S.A. LLC Fusion 10.1" integrated projected capacitive touch display with,
|
||||
1024 x 600 (WSVGA) LCD panel.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "tpk,f10a-0102"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
Rockchip RK3288 specific extensions to the Analogix Display Port
|
||||
================================
|
||||
|
||||
Required properties:
|
||||
- compatible: "rockchip,rk3288-edp";
|
||||
|
||||
- reg: physical base address of the controller and length
|
||||
|
||||
- clocks: from common clock binding: handle to dp clock.
|
||||
of memory mapped region.
|
||||
|
||||
- clock-names: from common clock binding:
|
||||
Required elements: "dp" "pclk"
|
||||
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
|
||||
- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
|
||||
- pinctrl-0: pin-control mode. should be <&edp_hpd>
|
||||
|
||||
- reset-names: Must include the name "dp"
|
||||
|
||||
- rockchip,grf: this soc should set GRF regs, so need get grf here.
|
||||
|
||||
- ports: there are 2 port nodes with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt.
|
||||
Port 0: contained 2 endpoints, connecting to the output of vop.
|
||||
Port 1: contained 1 endpoint, connecting to the input of panel.
|
||||
|
||||
For the below properties, please refer to Analogix DP binding document:
|
||||
* Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
|
||||
- phys (required)
|
||||
- phy-names (required)
|
||||
- hpd-gpios (optional)
|
||||
- force-hpd (optional)
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Example:
|
||||
dp-controller: dp@ff970000 {
|
||||
compatible = "rockchip,rk3288-dp";
|
||||
reg = <0xff970000 0x4000>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
|
||||
clock-names = "dp", "pclk";
|
||||
phys = <&dp_phy>;
|
||||
phy-names = "dp";
|
||||
|
||||
rockchip,grf = <&grf>;
|
||||
resets = <&cru 111>;
|
||||
reset-names = "dp";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&edp_hpd>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
edp_in: port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
edp_in_vopb: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&vopb_out_edp>;
|
||||
};
|
||||
edp_in_vopl: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&vopl_out_edp>;
|
||||
};
|
||||
};
|
||||
|
||||
edp_out: port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
edp_out_panel: endpoint {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&panel_in_edp>
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl {
|
||||
edp {
|
||||
edp_hpd: edp-hpd {
|
||||
rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
35
Documentation/devicetree/bindings/display/snps,arcpgu.txt
Normal file
35
Documentation/devicetree/bindings/display/snps,arcpgu.txt
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
ARC PGU
|
||||
|
||||
This is a display controller found on several development boards produced
|
||||
by Synopsys. The ARC PGU is an RGB streamer that reads the data from a
|
||||
framebuffer and sends it to a single digital encoder (usually HDMI).
|
||||
|
||||
Required properties:
|
||||
- compatible: "snps,arcpgu"
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- clocks: A list of phandle + clock-specifier pairs, one for each
|
||||
entry in 'clock-names'.
|
||||
- clock-names: A list of clock names. For ARC PGU it should contain:
|
||||
- "pxlclk" for the clock feeding the output PLL of the controller.
|
||||
|
||||
Required sub-nodes:
|
||||
- port: The PGU connection to an encoder chip.
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
pgu@XXXXXXXX {
|
||||
compatible = "snps,arcpgu";
|
||||
reg = <0xXXXXXXXX 0x400>;
|
||||
clocks = <&clock_node>;
|
||||
clock-names = "pxlclk";
|
||||
|
||||
port {
|
||||
pgu_output: endpoint {
|
||||
remote-endpoint = <&hdmi_enc_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
258
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
Normal file
258
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
Normal file
|
|
@ -0,0 +1,258 @@
|
|||
Allwinner A10 Display Pipeline
|
||||
==============================
|
||||
|
||||
The Allwinner A10 Display pipeline is composed of several components
|
||||
that are going to be documented below:
|
||||
|
||||
TV Encoder
|
||||
----------
|
||||
|
||||
The TV Encoder supports the composite and VGA output. It is one end of
|
||||
the pipeline.
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be "allwinner,sun4i-a10-tv-encoder".
|
||||
- reg: base address and size of memory-mapped region
|
||||
- clocks: the clocks driving the TV encoder
|
||||
- resets: phandle to the reset controller driving the encoder
|
||||
|
||||
- ports: A ports node with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt. The
|
||||
first port should be the input endpoint.
|
||||
|
||||
TCON
|
||||
----
|
||||
|
||||
The TCON acts as a timing controller for RGB, LVDS and TV interfaces.
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be "allwinner,sun5i-a13-tcon".
|
||||
- reg: base address and size of memory-mapped region
|
||||
- interrupts: interrupt associated to this IP
|
||||
- clocks: phandles to the clocks feeding the TCON. Three are needed:
|
||||
- 'ahb': the interface clocks
|
||||
- 'tcon-ch0': The clock driving the TCON channel 0
|
||||
- 'tcon-ch1': The clock driving the TCON channel 1
|
||||
- resets: phandles to the reset controllers driving the encoder
|
||||
- "lcd": the reset line for the TCON channel 0
|
||||
|
||||
- clock-names: the clock names mentioned above
|
||||
- reset-names: the reset names mentioned above
|
||||
- clock-output-names: Name of the pixel clock created
|
||||
|
||||
- ports: A ports node with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt. The
|
||||
first port should be the input endpoint, the second one the output
|
||||
|
||||
The output should have two endpoints. The first is the block
|
||||
connected to the TCON channel 0 (usually a panel or a bridge), the
|
||||
second the block connected to the TCON channel 1 (usually the TV
|
||||
encoder)
|
||||
|
||||
|
||||
Display Engine Backend
|
||||
----------------------
|
||||
|
||||
The display engine backend exposes layers and sprites to the
|
||||
system.
|
||||
|
||||
Required properties:
|
||||
- compatible: value must be one of:
|
||||
* allwinner,sun5i-a13-display-backend
|
||||
- reg: base address and size of the memory-mapped region.
|
||||
- clocks: phandles to the clocks feeding the frontend and backend
|
||||
* ahb: the backend interface clock
|
||||
* mod: the backend module clock
|
||||
* ram: the backend DRAM clock
|
||||
- clock-names: the clock names mentioned above
|
||||
- resets: phandles to the reset controllers driving the backend
|
||||
|
||||
- ports: A ports node with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt. The
|
||||
first port should be the input endpoints, the second one the output
|
||||
|
||||
Display Engine Frontend
|
||||
-----------------------
|
||||
|
||||
The display engine frontend does formats conversion, scaling,
|
||||
deinterlacing and color space conversion.
|
||||
|
||||
Required properties:
|
||||
- compatible: value must be one of:
|
||||
* allwinner,sun5i-a13-display-frontend
|
||||
- reg: base address and size of the memory-mapped region.
|
||||
- interrupts: interrupt associated to this IP
|
||||
- clocks: phandles to the clocks feeding the frontend and backend
|
||||
* ahb: the backend interface clock
|
||||
* mod: the backend module clock
|
||||
* ram: the backend DRAM clock
|
||||
- clock-names: the clock names mentioned above
|
||||
- resets: phandles to the reset controllers driving the backend
|
||||
|
||||
- ports: A ports node with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt. The
|
||||
first port should be the input endpoints, the second one the outputs
|
||||
|
||||
|
||||
Display Engine Pipeline
|
||||
-----------------------
|
||||
|
||||
The display engine pipeline (and its entry point, since it can be
|
||||
either directly the backend or the frontend) is represented as an
|
||||
extra node.
|
||||
|
||||
Required properties:
|
||||
- compatible: value must be one of:
|
||||
* allwinner,sun5i-a13-display-engine
|
||||
|
||||
- allwinner,pipelines: list of phandle to the display engine
|
||||
frontends available.
|
||||
|
||||
Example:
|
||||
|
||||
panel: panel {
|
||||
compatible = "olimex,lcd-olinuxino-43-ts";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
panel_input: endpoint {
|
||||
remote-endpoint = <&tcon0_out_panel>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tve0: tv-encoder@01c0a000 {
|
||||
compatible = "allwinner,sun4i-a10-tv-encoder";
|
||||
reg = <0x01c0a000 0x1000>;
|
||||
clocks = <&ahb_gates 34>;
|
||||
resets = <&tcon_ch0_clk 0>;
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tve0_in_tcon0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&tcon0_out_tve0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tcon0: lcd-controller@1c0c000 {
|
||||
compatible = "allwinner,sun5i-a13-tcon";
|
||||
reg = <0x01c0c000 0x1000>;
|
||||
interrupts = <44>;
|
||||
resets = <&tcon_ch0_clk 1>;
|
||||
reset-names = "lcd";
|
||||
clocks = <&ahb_gates 36>,
|
||||
<&tcon_ch0_clk>,
|
||||
<&tcon_ch1_clk>;
|
||||
clock-names = "ahb",
|
||||
"tcon-ch0",
|
||||
"tcon-ch1";
|
||||
clock-output-names = "tcon-pixel-clock";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon0_in: port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
tcon0_in_be0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&be0_out_tcon0>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon0_out: port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
tcon0_out_panel: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&panel_input>;
|
||||
};
|
||||
|
||||
tcon0_out_tve0: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&tve0_in_tcon0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fe0: display-frontend@1e00000 {
|
||||
compatible = "allwinner,sun5i-a13-display-frontend";
|
||||
reg = <0x01e00000 0x20000>;
|
||||
interrupts = <47>;
|
||||
clocks = <&ahb_gates 46>, <&de_fe_clk>,
|
||||
<&dram_gates 25>;
|
||||
clock-names = "ahb", "mod",
|
||||
"ram";
|
||||
resets = <&de_fe_clk>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
fe0_out: port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
fe0_out_be0: endpoint {
|
||||
remote-endpoint = <&be0_in_fe0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
be0: display-backend@1e60000 {
|
||||
compatible = "allwinner,sun5i-a13-display-backend";
|
||||
reg = <0x01e60000 0x10000>;
|
||||
clocks = <&ahb_gates 44>, <&de_be_clk>,
|
||||
<&dram_gates 26>;
|
||||
clock-names = "ahb", "mod",
|
||||
"ram";
|
||||
resets = <&de_be_clk>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
be0_in: port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
be0_in_fe0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&fe0_out_be0>;
|
||||
};
|
||||
};
|
||||
|
||||
be0_out: port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
be0_out_tcon0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&tcon0_in_be0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
display-engine {
|
||||
compatible = "allwinner,sun5i-a13-display-engine";
|
||||
allwinner,pipelines = <&fe0>;
|
||||
};
|
||||
|
|
@ -6,8 +6,8 @@ RK3xxx SoCs.
|
|||
Required properties :
|
||||
|
||||
- reg : Offset and length of the register set for the device
|
||||
- compatible : should be "rockchip,rk3066-i2c", "rockchip,rk3188-i2c" or
|
||||
"rockchip,rk3288-i2c".
|
||||
- compatible : should be "rockchip,rk3066-i2c", "rockchip,rk3188-i2c",
|
||||
"rockchip,rk3228-i2c" or "rockchip,rk3288-i2c".
|
||||
- interrupts : interrupt number
|
||||
- clocks : parent clock
|
||||
|
||||
|
|
|
|||
|
|
@ -45,13 +45,13 @@ Required properties:
|
|||
Optional properties:
|
||||
- dual_emac_res_vlan : Specifies VID to be used to segregate the ports
|
||||
- mac-address : See ethernet.txt file in the same directory
|
||||
- phy_id : Specifies slave phy id
|
||||
- phy_id : Specifies slave phy id (deprecated, use phy-handle)
|
||||
- phy-handle : See ethernet.txt file in the same directory
|
||||
|
||||
Slave sub-nodes:
|
||||
- fixed-link : See fixed-link.txt file in the same directory
|
||||
Either the property phy_id, or the sub-node
|
||||
fixed-link can be specified
|
||||
|
||||
Note: Exactly one of phy_id, phy-handle, or fixed-link must be specified.
|
||||
|
||||
Note: "ti,hwmods" field is used to fetch the base address and irq
|
||||
resources from TI, omap hwmod data base during device registration.
|
||||
|
|
|
|||
|
|
@ -9,7 +9,8 @@ have dual GMAC each represented by a child node..
|
|||
Required properties:
|
||||
- compatible: Should be "mediatek,mt7623-eth"
|
||||
- reg: Address and length of the register set for the device
|
||||
- interrupts: Should contain the frame engines interrupt
|
||||
- interrupts: Should contain the three frame engines interrupts in numeric
|
||||
order. These are fe_int0, fe_int1 and fe_int2.
|
||||
- clocks: the clock used by the core
|
||||
- clock-names: the names of the clock listed in the clocks property. These are
|
||||
"ethif", "esw", "gp2", "gp1"
|
||||
|
|
@ -42,7 +43,9 @@ eth: ethernet@1b100000 {
|
|||
<ðsys CLK_ETHSYS_GP2>,
|
||||
<ðsys CLK_ETHSYS_GP1>;
|
||||
clock-names = "ethif", "esw", "gp2", "gp1";
|
||||
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
|
||||
GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
|
||||
GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
|
||||
resets = <ðsys MT2701_ETHSYS_ETH_RST>;
|
||||
reset-names = "eth";
|
||||
|
|
|
|||
|
|
@ -8,15 +8,19 @@ Required properties:
|
|||
of memory mapped region.
|
||||
- clock-names: from common clock binding:
|
||||
Required elements: "24m"
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
- #phy-cells : from the generic PHY bindings, must be 0;
|
||||
|
||||
Example:
|
||||
|
||||
edp_phy: edp-phy {
|
||||
compatible = "rockchip,rk3288-dp-phy";
|
||||
rockchip,grf = <&grf>;
|
||||
clocks = <&cru SCLK_EDP_24M>;
|
||||
clock-names = "24m";
|
||||
#phy-cells = <0>;
|
||||
grf: syscon@ff770000 {
|
||||
compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
|
||||
|
||||
...
|
||||
|
||||
edp_phy: edp-phy {
|
||||
compatible = "rockchip,rk3288-dp-phy";
|
||||
clocks = <&cru SCLK_EDP_24M>;
|
||||
clock-names = "24m";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -3,17 +3,23 @@ Rockchip EMMC PHY
|
|||
|
||||
Required properties:
|
||||
- compatible: rockchip,rk3399-emmc-phy
|
||||
- rockchip,grf : phandle to the syscon managing the "general
|
||||
register files"
|
||||
- #phy-cells: must be 0
|
||||
- reg: PHY configure reg address offset in "general
|
||||
- reg: PHY register address offset and length in "general
|
||||
register files"
|
||||
|
||||
Example:
|
||||
|
||||
emmcphy: phy {
|
||||
compatible = "rockchip,rk3399-emmc-phy";
|
||||
rockchip,grf = <&grf>;
|
||||
reg = <0xf780>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
grf: syscon@ff770000 {
|
||||
compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
...
|
||||
|
||||
emmcphy: phy@f780 {
|
||||
compatible = "rockchip,rk3399-emmc-phy";
|
||||
reg = <0xf780 0x20>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,13 +1,16 @@
|
|||
== Amlogic Meson pinmux controller ==
|
||||
|
||||
Required properties for the root node:
|
||||
- compatible: "amlogic,meson8-pinctrl" or "amlogic,meson8b-pinctrl"
|
||||
- compatible: one of "amlogic,meson8-cbus-pinctrl"
|
||||
"amlogic,meson8b-cbus-pinctrl"
|
||||
"amlogic,meson8-aobus-pinctrl"
|
||||
"amlogic,meson8b-aobus-pinctrl"
|
||||
- reg: address and size of registers controlling irq functionality
|
||||
|
||||
=== GPIO sub-nodes ===
|
||||
|
||||
The 2 power domains of the controller (regular and always-on) are
|
||||
represented as sub-nodes and each of them acts as a GPIO controller.
|
||||
The GPIO bank for the controller is represented as a sub-node and it acts as a
|
||||
GPIO controller.
|
||||
|
||||
Required properties for sub-nodes are:
|
||||
- reg: should contain address and size for mux, pull-enable, pull and
|
||||
|
|
@ -18,10 +21,6 @@ Required properties for sub-nodes are:
|
|||
- gpio-controller: identifies the node as a gpio controller
|
||||
- #gpio-cells: must be 2
|
||||
|
||||
Valid sub-node names are:
|
||||
- "banks" for the regular domain
|
||||
- "ao-bank" for the always-on domain
|
||||
|
||||
=== Other sub-nodes ===
|
||||
|
||||
Child nodes without the "gpio-controller" represent some desired
|
||||
|
|
@ -45,7 +44,7 @@ pinctrl-bindings.txt
|
|||
=== Example ===
|
||||
|
||||
pinctrl: pinctrl@c1109880 {
|
||||
compatible = "amlogic,meson8-pinctrl";
|
||||
compatible = "amlogic,meson8-cbus-pinctrl";
|
||||
reg = <0xc1109880 0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -61,15 +60,6 @@ pinctrl-bindings.txt
|
|||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio_ao: ao-bank@c1108030 {
|
||||
reg = <0xc8100014 0x4>,
|
||||
<0xc810002c 0x4>,
|
||||
<0xc8100024 0x8>;
|
||||
reg-names = "mux", "pull", "gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
nand {
|
||||
mux {
|
||||
groups = "nand_io", "nand_io_ce0", "nand_io_ce1",
|
||||
|
|
@ -79,18 +69,4 @@ pinctrl-bindings.txt
|
|||
function = "nand";
|
||||
};
|
||||
};
|
||||
|
||||
uart_ao_a {
|
||||
mux {
|
||||
groups = "uart_tx_ao_a", "uart_rx_ao_a",
|
||||
"uart_cts_ao_a", "uart_rts_ao_a";
|
||||
function = "uart_ao";
|
||||
};
|
||||
|
||||
conf {
|
||||
pins = "GPIOAO_0", "GPIOAO_1",
|
||||
"GPIOAO_2", "GPIOAO_3";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -15,9 +15,10 @@ Required properties:
|
|||
is the rtc tick interrupt. The number of cells representing a interrupt
|
||||
depends on the parent interrupt controller.
|
||||
- clocks: Must contain a list of phandle and clock specifier for the rtc
|
||||
and source clocks.
|
||||
- clock-names: Must contain "rtc" and "rtc_src" entries sorted in the
|
||||
same order as the clocks property.
|
||||
clock and in the case of a s3c6410 compatible controller, also
|
||||
a source clock.
|
||||
- clock-names: Must contain "rtc" and for a s3c6410 compatible controller,
|
||||
a "rtc_src" sorted in the same order as the clocks property.
|
||||
|
||||
Example:
|
||||
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@ amlogic Amlogic, Inc.
|
|||
ampire Ampire Co., Ltd.
|
||||
ams AMS AG
|
||||
amstaos AMS-Taos Inc.
|
||||
analogix Analogix Semiconductor, Inc.
|
||||
apm Applied Micro Circuits Corporation (APM)
|
||||
aptina Aptina Imaging
|
||||
arasan Arasan Chip Systems
|
||||
|
|
@ -172,6 +173,7 @@ nxp NXP Semiconductors
|
|||
okaya Okaya Electric America, Inc.
|
||||
olimex OLIMEX Ltd.
|
||||
onnn ON Semiconductor Corp.
|
||||
ontat On Tat Industrial Company
|
||||
opencores OpenCores.org
|
||||
option Option NV
|
||||
ortustech Ortus Technology Co., Ltd.
|
||||
|
|
@ -247,6 +249,7 @@ toradex Toradex AG
|
|||
toshiba Toshiba Corporation
|
||||
toumaz Toumaz
|
||||
tplink TP-LINK Technologies Co., Ltd.
|
||||
tpk TPK U.S.A. LLC
|
||||
tronfy Tronfy
|
||||
tronsmart Tronsmart
|
||||
truly Truly Semiconductors Limited
|
||||
|
|
|
|||
40
Documentation/devicetree/bindings/video/bridge/anx7814.txt
Normal file
40
Documentation/devicetree/bindings/video/bridge/anx7814.txt
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
Analogix ANX7814 SlimPort (Full-HD Transmitter)
|
||||
-----------------------------------------------
|
||||
|
||||
The ANX7814 is an ultra-low power Full-HD (1080p60) SlimPort transmitter
|
||||
designed for portable devices.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : "analogix,anx7814"
|
||||
- reg : I2C address of the device
|
||||
- interrupt-parent : Should be the phandle of the interrupt controller
|
||||
that services interrupts for this device
|
||||
- interrupts : Should contain the INTP interrupt
|
||||
- hpd-gpios : Which GPIO to use for hpd
|
||||
- pd-gpios : Which GPIO to use for power down
|
||||
- reset-gpios : Which GPIO to use for reset
|
||||
|
||||
Optional properties:
|
||||
|
||||
- dvdd10-supply : Regulator for 1.0V digital core power.
|
||||
- Video port for HDMI input, using the DT bindings defined in [1].
|
||||
|
||||
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
Example:
|
||||
|
||||
anx7814: anx7814@38 {
|
||||
compatible = "analogix,anx7814";
|
||||
reg = <0x38>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <99 IRQ_TYPE_LEVEL_LOW>; /* INTP */
|
||||
hpd-gpios = <&pio 36 GPIO_ACTIVE_HIGH>;
|
||||
pd-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&pio 98 GPIO_ACTIVE_HIGH>;
|
||||
port {
|
||||
anx7814_in: endpoint {
|
||||
remote-endpoint = <&hdmi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -173,6 +173,10 @@ A few EV_ABS codes have special meanings:
|
|||
proximity of the device and while the value of the BTN_TOUCH code is 0. If
|
||||
the input device may be used freely in three dimensions, consider ABS_Z
|
||||
instead.
|
||||
- BTN_TOOL_<name> should be set to 1 when the tool comes into detectable
|
||||
proximity and set to 0 when the tool leaves detectable proximity.
|
||||
BTN_TOOL_<name> signals the type of tool that is currently detected by the
|
||||
hardware and is otherwise independent of ABS_DISTANCE and/or BTN_TOUCH.
|
||||
|
||||
* ABS_MT_<name>:
|
||||
- Used to describe multitouch input events. Please see
|
||||
|
|
|
|||
|
|
@ -4077,6 +4077,8 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
|
|||
sector if the number is odd);
|
||||
i = IGNORE_DEVICE (don't bind to this
|
||||
device);
|
||||
j = NO_REPORT_LUNS (don't use report luns
|
||||
command, uas only);
|
||||
l = NOT_LOCKABLE (don't try to lock and
|
||||
unlock ejectable media);
|
||||
m = MAX_SECTORS_64 (don't transfer more
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ This is the driver for the Altera Triple-Speed Ethernet (TSE) controllers
|
|||
using the SGDMA and MSGDMA soft DMA IP components. The driver uses the
|
||||
platform bus to obtain component resources. The designs used to test this
|
||||
driver were built for a Cyclone(R) V SOC FPGA board, a Cyclone(R) V FPGA board,
|
||||
and tested with ARM and NIOS processor hosts seperately. The anticipated use
|
||||
and tested with ARM and NIOS processor hosts separately. The anticipated use
|
||||
cases are simple communications between an embedded system and an external peer
|
||||
for status and simple configuration of the embedded system.
|
||||
|
||||
|
|
@ -65,14 +65,14 @@ Driver parameters can be also passed in command line by using:
|
|||
4.1) Transmit process
|
||||
When the driver's transmit routine is called by the kernel, it sets up a
|
||||
transmit descriptor by calling the underlying DMA transmit routine (SGDMA or
|
||||
MSGDMA), and initites a transmit operation. Once the transmit is complete, an
|
||||
MSGDMA), and initiates a transmit operation. Once the transmit is complete, an
|
||||
interrupt is driven by the transmit DMA logic. The driver handles the transmit
|
||||
completion in the context of the interrupt handling chain by recycling
|
||||
resource required to send and track the requested transmit operation.
|
||||
|
||||
4.2) Receive process
|
||||
The driver will post receive buffers to the receive DMA logic during driver
|
||||
intialization. Receive buffers may or may not be queued depending upon the
|
||||
initialization. Receive buffers may or may not be queued depending upon the
|
||||
underlying DMA logic (MSGDMA is able queue receive buffers, SGDMA is not able
|
||||
to queue receive buffers to the SGDMA receive logic). When a packet is
|
||||
received, the DMA logic generates an interrupt. The driver handles a receive
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ Initial Release:
|
|||
This is conceptually very similar to the macvlan driver with one major
|
||||
exception of using L3 for mux-ing /demux-ing among slaves. This property makes
|
||||
the master device share the L2 with it's slave devices. I have developed this
|
||||
driver in conjuntion with network namespaces and not sure if there is use case
|
||||
driver in conjunction with network namespaces and not sure if there is use case
|
||||
outside of it.
|
||||
|
||||
|
||||
|
|
@ -42,7 +42,7 @@ out. In this mode the slaves will RX/TX multicast and broadcast (if applicable)
|
|||
as well.
|
||||
|
||||
4.2 L3 mode:
|
||||
In this mode TX processing upto L3 happens on the stack instance attached
|
||||
In this mode TX processing up to L3 happens on the stack instance attached
|
||||
to the slave device and packets are switched to the stack instance of the
|
||||
master device for the L2 processing and routing from that instance will be
|
||||
used before packets are queued on the outbound device. In this mode the slaves
|
||||
|
|
@ -56,7 +56,7 @@ situations defines your use case then you can choose to use ipvlan -
|
|||
(a) The Linux host that is connected to the external switch / router has
|
||||
policy configured that allows only one mac per port.
|
||||
(b) No of virtual devices created on a master exceed the mac capacity and
|
||||
puts the NIC in promiscous mode and degraded performance is a concern.
|
||||
puts the NIC in promiscuous mode and degraded performance is a concern.
|
||||
(c) If the slave device is to be put into the hostile / untrusted network
|
||||
namespace where L2 on the slave could be changed / misused.
|
||||
|
||||
|
|
|
|||
|
|
@ -67,12 +67,12 @@ The two basic thread commands are:
|
|||
* add_device DEVICE@NAME -- adds a single device
|
||||
* rem_device_all -- remove all associated devices
|
||||
|
||||
When adding a device to a thread, a corrosponding procfile is created
|
||||
When adding a device to a thread, a corresponding procfile is created
|
||||
which is used for configuring this device. Thus, device names need to
|
||||
be unique.
|
||||
|
||||
To support adding the same device to multiple threads, which is useful
|
||||
with multi queue NICs, a the device naming scheme is extended with "@":
|
||||
with multi queue NICs, the device naming scheme is extended with "@":
|
||||
device@something
|
||||
|
||||
The part after "@" can be anything, but it is custom to use the thread
|
||||
|
|
@ -221,7 +221,7 @@ Sample scripts
|
|||
|
||||
A collection of tutorial scripts and helpers for pktgen is in the
|
||||
samples/pktgen directory. The helper parameters.sh file support easy
|
||||
and consistant parameter parsing across the sample scripts.
|
||||
and consistent parameter parsing across the sample scripts.
|
||||
|
||||
Usage example and help:
|
||||
./pktgen_sample01_simple.sh -i eth4 -m 00:1B:21:3C:9D:F8 -d 192.168.8.2
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ using an rx_handler which gives the impression that packets flow through
|
|||
the VRF device. Similarly on egress routing rules are used to send packets
|
||||
to the VRF device driver before getting sent out the actual interface. This
|
||||
allows tcpdump on a VRF device to capture all packets into and out of the
|
||||
VRF as a whole.[1] Similiarly, netfilter [2] and tc rules can be applied
|
||||
VRF as a whole.[1] Similarly, netfilter [2] and tc rules can be applied
|
||||
using the VRF device to specify rules that apply to the VRF domain as a whole.
|
||||
|
||||
[1] Packets in the forwarded state do not flow through the device, so those
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ Krisztian <hidden@balabit.hu> and others and additional patches
|
|||
from Jamal <hadi@cyberus.ca>.
|
||||
|
||||
The end goal for syncing is to be able to insert attributes + generate
|
||||
events so that the an SA can be safely moved from one machine to another
|
||||
events so that the SA can be safely moved from one machine to another
|
||||
for HA purposes.
|
||||
The idea is to synchronize the SA so that the takeover machine can do
|
||||
the processing of the SA as accurate as possible if it has access to it.
|
||||
|
|
@ -13,7 +13,7 @@ We already have the ability to generate SA add/del/upd events.
|
|||
These patches add ability to sync and have accurate lifetime byte (to
|
||||
ensure proper decay of SAs) and replay counters to avoid replay attacks
|
||||
with as minimal loss at failover time.
|
||||
This way a backup stays as closely uptodate as an active member.
|
||||
This way a backup stays as closely up-to-date as an active member.
|
||||
|
||||
Because the above items change for every packet the SA receives,
|
||||
it is possible for a lot of the events to be generated.
|
||||
|
|
@ -163,7 +163,7 @@ If you have an SA that is getting hit by traffic in bursts such that
|
|||
there is a period where the timer threshold expires with no packets
|
||||
seen, then an odd behavior is seen as follows:
|
||||
The first packet arrival after a timer expiry will trigger a timeout
|
||||
aevent; i.e we dont wait for a timeout period or a packet threshold
|
||||
event; i.e we don't wait for a timeout period or a packet threshold
|
||||
to be reached. This is done for simplicity and efficiency reasons.
|
||||
|
||||
-JHS
|
||||
|
|
|
|||
|
|
@ -581,15 +581,16 @@ Specify "[Nn]ode" for node order
|
|||
"Zone Order" orders the zonelists by zone type, then by node within each
|
||||
zone. Specify "[Zz]one" for zone order.
|
||||
|
||||
Specify "[Dd]efault" to request automatic configuration. Autoconfiguration
|
||||
will select "node" order in following case.
|
||||
(1) if the DMA zone does not exist or
|
||||
(2) if the DMA zone comprises greater than 50% of the available memory or
|
||||
(3) if any node's DMA zone comprises greater than 70% of its local memory and
|
||||
the amount of local memory is big enough.
|
||||
Specify "[Dd]efault" to request automatic configuration.
|
||||
|
||||
Otherwise, "zone" order will be selected. Default order is recommended unless
|
||||
this is causing problems for your system/application.
|
||||
On 32-bit, the Normal zone needs to be preserved for allocations accessible
|
||||
by the kernel, so "zone" order will be selected.
|
||||
|
||||
On 64-bit, devices that require DMA32/DMA are relatively rare, so "node"
|
||||
order will be selected.
|
||||
|
||||
Default order is recommended unless this is causing problems for your
|
||||
system/application.
|
||||
|
||||
==============================================================
|
||||
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ For the gadget two work under Windows two conditions have to be met:
|
|||
First of all, Windows need to detect the gadget as an USB composite
|
||||
gadget which on its own have some conditions[4]. If they are met,
|
||||
Windows lets USB Generic Parent Driver[5] handle the device which then
|
||||
tries to much drivers for each individual interface (sort of, don't
|
||||
tries to match drivers for each individual interface (sort of, don't
|
||||
get into too many details).
|
||||
|
||||
The good news is: you do not have to worry about most of the
|
||||
|
|
|
|||
27
Documentation/x86/protection-keys.txt
Normal file
27
Documentation/x86/protection-keys.txt
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
Memory Protection Keys for Userspace (PKU aka PKEYs) is a CPU feature
|
||||
which will be found on future Intel CPUs.
|
||||
|
||||
Memory Protection Keys provides a mechanism for enforcing page-based
|
||||
protections, but without requiring modification of the page tables
|
||||
when an application changes protection domains. It works by
|
||||
dedicating 4 previously ignored bits in each page table entry to a
|
||||
"protection key", giving 16 possible keys.
|
||||
|
||||
There is also a new user-accessible register (PKRU) with two separate
|
||||
bits (Access Disable and Write Disable) for each key. Being a CPU
|
||||
register, PKRU is inherently thread-local, potentially giving each
|
||||
thread a different set of protections from every other thread.
|
||||
|
||||
There are two new instructions (RDPKRU/WRPKRU) for reading and writing
|
||||
to the new register. The feature is only available in 64-bit mode,
|
||||
even though there is theoretically space in the PAE PTEs. These
|
||||
permissions are enforced on data access only and have no effect on
|
||||
instruction fetches.
|
||||
|
||||
=========================== Config Option ===========================
|
||||
|
||||
This config option adds approximately 1.5kb of text. and 50 bytes of
|
||||
data to the executable. A workload which does large O_DIRECT reads
|
||||
of holes in XFS files was run to exercise get_user_pages_fast(). No
|
||||
performance delta was observed with the config option
|
||||
enabled or disabled.
|
||||
|
|
@ -19,7 +19,7 @@ ffffff0000000000 - ffffff7fffffffff (=39 bits) %esp fixup stacks
|
|||
ffffffef00000000 - ffffffff00000000 (=64 GB) EFI region mapping space
|
||||
... unused hole ...
|
||||
ffffffff80000000 - ffffffffa0000000 (=512 MB) kernel text mapping, from phys 0
|
||||
ffffffffa0000000 - ffffffffff5fffff (=1525 MB) module mapping space
|
||||
ffffffffa0000000 - ffffffffff5fffff (=1526 MB) module mapping space
|
||||
ffffffffff600000 - ffffffffffdfffff (=8 MB) vsyscalls
|
||||
ffffffffffe00000 - ffffffffffffffff (=2 MB) unused hole
|
||||
|
||||
|
|
@ -31,8 +31,8 @@ vmalloc space is lazily synchronized into the different PML4 pages of
|
|||
the processes using the page fault handler, with init_level4_pgt as
|
||||
reference.
|
||||
|
||||
Current X86-64 implementations only support 40 bits of address space,
|
||||
but we support up to 46 bits. This expands into MBZ space in the page tables.
|
||||
Current X86-64 implementations support up to 46 bits of address space (64 TB),
|
||||
which is our current limit. This expands into MBZ space in the page tables.
|
||||
|
||||
We map EFI runtime services in the 'efi_pgd' PGD in a 64Gb large virtual
|
||||
memory window (this size is arbitrary, it can be raised later if needed).
|
||||
|
|
|
|||
228
MAINTAINERS
228
MAINTAINERS
|
|
@ -847,6 +847,12 @@ S: Maintained
|
|||
F: drivers/net/arcnet/
|
||||
F: include/uapi/linux/if_arcnet.h
|
||||
|
||||
ARC PGU DRM DRIVER
|
||||
M: Alexey Brodkin <abrodkin@synopsys.com>
|
||||
S: Supported
|
||||
F: drivers/gpu/drm/arc/
|
||||
F: Documentation/devicetree/bindings/display/snps,arcpgu.txt
|
||||
|
||||
ARM HDLCD DRM DRIVER
|
||||
M: Liviu Dudau <liviu.dudau@arm.com>
|
||||
S: Supported
|
||||
|
|
@ -872,9 +878,9 @@ F: drivers/perf/arm_pmu.c
|
|||
F: include/linux/perf/arm_pmu.h
|
||||
|
||||
ARM PORT
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.arm.linux.org.uk/
|
||||
W: http://www.armlinux.org.uk/
|
||||
S: Maintained
|
||||
F: arch/arm/
|
||||
|
||||
|
|
@ -886,35 +892,35 @@ F: arch/arm/plat-*/
|
|||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
|
||||
|
||||
ARM PRIMECELL AACI PL041 DRIVER
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
S: Maintained
|
||||
F: sound/arm/aaci.*
|
||||
|
||||
ARM PRIMECELL CLCD PL110 DRIVER
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
S: Maintained
|
||||
F: drivers/video/fbdev/amba-clcd.*
|
||||
|
||||
ARM PRIMECELL KMI PL050 DRIVER
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
S: Maintained
|
||||
F: drivers/input/serio/ambakmi.*
|
||||
F: include/linux/amba/kmi.h
|
||||
|
||||
ARM PRIMECELL MMCI PL180/1 DRIVER
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
S: Maintained
|
||||
F: drivers/mmc/host/mmci.*
|
||||
F: include/linux/amba/mmci.h
|
||||
|
||||
ARM PRIMECELL UART PL010 AND PL011 DRIVERS
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
S: Maintained
|
||||
F: drivers/tty/serial/amba-pl01*.c
|
||||
F: include/linux/amba/serial.h
|
||||
|
||||
ARM PRIMECELL BUS SUPPORT
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
S: Maintained
|
||||
F: drivers/amba/
|
||||
F: include/linux/amba/bus.h
|
||||
|
|
@ -1036,7 +1042,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
|||
S: Maintained
|
||||
|
||||
ARM/CLKDEV SUPPORT
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/include/asm/clkdev.h
|
||||
|
|
@ -1093,9 +1099,9 @@ F: arch/arm/boot/dts/cx92755*
|
|||
N: digicolor
|
||||
|
||||
ARM/EBSA110 MACHINE SUPPORT
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.arm.linux.org.uk/
|
||||
W: http://www.armlinux.org.uk/
|
||||
S: Maintained
|
||||
F: arch/arm/mach-ebsa110/
|
||||
F: drivers/net/ethernet/amd/am79c961a.*
|
||||
|
|
@ -1124,9 +1130,9 @@ T: git git://git.berlios.de/gemini-board
|
|||
F: arch/arm/mm/*-fa*
|
||||
|
||||
ARM/FOOTBRIDGE ARCHITECTURE
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.arm.linux.org.uk/
|
||||
W: http://www.armlinux.org.uk/
|
||||
S: Maintained
|
||||
F: arch/arm/include/asm/hardware/dec21285.h
|
||||
F: arch/arm/mach-footbridge/
|
||||
|
|
@ -1457,7 +1463,7 @@ S: Maintained
|
|||
ARM/PT DIGITAL BOARD PORT
|
||||
M: Stefan Eletzhofer <stefan.eletzhofer@eletztrick.de>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.arm.linux.org.uk/
|
||||
W: http://www.armlinux.org.uk/
|
||||
S: Maintained
|
||||
|
||||
ARM/QUALCOMM SUPPORT
|
||||
|
|
@ -1493,9 +1499,9 @@ S: Supported
|
|||
F: arch/arm64/boot/dts/renesas/
|
||||
|
||||
ARM/RISCPC ARCHITECTURE
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.arm.linux.org.uk/
|
||||
W: http://www.armlinux.org.uk/
|
||||
S: Maintained
|
||||
F: arch/arm/include/asm/hardware/entry-macro-iomd.S
|
||||
F: arch/arm/include/asm/hardware/ioc.h
|
||||
|
|
@ -1773,9 +1779,9 @@ F: drivers/clk/versatile/clk-vexpress-osc.c
|
|||
F: drivers/clocksource/versatile.c
|
||||
|
||||
ARM/VFP SUPPORT
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.arm.linux.org.uk/
|
||||
W: http://www.armlinux.org.uk/
|
||||
S: Maintained
|
||||
F: arch/arm/vfp/
|
||||
|
||||
|
|
@ -2921,7 +2927,7 @@ F: mm/cleancache.c
|
|||
F: include/linux/cleancache.h
|
||||
|
||||
CLK API
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
L: linux-clk@vger.kernel.org
|
||||
S: Maintained
|
||||
F: include/linux/clk.h
|
||||
|
|
@ -3354,9 +3360,9 @@ S: Supported
|
|||
F: drivers/net/ethernet/stmicro/stmmac/
|
||||
|
||||
CYBERPRO FB DRIVER
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.arm.linux.org.uk/
|
||||
W: http://www.armlinux.org.uk/
|
||||
S: Maintained
|
||||
F: drivers/video/fbdev/cyber2000fb.*
|
||||
|
||||
|
|
@ -3759,9 +3765,25 @@ T: git git://people.freedesktop.org/~airlied/linux
|
|||
S: Maintained
|
||||
F: drivers/gpu/drm/
|
||||
F: drivers/gpu/vga/
|
||||
F: Documentation/DocBook/gpu.*
|
||||
F: include/drm/
|
||||
F: include/uapi/drm/
|
||||
|
||||
DRM DRIVER FOR AST SERVER GRAPHICS CHIPS
|
||||
M: Dave Airlie <airlied@redhat.com>
|
||||
S: Odd Fixes
|
||||
F: drivers/gpu/drm/ast/
|
||||
|
||||
DRM DRIVER FOR BOCHS VIRTUAL GPU
|
||||
M: Gerd Hoffmann <kraxel@redhat.com>
|
||||
S: Odd Fixes
|
||||
F: drivers/gpu/drm/bochs/
|
||||
|
||||
DRM DRIVER FOR QEMU'S CIRRUS DEVICE
|
||||
M: Dave Airlie <airlied@redhat.com>
|
||||
S: Odd Fixes
|
||||
F: drivers/gpu/drm/cirrus/
|
||||
|
||||
RADEON and AMDGPU DRM DRIVERS
|
||||
M: Alex Deucher <alexander.deucher@amd.com>
|
||||
M: Christian König <christian.koenig@amd.com>
|
||||
|
|
@ -3769,9 +3791,9 @@ L: dri-devel@lists.freedesktop.org
|
|||
T: git git://people.freedesktop.org/~agd5f/linux
|
||||
S: Supported
|
||||
F: drivers/gpu/drm/radeon/
|
||||
F: include/uapi/drm/radeon*
|
||||
F: include/uapi/drm/radeon_drm.h
|
||||
F: drivers/gpu/drm/amd/
|
||||
F: include/uapi/drm/amdgpu*
|
||||
F: include/uapi/drm/amdgpu_drm.h
|
||||
|
||||
DRM PANEL DRIVERS
|
||||
M: Thierry Reding <thierry.reding@gmail.com>
|
||||
|
|
@ -3794,7 +3816,7 @@ T: git git://anongit.freedesktop.org/drm-intel
|
|||
S: Supported
|
||||
F: drivers/gpu/drm/i915/
|
||||
F: include/drm/i915*
|
||||
F: include/uapi/drm/i915*
|
||||
F: include/uapi/drm/i915_drm.h
|
||||
|
||||
DRM DRIVERS FOR ATMEL HLCDC
|
||||
M: Boris Brezillon <boris.brezillon@free-electrons.com>
|
||||
|
|
@ -3803,6 +3825,13 @@ S: Supported
|
|||
F: drivers/gpu/drm/atmel-hlcdc/
|
||||
F: Documentation/devicetree/bindings/drm/atmel/
|
||||
|
||||
DRM DRIVERS FOR ALLWINNER A10
|
||||
M: Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
S: Supported
|
||||
F: drivers/gpu/drm/sun4i/
|
||||
F: Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
|
||||
|
||||
DRM DRIVERS FOR EXYNOS
|
||||
M: Inki Dae <inki.dae@samsung.com>
|
||||
M: Joonyoung Shim <jy0922.shim@samsung.com>
|
||||
|
|
@ -3812,8 +3841,8 @@ L: dri-devel@lists.freedesktop.org
|
|||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git
|
||||
S: Supported
|
||||
F: drivers/gpu/drm/exynos/
|
||||
F: include/drm/exynos*
|
||||
F: include/uapi/drm/exynos*
|
||||
F: include/uapi/drm/exynos_drm.h
|
||||
F: Documentation/devicetree/bindings/display/exynos/
|
||||
|
||||
DRM DRIVERS FOR FREESCALE DCU
|
||||
M: Stefan Agner <stefan@agner.ch>
|
||||
|
|
@ -3822,6 +3851,7 @@ L: dri-devel@lists.freedesktop.org
|
|||
S: Supported
|
||||
F: drivers/gpu/drm/fsl-dcu/
|
||||
F: Documentation/devicetree/bindings/display/fsl,dcu.txt
|
||||
F: Documentation/devicetree/bindings/display/fsl,tcon.txt
|
||||
F: Documentation/devicetree/bindings/display/panel/nec,nl4827hc19_05b.txt
|
||||
|
||||
DRM DRIVERS FOR FREESCALE IMX
|
||||
|
|
@ -3837,12 +3867,45 @@ M: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
|
|||
L: dri-devel@lists.freedesktop.org
|
||||
T: git git://github.com/patjak/drm-gma500
|
||||
S: Maintained
|
||||
F: drivers/gpu/drm/gma500
|
||||
F: include/drm/gma500*
|
||||
F: drivers/gpu/drm/gma500/
|
||||
|
||||
DRM DRIVERS FOR HISILICON
|
||||
M: Xinliang Liu <z.liuxinliang@hisilicon.com>
|
||||
R: Xinwei Kong <kong.kongxinwei@hisilicon.com>
|
||||
R: Chen Feng <puck.chen@hisilicon.com>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
T: git git://github.com/xin3liang/linux.git
|
||||
S: Maintained
|
||||
F: drivers/gpu/drm/hisilicon/
|
||||
F: Documentation/devicetree/bindings/display/hisilicon/
|
||||
|
||||
DRM DRIVER FOR INTEL I810 VIDEO CARDS
|
||||
S: Orphan / Obsolete
|
||||
F: drivers/gpu/drm/i810/
|
||||
F: include/uapi/drm/i810_drm.h
|
||||
|
||||
DRM DRIVER FOR MSM ADRENO GPU
|
||||
M: Rob Clark <robdclark@gmail.com>
|
||||
L: linux-arm-msm@vger.kernel.org
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
L: freedreno@lists.freedesktop.org
|
||||
T: git git://people.freedesktop.org/~robclark/linux
|
||||
S: Maintained
|
||||
F: drivers/gpu/drm/msm/
|
||||
F: include/uapi/drm/msm_drm.h
|
||||
F: Documentation/devicetree/bindings/display/msm/
|
||||
|
||||
DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS
|
||||
M: Ben Skeggs <bskeggs@redhat.com>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
L: nouveau@lists.freedesktop.org
|
||||
T: git git://github.com/skeggsb/linux
|
||||
S: Supported
|
||||
F: drivers/gpu/drm/nouveau/
|
||||
F: include/uapi/drm/nouveau_drm.h
|
||||
|
||||
DRM DRIVERS FOR NVIDIA TEGRA
|
||||
M: Thierry Reding <thierry.reding@gmail.com>
|
||||
M: Terje Bergström <tbergstrom@nvidia.com>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
L: linux-tegra@vger.kernel.org
|
||||
T: git git://anongit.freedesktop.org/tegra/linux.git
|
||||
|
|
@ -3853,22 +3916,54 @@ F: include/linux/host1x.h
|
|||
F: include/uapi/drm/tegra_drm.h
|
||||
F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
|
||||
|
||||
DRM DRIVER FOR MATROX G200/G400 GRAPHICS CARDS
|
||||
S: Orphan / Obsolete
|
||||
F: drivers/gpu/drm/mga/
|
||||
F: include/uapi/drm/mga_drm.h
|
||||
|
||||
DRM DRIVER FOR MGA G200 SERVER GRAPHICS CHIPS
|
||||
M: Dave Airlie <airlied@redhat.com>
|
||||
S: Odd Fixes
|
||||
F: drivers/gpu/drm/mgag200/
|
||||
|
||||
DRM DRIVER FOR RAGE 128 VIDEO CARDS
|
||||
S: Orphan / Obsolete
|
||||
F: drivers/gpu/drm/r128/
|
||||
F: include/uapi/drm/r128_drm.h
|
||||
|
||||
DRM DRIVERS FOR RENESAS
|
||||
M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
L: linux-renesas-soc@vger.kernel.org
|
||||
T: git git://people.freedesktop.org/~airlied/linux
|
||||
T: git git://linuxtv.org/pinchartl/fbdev
|
||||
S: Supported
|
||||
F: drivers/gpu/drm/rcar-du/
|
||||
F: drivers/gpu/drm/shmobile/
|
||||
F: include/linux/platform_data/shmob_drm.h
|
||||
F: Documentation/devicetree/bindings/display/renesas,du.txt
|
||||
|
||||
DRM DRIVER FOR QXL VIRTUAL GPU
|
||||
M: Dave Airlie <airlied@redhat.com>
|
||||
S: Odd Fixes
|
||||
F: drivers/gpu/drm/qxl/
|
||||
F: include/uapi/drm/qxl_drm.h
|
||||
|
||||
DRM DRIVERS FOR ROCKCHIP
|
||||
M: Mark Yao <mark.yao@rock-chips.com>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
S: Maintained
|
||||
F: drivers/gpu/drm/rockchip/
|
||||
F: Documentation/devicetree/bindings/display/rockchip*
|
||||
F: Documentation/devicetree/bindings/display/rockchip/
|
||||
|
||||
DRM DRIVER FOR SAVAGE VIDEO CARDS
|
||||
S: Orphan / Obsolete
|
||||
F: drivers/gpu/drm/savage/
|
||||
F: include/uapi/drm/savage_drm.h
|
||||
|
||||
DRM DRIVER FOR SIS VIDEO CARDS
|
||||
S: Orphan / Obsolete
|
||||
F: drivers/gpu/drm/sis/
|
||||
F: include/uapi/drm/sis_drm.h
|
||||
|
||||
DRM DRIVERS FOR STI
|
||||
M: Benjamin Gaignard <benjamin.gaignard@linaro.org>
|
||||
|
|
@ -3879,14 +3974,43 @@ S: Maintained
|
|||
F: drivers/gpu/drm/sti
|
||||
F: Documentation/devicetree/bindings/display/st,stih4xx.txt
|
||||
|
||||
DRM DRIVER FOR TDFX VIDEO CARDS
|
||||
S: Orphan / Obsolete
|
||||
F: drivers/gpu/drm/tdfx/
|
||||
|
||||
DRM DRIVER FOR USB DISPLAYLINK VIDEO ADAPTERS
|
||||
M: Dave Airlie <airlied@redhat.com>
|
||||
S: Odd Fixes
|
||||
F: drivers/gpu/drm/udl/
|
||||
|
||||
DRM DRIVERS FOR VIVANTE GPU IP
|
||||
M: Lucas Stach <l.stach@pengutronix.de>
|
||||
R: Russell King <linux+etnaviv@arm.linux.org.uk>
|
||||
R: Russell King <linux+etnaviv@armlinux.org.uk>
|
||||
R: Christian Gmeiner <christian.gmeiner@gmail.com>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
S: Maintained
|
||||
F: drivers/gpu/drm/etnaviv
|
||||
F: Documentation/devicetree/bindings/display/etnaviv
|
||||
F: drivers/gpu/drm/etnaviv/
|
||||
F: include/uapi/drm/etnaviv_drm.h
|
||||
F: Documentation/devicetree/bindings/display/etnaviv/
|
||||
|
||||
DRM DRIVER FOR VMWARE VIRTUAL GPU
|
||||
M: "VMware Graphics" <linux-graphics-maintainer@vmware.com>
|
||||
M: Sinclair Yeh <syeh@vmware.com>
|
||||
M: Thomas Hellstrom <thellstrom@vmware.com>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
T: git git://people.freedesktop.org/~syeh/repos_linux
|
||||
T: git git://people.freedesktop.org/~thomash/linux
|
||||
S: Supported
|
||||
F: drivers/gpu/drm/vmwgfx/
|
||||
F: include/uapi/drm/vmwgfx_drm.h
|
||||
|
||||
DRM DRIVERS FOR VC4
|
||||
M: Eric Anholt <eric@anholt.net>
|
||||
T: git git://github.com/anholt/linux
|
||||
S: Supported
|
||||
F: drivers/gpu/drm/vc4/
|
||||
F: include/uapi/drm/vc4_drm.h
|
||||
F: Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt
|
||||
|
||||
DSBR100 USB FM RADIO DRIVER
|
||||
M: Alexey Klimov <klimov.linux@gmail.com>
|
||||
|
|
@ -4223,8 +4347,8 @@ F: Documentation/efi-stub.txt
|
|||
F: arch/ia64/kernel/efi.c
|
||||
F: arch/x86/boot/compressed/eboot.[ch]
|
||||
F: arch/x86/include/asm/efi.h
|
||||
F: arch/x86/platform/efi/*
|
||||
F: drivers/firmware/efi/*
|
||||
F: arch/x86/platform/efi/
|
||||
F: drivers/firmware/efi/
|
||||
F: include/linux/efi*.h
|
||||
|
||||
EFI VARIABLE FILESYSTEM
|
||||
|
|
@ -4744,7 +4868,7 @@ F: drivers/platform/x86/fujitsu-tablet.c
|
|||
|
||||
FUSE: FILESYSTEM IN USERSPACE
|
||||
M: Miklos Szeredi <miklos@szeredi.hu>
|
||||
L: fuse-devel@lists.sourceforge.net
|
||||
L: linux-fsdevel@vger.kernel.org
|
||||
W: http://fuse.sourceforge.net/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi/fuse.git
|
||||
S: Maintained
|
||||
|
|
@ -4903,7 +5027,7 @@ F: net/ipv4/gre_offload.c
|
|||
F: include/net/gre.h
|
||||
|
||||
GRETH 10/100/1G Ethernet MAC device driver
|
||||
M: Kristoffer Glembo <kristoffer@gaisler.com>
|
||||
M: Andreas Larsson <andreas@gaisler.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/net/ethernet/aeroflex/
|
||||
|
|
@ -6027,7 +6151,7 @@ F: include/scsi/*iscsi*
|
|||
|
||||
ISCSI EXTENSIONS FOR RDMA (ISER) INITIATOR
|
||||
M: Or Gerlitz <ogerlitz@mellanox.com>
|
||||
M: Sagi Grimberg <sagig@mellanox.com>
|
||||
M: Sagi Grimberg <sagi@grimberg.me>
|
||||
M: Roi Dayan <roid@mellanox.com>
|
||||
L: linux-rdma@vger.kernel.org
|
||||
S: Supported
|
||||
|
|
@ -6037,7 +6161,7 @@ Q: http://patchwork.kernel.org/project/linux-rdma/list/
|
|||
F: drivers/infiniband/ulp/iser/
|
||||
|
||||
ISCSI EXTENSIONS FOR RDMA (ISER) TARGET
|
||||
M: Sagi Grimberg <sagig@mellanox.com>
|
||||
M: Sagi Grimberg <sagi@grimberg.me>
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/nab/target-pending.git master
|
||||
L: linux-rdma@vger.kernel.org
|
||||
L: target-devel@vger.kernel.org
|
||||
|
|
@ -6252,8 +6376,8 @@ S: Maintained
|
|||
F: tools/testing/selftests
|
||||
|
||||
KERNEL VIRTUAL MACHINE (KVM)
|
||||
M: Gleb Natapov <gleb@kernel.org>
|
||||
M: Paolo Bonzini <pbonzini@redhat.com>
|
||||
M: Radim Krčmář <rkrcmar@redhat.com>
|
||||
L: kvm@vger.kernel.org
|
||||
W: http://www.linux-kvm.org
|
||||
T: git git://git.kernel.org/pub/scm/virt/kvm/kvm.git
|
||||
|
|
@ -6400,7 +6524,7 @@ F: mm/kmemleak.c
|
|||
F: mm/kmemleak-test.c
|
||||
|
||||
KPROBES
|
||||
M: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
|
||||
M: Ananth N Mavinakayanahalli <ananth@linux.vnet.ibm.com>
|
||||
M: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
|
||||
M: "David S. Miller" <davem@davemloft.net>
|
||||
M: Masami Hiramatsu <mhiramat@kernel.org>
|
||||
|
|
@ -6905,9 +7029,11 @@ L: linux-man@vger.kernel.org
|
|||
S: Maintained
|
||||
|
||||
MARVELL ARMADA DRM SUPPORT
|
||||
M: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
M: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
S: Maintained
|
||||
F: drivers/gpu/drm/armada/
|
||||
F: include/uapi/drm/armada_drm.h
|
||||
F: Documentation/devicetree/bindings/display/armada/
|
||||
|
||||
MARVELL 88E6352 DSA support
|
||||
M: Guenter Roeck <linux@roeck-us.net>
|
||||
|
|
@ -7905,7 +8031,7 @@ S: Supported
|
|||
F: drivers/nfc/nxp-nci
|
||||
|
||||
NXP TDA998X DRM DRIVER
|
||||
M: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
M: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
S: Supported
|
||||
F: drivers/gpu/drm/i2c/tda998x_drv.c
|
||||
F: include/drm/i2c/tda998x.h
|
||||
|
|
@ -7978,7 +8104,7 @@ F: arch/arm/*omap*/*pm*
|
|||
F: drivers/cpufreq/omap-cpufreq.c
|
||||
|
||||
OMAP POWERDOMAIN SOC ADAPTATION LAYER SUPPORT
|
||||
M: Rajendra Nayak <rnayak@ti.com>
|
||||
M: Rajendra Nayak <rnayak@codeaurora.org>
|
||||
M: Paul Walmsley <paul@pwsan.com>
|
||||
L: linux-omap@vger.kernel.org
|
||||
S: Maintained
|
||||
|
|
@ -10014,7 +10140,8 @@ F: drivers/infiniband/hw/ocrdma/
|
|||
|
||||
SFC NETWORK DRIVER
|
||||
M: Solarflare linux maintainers <linux-net-drivers@solarflare.com>
|
||||
M: Shradha Shah <sshah@solarflare.com>
|
||||
M: Edward Cree <ecree@solarflare.com>
|
||||
M: Bert Kenward <bkenward@solarflare.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
F: drivers/net/ethernet/sfc/
|
||||
|
|
@ -11071,6 +11198,15 @@ S: Maintained
|
|||
F: drivers/clk/ti/
|
||||
F: include/linux/clk/ti.h
|
||||
|
||||
TI ETHERNET SWITCH DRIVER (CPSW)
|
||||
M: Mugunthan V N <mugunthanvnm@ti.com>
|
||||
R: Grygorii Strashko <grygorii.strashko@ti.com>
|
||||
L: linux-omap@vger.kernel.org
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/net/ethernet/ti/cpsw*
|
||||
F: drivers/net/ethernet/ti/davinci*
|
||||
|
||||
TI FLASH MEDIA INTERFACE DRIVER
|
||||
M: Alex Dubov <oakad@yahoo.com>
|
||||
S: Maintained
|
||||
|
|
|
|||
7
Makefile
7
Makefile
|
|
@ -1,8 +1,8 @@
|
|||
VERSION = 4
|
||||
PATCHLEVEL = 6
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc3
|
||||
NAME = Blurry Fish Butt
|
||||
EXTRAVERSION = -rc7
|
||||
NAME = Charred Weasel
|
||||
|
||||
# *DOCUMENTATION*
|
||||
# To see a list of typical targets execute "make help"
|
||||
|
|
@ -1008,7 +1008,8 @@ prepare0: archprepare FORCE
|
|||
prepare: prepare0 prepare-objtool
|
||||
|
||||
ifdef CONFIG_STACK_VALIDATION
|
||||
has_libelf := $(shell echo "int main() {}" | $(HOSTCC) -xc -o /dev/null -lelf - &> /dev/null && echo 1 || echo 0)
|
||||
has_libelf := $(call try-run,\
|
||||
echo "int main() {}" | $(HOSTCC) -xc -o /dev/null -lelf -,1,0)
|
||||
ifeq ($(has_libelf),1)
|
||||
objtool_target := tools/objtool FORCE
|
||||
else
|
||||
|
|
|
|||
|
|
@ -35,8 +35,10 @@ config ARC
|
|||
select NO_BOOTMEM
|
||||
select OF
|
||||
select OF_EARLY_FLATTREE
|
||||
select OF_RESERVED_MEM
|
||||
select PERF_USE_VMALLOC
|
||||
select HAVE_DEBUG_STACKOVERFLOW
|
||||
select HAVE_GENERIC_DMA_COHERENT
|
||||
|
||||
config MIGHT_HAVE_PCI
|
||||
bool
|
||||
|
|
@ -56,6 +58,9 @@ config GENERIC_CSUM
|
|||
config RWSEM_GENERIC_SPINLOCK
|
||||
def_bool y
|
||||
|
||||
config ARCH_DISCONTIGMEM_ENABLE
|
||||
def_bool y
|
||||
|
||||
config ARCH_FLATMEM_ENABLE
|
||||
def_bool y
|
||||
|
||||
|
|
@ -345,6 +350,15 @@ config ARC_HUGEPAGE_16M
|
|||
|
||||
endchoice
|
||||
|
||||
config NODES_SHIFT
|
||||
int "Maximum NUMA Nodes (as a power of 2)"
|
||||
default "1" if !DISCONTIGMEM
|
||||
default "2" if DISCONTIGMEM
|
||||
depends on NEED_MULTIPLE_NODES
|
||||
---help---
|
||||
Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
|
||||
zones.
|
||||
|
||||
if ISA_ARCOMPACT
|
||||
|
||||
config ARC_COMPACT_IRQ_LEVELS
|
||||
|
|
@ -453,6 +467,7 @@ config LINUX_LINK_BASE
|
|||
|
||||
config HIGHMEM
|
||||
bool "High Memory Support"
|
||||
select DISCONTIGMEM
|
||||
help
|
||||
With ARC 2G:2G address split, only upper 2G is directly addressable by
|
||||
kernel. Enable this to potentially allow access to rest of 2G and PAE
|
||||
|
|
@ -593,7 +608,6 @@ config PCI_SYSCALL
|
|||
def_bool PCI
|
||||
|
||||
source "drivers/pci/Kconfig"
|
||||
source "drivers/pci/pcie/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
||||
|
|
|
|||
|
|
@ -93,8 +93,26 @@
|
|||
memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0x80000000 0x40000000>;
|
||||
ranges = <0x00000000 0x80000000 0x20000000>;
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x20000000>; /* 512MiB */
|
||||
reg = <0x80000000 0x1b000000>; /* (512 - 32) MiB */
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
/*
|
||||
* We just move frame buffer area to the very end of
|
||||
* available DDR. And even though in case of ARC770 there's
|
||||
* no strict requirement for a frame-buffer to be in any
|
||||
* particular location it allows us to use the same
|
||||
* base board's DT node for ARC PGU as for ARc HS38.
|
||||
*/
|
||||
frame_buffer: frame_buffer@9e000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x9e000000 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -100,4 +100,18 @@
|
|||
device_type = "memory";
|
||||
reg = <0x80000000 0x20000000>; /* 512MiB */
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
/*
|
||||
* Move frame buffer out of IOC aperture (0x8z-0xAz).
|
||||
*/
|
||||
frame_buffer: frame_buffer@be000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0xbe000000 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -123,4 +123,18 @@
|
|||
device_type = "memory";
|
||||
reg = <0x80000000 0x20000000>; /* 512MiB */
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
/*
|
||||
* Move frame buffer out of IOC aperture (0x8z-0xAz).
|
||||
*/
|
||||
frame_buffer: frame_buffer@be000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0xbe000000 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -34,6 +34,12 @@
|
|||
clock-frequency = <50000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
pguclk: pguclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <74440000>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@0x18000 {
|
||||
|
|
@ -47,14 +53,6 @@
|
|||
clocks = <&apbclk>;
|
||||
clock-names = "stmmaceth";
|
||||
max-speed = <100>;
|
||||
mdio0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ehci@0x40000 {
|
||||
|
|
@ -155,6 +153,37 @@
|
|||
clocks = <&i2cclk>;
|
||||
interrupts = <16>;
|
||||
|
||||
adv7511:adv7511@39{
|
||||
compatible="adi,adv7511";
|
||||
reg = <0x39>;
|
||||
interrupts = <23>;
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,clock-delay = <0x03>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* RGB/YUV input */
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_input:endpoint {
|
||||
remote-endpoint = <&pgu_output>;
|
||||
};
|
||||
};
|
||||
|
||||
/* HDMI output */
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_output: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
eeprom@0x54{
|
||||
compatible = "24c01";
|
||||
reg = <0x54>;
|
||||
|
|
@ -168,6 +197,16 @@
|
|||
};
|
||||
};
|
||||
|
||||
hdmi0: connector {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
port {
|
||||
hdmi_connector_in: endpoint {
|
||||
remote-endpoint = <&adv7511_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio0:gpio@13000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x13000 0x1000>;
|
||||
|
|
@ -229,5 +268,19 @@
|
|||
reg = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pgu@17000 {
|
||||
compatible = "snps,arcpgu";
|
||||
reg = <0x17000 0x400>;
|
||||
encoder-slave = <&adv7511>;
|
||||
clocks = <&pguclk>;
|
||||
clock-names = "pxlclk";
|
||||
memory-region = <&frame_buffer>;
|
||||
port {
|
||||
pgu_output: endpoint {
|
||||
remote-endpoint = <&adv7511_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -42,6 +42,7 @@ CONFIG_DEVTMPFS=y
|
|||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
# CONFIG_FIRMWARE_IN_KERNEL is not set
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -43,6 +43,7 @@ CONFIG_DEVTMPFS=y
|
|||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
# CONFIG_FIRMWARE_IN_KERNEL is not set
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
19
arch/arc/include/asm/fb.h
Normal file
19
arch/arc/include/asm/fb.h
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
#ifndef _ASM_FB_H_
|
||||
#define _ASM_FB_H_
|
||||
|
||||
#include <linux/fb.h>
|
||||
#include <linux/fs.h>
|
||||
#include <asm/page.h>
|
||||
|
||||
static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
|
||||
unsigned long off)
|
||||
{
|
||||
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
|
||||
}
|
||||
|
||||
static inline int fb_is_primary_device(struct fb_info *info)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* _ASM_FB_H_ */
|
||||
|
|
@ -13,6 +13,15 @@
|
|||
#include <asm/byteorder.h>
|
||||
#include <asm/page.h>
|
||||
|
||||
#ifdef CONFIG_ISA_ARCV2
|
||||
#include <asm/barrier.h>
|
||||
#define __iormb() rmb()
|
||||
#define __iowmb() wmb()
|
||||
#else
|
||||
#define __iormb() do { } while (0)
|
||||
#define __iowmb() do { } while (0)
|
||||
#endif
|
||||
|
||||
extern void __iomem *ioremap(phys_addr_t paddr, unsigned long size);
|
||||
extern void __iomem *ioremap_prot(phys_addr_t paddr, unsigned long size,
|
||||
unsigned long flags);
|
||||
|
|
@ -31,6 +40,15 @@ extern void iounmap(const void __iomem *addr);
|
|||
#define ioremap_wc(phy, sz) ioremap(phy, sz)
|
||||
#define ioremap_wt(phy, sz) ioremap(phy, sz)
|
||||
|
||||
/*
|
||||
* io{read,write}{16,32}be() macros
|
||||
*/
|
||||
#define ioread16be(p) ({ u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
|
||||
#define ioread32be(p) ({ u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
|
||||
|
||||
#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force u16)cpu_to_be16(v), p); })
|
||||
#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force u32)cpu_to_be32(v), p); })
|
||||
|
||||
/* Change struct page to physical address */
|
||||
#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
|
||||
|
||||
|
|
@ -108,15 +126,6 @@ static inline void __raw_writel(u32 w, volatile void __iomem *addr)
|
|||
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ISA_ARCV2
|
||||
#include <asm/barrier.h>
|
||||
#define __iormb() rmb()
|
||||
#define __iowmb() wmb()
|
||||
#else
|
||||
#define __iormb() do { } while (0)
|
||||
#define __iowmb() do { } while (0)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MMIO can also get buffered/optimized in micro-arch, so barriers needed
|
||||
* Based on ARM model for the typical use case
|
||||
|
|
|
|||
|
|
@ -18,6 +18,12 @@
|
|||
#define STATUS_AD_MASK (1<<STATUS_AD_BIT)
|
||||
#define STATUS_IE_MASK (1<<STATUS_IE_BIT)
|
||||
|
||||
/* status32 Bits as encoded/expected by CLRI/SETI */
|
||||
#define CLRI_STATUS_IE_BIT 4
|
||||
|
||||
#define CLRI_STATUS_E_MASK 0xF
|
||||
#define CLRI_STATUS_IE_MASK (1 << CLRI_STATUS_IE_BIT)
|
||||
|
||||
#define AUX_USER_SP 0x00D
|
||||
#define AUX_IRQ_CTRL 0x00E
|
||||
#define AUX_IRQ_ACT 0x043 /* Active Intr across all levels */
|
||||
|
|
@ -100,6 +106,13 @@ static inline long arch_local_save_flags(void)
|
|||
:
|
||||
: "memory");
|
||||
|
||||
/* To be compatible with irq_save()/irq_restore()
|
||||
* encode the irq bits as expected by CLRI/SETI
|
||||
* (this was needed to make CONFIG_TRACE_IRQFLAGS work)
|
||||
*/
|
||||
temp = (1 << 5) |
|
||||
((!!(temp & STATUS_IE_MASK)) << CLRI_STATUS_IE_BIT) |
|
||||
(temp & CLRI_STATUS_E_MASK);
|
||||
return temp;
|
||||
}
|
||||
|
||||
|
|
@ -108,7 +121,7 @@ static inline long arch_local_save_flags(void)
|
|||
*/
|
||||
static inline int arch_irqs_disabled_flags(unsigned long flags)
|
||||
{
|
||||
return !(flags & (STATUS_IE_MASK));
|
||||
return !(flags & CLRI_STATUS_IE_MASK);
|
||||
}
|
||||
|
||||
static inline int arch_irqs_disabled(void)
|
||||
|
|
@ -128,11 +141,32 @@ static inline void arc_softirq_clear(int irq)
|
|||
|
||||
#else
|
||||
|
||||
#ifdef CONFIG_TRACE_IRQFLAGS
|
||||
|
||||
.macro TRACE_ASM_IRQ_DISABLE
|
||||
bl trace_hardirqs_off
|
||||
.endm
|
||||
|
||||
.macro TRACE_ASM_IRQ_ENABLE
|
||||
bl trace_hardirqs_on
|
||||
.endm
|
||||
|
||||
#else
|
||||
|
||||
.macro TRACE_ASM_IRQ_DISABLE
|
||||
.endm
|
||||
|
||||
.macro TRACE_ASM_IRQ_ENABLE
|
||||
.endm
|
||||
|
||||
#endif
|
||||
.macro IRQ_DISABLE scratch
|
||||
clri
|
||||
TRACE_ASM_IRQ_DISABLE
|
||||
.endm
|
||||
|
||||
.macro IRQ_ENABLE scratch
|
||||
TRACE_ASM_IRQ_ENABLE
|
||||
seti
|
||||
.endm
|
||||
|
||||
|
|
|
|||
43
arch/arc/include/asm/mmzone.h
Normal file
43
arch/arc/include/asm/mmzone.h
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARC_MMZONE_H
|
||||
#define _ASM_ARC_MMZONE_H
|
||||
|
||||
#ifdef CONFIG_DISCONTIGMEM
|
||||
|
||||
extern struct pglist_data node_data[];
|
||||
#define NODE_DATA(nid) (&node_data[nid])
|
||||
|
||||
static inline int pfn_to_nid(unsigned long pfn)
|
||||
{
|
||||
int is_end_low = 1;
|
||||
|
||||
if (IS_ENABLED(CONFIG_ARC_HAS_PAE40))
|
||||
is_end_low = pfn <= virt_to_pfn(0xFFFFFFFFUL);
|
||||
|
||||
/*
|
||||
* node 0: lowmem: 0x8000_0000 to 0xFFFF_FFFF
|
||||
* node 1: HIGHMEM w/o PAE40: 0x0 to 0x7FFF_FFFF
|
||||
* HIGHMEM with PAE40: 0x1_0000_0000 to ...
|
||||
*/
|
||||
if (pfn >= ARCH_PFN_OFFSET && is_end_low)
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static inline int pfn_valid(unsigned long pfn)
|
||||
{
|
||||
int nid = pfn_to_nid(pfn);
|
||||
|
||||
return (pfn <= node_end_pfn(nid));
|
||||
}
|
||||
#endif /* CONFIG_DISCONTIGMEM */
|
||||
|
||||
#endif
|
||||
|
|
@ -72,11 +72,20 @@ typedef unsigned long pgprot_t;
|
|||
|
||||
typedef pte_t * pgtable_t;
|
||||
|
||||
/*
|
||||
* Use virt_to_pfn with caution:
|
||||
* If used in pte or paddr related macros, it could cause truncation
|
||||
* in PAE40 builds
|
||||
* As a rule of thumb, only use it in helpers starting with virt_
|
||||
* You have been warned !
|
||||
*/
|
||||
#define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT)
|
||||
|
||||
#define ARCH_PFN_OFFSET virt_to_pfn(CONFIG_LINUX_LINK_BASE)
|
||||
|
||||
#ifdef CONFIG_FLATMEM
|
||||
#define pfn_valid(pfn) (((pfn) - ARCH_PFN_OFFSET) < max_mapnr)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* __pa, __va, virt_to_page (ALERT: deprecated, don't use them)
|
||||
|
|
@ -85,12 +94,10 @@ typedef pte_t * pgtable_t;
|
|||
* virt here means link-address/program-address as embedded in object code.
|
||||
* And for ARC, link-addr = physical address
|
||||
*/
|
||||
#define __pa(vaddr) ((unsigned long)vaddr)
|
||||
#define __pa(vaddr) ((unsigned long)(vaddr))
|
||||
#define __va(paddr) ((void *)((unsigned long)(paddr)))
|
||||
|
||||
#define virt_to_page(kaddr) \
|
||||
(mem_map + virt_to_pfn((kaddr) - CONFIG_LINUX_LINK_BASE))
|
||||
|
||||
#define virt_to_page(kaddr) pfn_to_page(virt_to_pfn(kaddr))
|
||||
#define virt_addr_valid(kaddr) pfn_valid(virt_to_pfn(kaddr))
|
||||
|
||||
/* Default Permissions for stack/heaps pages (Non Executable) */
|
||||
|
|
|
|||
|
|
@ -278,14 +278,13 @@ static inline void pmd_set(pmd_t *pmdp, pte_t *ptep)
|
|||
#define pmd_present(x) (pmd_val(x))
|
||||
#define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0)
|
||||
|
||||
#define pte_page(pte) \
|
||||
(mem_map + virt_to_pfn(pte_val(pte) - CONFIG_LINUX_LINK_BASE))
|
||||
|
||||
#define pte_page(pte) pfn_to_page(pte_pfn(pte))
|
||||
#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
|
||||
#define pte_pfn(pte) virt_to_pfn(pte_val(pte))
|
||||
#define pfn_pte(pfn, prot) (__pte(((pte_t)(pfn) << PAGE_SHIFT) | \
|
||||
pgprot_val(prot)))
|
||||
#define __pte_index(addr) (virt_to_pfn(addr) & (PTRS_PER_PTE - 1))
|
||||
#define pfn_pte(pfn, prot) (__pte(((pte_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
|
||||
|
||||
/* Don't use virt_to_pfn for macros below: could cause truncations for PAE40*/
|
||||
#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
|
||||
#define __pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
|
||||
|
||||
/*
|
||||
* pte_offset gets a @ptr to PMD entry (PGD in our 2-tier paging system)
|
||||
|
|
|
|||
|
|
@ -69,8 +69,11 @@ ENTRY(handle_interrupt)
|
|||
|
||||
clri ; To make status32.IE agree with CPU internal state
|
||||
|
||||
lr r0, [ICAUSE]
|
||||
#ifdef CONFIG_TRACE_IRQFLAGS
|
||||
TRACE_ASM_IRQ_DISABLE
|
||||
#endif
|
||||
|
||||
lr r0, [ICAUSE]
|
||||
mov blink, ret_from_exception
|
||||
|
||||
b.d arch_do_IRQ
|
||||
|
|
@ -169,6 +172,11 @@ END(EV_TLBProtV)
|
|||
|
||||
.Lrestore_regs:
|
||||
|
||||
# Interrpts are actually disabled from this point on, but will get
|
||||
# reenabled after we return from interrupt/exception.
|
||||
# But irq tracer needs to be told now...
|
||||
TRACE_ASM_IRQ_ENABLE
|
||||
|
||||
ld r0, [sp, PT_status32] ; U/K mode at time of entry
|
||||
lr r10, [AUX_IRQ_ACT]
|
||||
|
||||
|
|
|
|||
|
|
@ -341,6 +341,9 @@ END(call_do_page_fault)
|
|||
|
||||
.Lrestore_regs:
|
||||
|
||||
# Interrpts are actually disabled from this point on, but will get
|
||||
# reenabled after we return from interrupt/exception.
|
||||
# But irq tracer needs to be told now...
|
||||
TRACE_ASM_IRQ_ENABLE
|
||||
|
||||
lr r10, [status32]
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#ifdef CONFIG_BLK_DEV_INITRD
|
||||
#include <linux/initrd.h>
|
||||
#endif
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/swap.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/highmem.h>
|
||||
|
|
@ -29,11 +30,16 @@ static const unsigned long low_mem_start = CONFIG_LINUX_LINK_BASE;
|
|||
static unsigned long low_mem_sz;
|
||||
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
static unsigned long min_high_pfn;
|
||||
static unsigned long min_high_pfn, max_high_pfn;
|
||||
static u64 high_mem_start;
|
||||
static u64 high_mem_sz;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DISCONTIGMEM
|
||||
struct pglist_data node_data[MAX_NUMNODES] __read_mostly;
|
||||
EXPORT_SYMBOL(node_data);
|
||||
#endif
|
||||
|
||||
/* User can over-ride above with "mem=nnn[KkMm]" in cmdline */
|
||||
static int __init setup_mem_sz(char *str)
|
||||
{
|
||||
|
|
@ -108,13 +114,11 @@ void __init setup_arch_memory(void)
|
|||
/* Last usable page of low mem */
|
||||
max_low_pfn = max_pfn = PFN_DOWN(low_mem_start + low_mem_sz);
|
||||
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
min_high_pfn = PFN_DOWN(high_mem_start);
|
||||
max_pfn = PFN_DOWN(high_mem_start + high_mem_sz);
|
||||
#ifdef CONFIG_FLATMEM
|
||||
/* pfn_valid() uses this */
|
||||
max_mapnr = max_low_pfn - min_low_pfn;
|
||||
#endif
|
||||
|
||||
max_mapnr = max_pfn - min_low_pfn;
|
||||
|
||||
/*------------- bootmem allocator setup -----------------------*/
|
||||
|
||||
/*
|
||||
|
|
@ -128,7 +132,7 @@ void __init setup_arch_memory(void)
|
|||
* the crash
|
||||
*/
|
||||
|
||||
memblock_add(low_mem_start, low_mem_sz);
|
||||
memblock_add_node(low_mem_start, low_mem_sz, 0);
|
||||
memblock_reserve(low_mem_start, __pa(_end) - low_mem_start);
|
||||
|
||||
#ifdef CONFIG_BLK_DEV_INITRD
|
||||
|
|
@ -136,6 +140,9 @@ void __init setup_arch_memory(void)
|
|||
memblock_reserve(__pa(initrd_start), initrd_end - initrd_start);
|
||||
#endif
|
||||
|
||||
early_init_fdt_reserve_self();
|
||||
early_init_fdt_scan_reserved_mem();
|
||||
|
||||
memblock_dump_all();
|
||||
|
||||
/*----------------- node/zones setup --------------------------*/
|
||||
|
|
@ -145,13 +152,6 @@ void __init setup_arch_memory(void)
|
|||
zones_size[ZONE_NORMAL] = max_low_pfn - min_low_pfn;
|
||||
zones_holes[ZONE_NORMAL] = 0;
|
||||
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
zones_size[ZONE_HIGHMEM] = max_pfn - max_low_pfn;
|
||||
|
||||
/* This handles the peripheral address space hole */
|
||||
zones_holes[ZONE_HIGHMEM] = min_high_pfn - max_low_pfn;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* We can't use the helper free_area_init(zones[]) because it uses
|
||||
* PAGE_OFFSET to compute the @min_low_pfn which would be wrong
|
||||
|
|
@ -164,6 +164,34 @@ void __init setup_arch_memory(void)
|
|||
zones_holes); /* holes */
|
||||
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
/*
|
||||
* Populate a new node with highmem
|
||||
*
|
||||
* On ARC (w/o PAE) HIGHMEM addresses are actually smaller (0 based)
|
||||
* than addresses in normal ala low memory (0x8000_0000 based).
|
||||
* Even with PAE, the huge peripheral space hole would waste a lot of
|
||||
* mem with single mem_map[]. This warrants a mem_map per region design.
|
||||
* Thus HIGHMEM on ARC is imlemented with DISCONTIGMEM.
|
||||
*
|
||||
* DISCONTIGMEM in turns requires multiple nodes. node 0 above is
|
||||
* populated with normal memory zone while node 1 only has highmem
|
||||
*/
|
||||
node_set_online(1);
|
||||
|
||||
min_high_pfn = PFN_DOWN(high_mem_start);
|
||||
max_high_pfn = PFN_DOWN(high_mem_start + high_mem_sz);
|
||||
|
||||
zones_size[ZONE_NORMAL] = 0;
|
||||
zones_holes[ZONE_NORMAL] = 0;
|
||||
|
||||
zones_size[ZONE_HIGHMEM] = max_high_pfn - min_high_pfn;
|
||||
zones_holes[ZONE_HIGHMEM] = 0;
|
||||
|
||||
free_area_init_node(1, /* node-id */
|
||||
zones_size, /* num pages per zone */
|
||||
min_high_pfn, /* first pfn of node */
|
||||
zones_holes); /* holes */
|
||||
|
||||
high_memory = (void *)(min_high_pfn << PAGE_SHIFT);
|
||||
kmap_init();
|
||||
#endif
|
||||
|
|
@ -181,7 +209,7 @@ void __init mem_init(void)
|
|||
unsigned long tmp;
|
||||
|
||||
reset_all_zones_managed_pages();
|
||||
for (tmp = min_high_pfn; tmp < max_pfn; tmp++)
|
||||
for (tmp = min_high_pfn; tmp < max_high_pfn; tmp++)
|
||||
free_highmem_page(pfn_to_page(tmp));
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -470,9 +470,12 @@
|
|||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <0>;
|
||||
phy-mode = "rmii";
|
||||
dual_emac_res_vlan = <1>;
|
||||
fixed-link {
|
||||
speed = <100>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
|
|
|
|||
|
|
@ -860,7 +860,7 @@
|
|||
ti,no-idle-on-init;
|
||||
reg = <0x50000000 0x2000>;
|
||||
interrupts = <100>;
|
||||
dmas = <&edma 52>;
|
||||
dmas = <&edma 52 0>;
|
||||
dma-names = "rxtx";
|
||||
gpmc,num-cs = <7>;
|
||||
gpmc,num-waitpins = <2>;
|
||||
|
|
|
|||
|
|
@ -207,7 +207,7 @@
|
|||
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
|
||||
<&edma_tptc2 0>;
|
||||
|
||||
ti,edma-memcpy-channels = <32 33>;
|
||||
ti,edma-memcpy-channels = <58 59>;
|
||||
};
|
||||
|
||||
edma_tptc0: tptc@49800000 {
|
||||
|
|
@ -884,7 +884,7 @@
|
|||
gpmc: gpmc@50000000 {
|
||||
compatible = "ti,am3352-gpmc";
|
||||
ti,hwmods = "gpmc";
|
||||
dmas = <&edma 52>;
|
||||
dmas = <&edma 52 0>;
|
||||
dma-names = "rxtx";
|
||||
clocks = <&l3s_gclk>;
|
||||
clock-names = "fck";
|
||||
|
|
|
|||
|
|
@ -794,3 +794,8 @@
|
|||
tx-num-evt = <32>;
|
||||
rx-num-evt = <32>;
|
||||
};
|
||||
|
||||
&synctimer_32kclk {
|
||||
assigned-clocks = <&mux_synctimer32k_ck>;
|
||||
assigned-clock-parents = <&clkdiv32k_ick>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -99,13 +99,6 @@
|
|||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
extcon_usb1: extcon_usb1 {
|
||||
compatible = "linux,extcon-usb-gpio";
|
||||
id-gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&extcon_usb1_pins>;
|
||||
};
|
||||
|
||||
hdmi0: connector {
|
||||
compatible = "hdmi-connector";
|
||||
label = "hdmi";
|
||||
|
|
@ -349,12 +342,6 @@
|
|||
>;
|
||||
};
|
||||
|
||||
extcon_usb1_pins: extcon_usb1_pins {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_rtsn.gpio7_25 */
|
||||
>;
|
||||
};
|
||||
|
||||
tpd12s015_pins: pinmux_tpd12s015_pins {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x37b0, PIN_OUTPUT | MUX_MODE14) /* gpio7_10 CT_CP_HPD */
|
||||
|
|
@ -706,10 +693,6 @@
|
|||
pinctrl-0 = <&usb1_pins>;
|
||||
};
|
||||
|
||||
&omap_dwc3_1 {
|
||||
extcon = <&extcon_usb1>;
|
||||
};
|
||||
|
||||
&omap_dwc3_2 {
|
||||
extcon = <&extcon_usb2>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -117,7 +117,7 @@
|
|||
};
|
||||
|
||||
/* USB part of the eSATA/USB 2.0 port */
|
||||
usb@50000 {
|
||||
usb@58000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -4,6 +4,157 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
&pllss {
|
||||
/*
|
||||
* See TRM "2.6.10 Connected outputso DPLLS" and
|
||||
* "2.6.11 Connected Outputs of DPLLJ". Only clkout is
|
||||
* connected except for hdmi and usb.
|
||||
*/
|
||||
adpll_mpu_ck: adpll@40 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-s-clock";
|
||||
reg = <0x40 0x40>;
|
||||
clocks = <&devosc_ck &devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow", "clkinphif";
|
||||
clock-output-names = "481c5040.adpll.dcoclkldo",
|
||||
"481c5040.adpll.clkout",
|
||||
"481c5040.adpll.clkoutx2",
|
||||
"481c5040.adpll.clkouthif";
|
||||
};
|
||||
|
||||
adpll_dsp_ck: adpll@80 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x80 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5080.adpll.dcoclkldo",
|
||||
"481c5080.adpll.clkout",
|
||||
"481c5080.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_sgx_ck: adpll@b0 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0xb0 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c50b0.adpll.dcoclkldo",
|
||||
"481c50b0.adpll.clkout",
|
||||
"481c50b0.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_hdvic_ck: adpll@e0 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0xe0 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c50e0.adpll.dcoclkldo",
|
||||
"481c50e0.adpll.clkout",
|
||||
"481c50e0.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_l3_ck: adpll@110 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x110 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5110.adpll.dcoclkldo",
|
||||
"481c5110.adpll.clkout",
|
||||
"481c5110.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_isp_ck: adpll@140 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x140 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5140.adpll.dcoclkldo",
|
||||
"481c5140.adpll.clkout",
|
||||
"481c5140.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_dss_ck: adpll@170 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x170 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5170.adpll.dcoclkldo",
|
||||
"481c5170.adpll.clkout",
|
||||
"481c5170.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_video0_ck: adpll@1a0 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x1a0 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c51a0.adpll.dcoclkldo",
|
||||
"481c51a0.adpll.clkout",
|
||||
"481c51a0.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_video1_ck: adpll@1d0 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x1d0 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c51d0.adpll.dcoclkldo",
|
||||
"481c51d0.adpll.clkout",
|
||||
"481c51d0.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_hdmi_ck: adpll@200 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x200 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5200.adpll.dcoclkldo",
|
||||
"481c5200.adpll.clkout",
|
||||
"481c5200.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_audio_ck: adpll@230 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x230 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5230.adpll.dcoclkldo",
|
||||
"481c5230.adpll.clkout",
|
||||
"481c5230.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_usb_ck: adpll@260 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x260 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5260.adpll.dcoclkldo",
|
||||
"481c5260.adpll.clkout",
|
||||
"481c5260.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_ddr_ck: adpll@290 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x290 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5290.adpll.dcoclkldo",
|
||||
"481c5290.adpll.clkout",
|
||||
"481c5290.adpll.clkoutldo";
|
||||
};
|
||||
};
|
||||
|
||||
&pllss_clocks {
|
||||
timer1_fck: timer1_fck {
|
||||
#clock-cells = <0>;
|
||||
|
|
@ -23,6 +174,24 @@
|
|||
reg = <0x2e0>;
|
||||
};
|
||||
|
||||
/* CPTS_RFT_CLK in RMII_REFCLK_SRC, usually sourced from auiod */
|
||||
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&adpll_video0_ck 1
|
||||
&adpll_video1_ck 1
|
||||
&adpll_audio_ck 1>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x2e8>;
|
||||
};
|
||||
|
||||
/* REVISIT: Set up with a proper mux using RMII_REFCLK_SRC */
|
||||
cpsw_125mhz_gclk: cpsw_125mhz_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
sysclk18_ck: sysclk18_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
|
|
@ -79,37 +248,6 @@
|
|||
compatible = "fixed-clock";
|
||||
clock-frequency = <1000000000>;
|
||||
};
|
||||
|
||||
sysclk4_ck: sysclk4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <222000000>;
|
||||
};
|
||||
|
||||
sysclk6_ck: sysclk6_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
sysclk10_ck: sysclk10_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
cpsw_125mhz_gclk: cpsw_125mhz_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <250000000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&prcm_clocks {
|
||||
|
|
@ -138,6 +276,49 @@
|
|||
clock-div = <78125>;
|
||||
};
|
||||
|
||||
/* L4_HS 220 MHz*/
|
||||
sysclk4_ck: sysclk4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,fixed-factor-clock";
|
||||
clocks = <&adpll_l3_ck 1>;
|
||||
ti,clock-mult = <1>;
|
||||
ti,clock-div = <1>;
|
||||
};
|
||||
|
||||
/* L4_FWCFG */
|
||||
sysclk5_ck: sysclk5_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,fixed-factor-clock";
|
||||
clocks = <&adpll_l3_ck 1>;
|
||||
ti,clock-mult = <1>;
|
||||
ti,clock-div = <2>;
|
||||
};
|
||||
|
||||
/* L4_LS 110 MHz */
|
||||
sysclk6_ck: sysclk6_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,fixed-factor-clock";
|
||||
clocks = <&adpll_l3_ck 1>;
|
||||
ti,clock-mult = <1>;
|
||||
ti,clock-div = <2>;
|
||||
};
|
||||
|
||||
sysclk8_ck: sysclk8_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,fixed-factor-clock";
|
||||
clocks = <&adpll_usb_ck 1>;
|
||||
ti,clock-mult = <1>;
|
||||
ti,clock-div = <1>;
|
||||
};
|
||||
|
||||
sysclk10_ck: sysclk10_ck {
|
||||
compatible = "ti,divider-clock";
|
||||
reg = <0x324>;
|
||||
ti,max-div = <7>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&adpll_usb_ck 1>;
|
||||
};
|
||||
|
||||
aud_clkin0_ck: aud_clkin0_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
|
|
|
|||
|
|
@ -6,6 +6,32 @@
|
|||
|
||||
#include "dm814x-clocks.dtsi"
|
||||
|
||||
/* Compared to dm814x, dra62x does not have hdic, l3 or dss PLLs */
|
||||
&adpll_hdvic_ck {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&adpll_l3_ck {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&adpll_dss_ck {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Compared to dm814x, dra62x has interconnect clocks on isp PLL */
|
||||
&sysclk4_ck {
|
||||
clocks = <&adpll_isp_ck 1>;
|
||||
};
|
||||
|
||||
&sysclk5_ck {
|
||||
clocks = <&adpll_isp_ck 1>;
|
||||
};
|
||||
|
||||
&sysclk6_ck {
|
||||
clocks = <&adpll_isp_ck 1>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Compared to dm814x, dra62x has different shifts and more mux options.
|
||||
* Please add the extra options for ysclk_14 and 16 if really needed.
|
||||
|
|
|
|||
|
|
@ -98,12 +98,20 @@
|
|||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
sys_32k_ck: sys_32k_ck {
|
||||
sys_clk32_crystal_ck: sys_clk32_crystal_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin1>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <610>;
|
||||
};
|
||||
|
||||
virt_12000000_ck: virt_12000000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
|
|
@ -2170,4 +2178,12 @@
|
|||
ti,bit-shift = <22>;
|
||||
reg = <0x0558>;
|
||||
};
|
||||
|
||||
sys_32k_ck: sys_32k_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x6c4>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -124,8 +124,6 @@
|
|||
&dp {
|
||||
status = "okay";
|
||||
samsung,color-space = <0>;
|
||||
samsung,dynamic-range = <0>;
|
||||
samsung,ycbcr-coeff = <0>;
|
||||
samsung,color-depth = <1>;
|
||||
samsung,link-rate = <0x0a>;
|
||||
samsung,lane-count = <4>;
|
||||
|
|
|
|||
|
|
@ -80,8 +80,6 @@
|
|||
|
||||
&dp {
|
||||
samsung,color-space = <0>;
|
||||
samsung,dynamic-range = <0>;
|
||||
samsung,ycbcr-coeff = <0>;
|
||||
samsung,color-depth = <1>;
|
||||
samsung,link-rate = <0x0a>;
|
||||
samsung,lane-count = <4>;
|
||||
|
|
|
|||
|
|
@ -236,12 +236,10 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dp_hpd>;
|
||||
samsung,color-space = <0>;
|
||||
samsung,dynamic-range = <0>;
|
||||
samsung,ycbcr-coeff = <0>;
|
||||
samsung,color-depth = <1>;
|
||||
samsung,link-rate = <0x0a>;
|
||||
samsung,lane-count = <2>;
|
||||
samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
|
||||
hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
|
|
|
|||
|
|
@ -74,12 +74,10 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dp_hpd_gpio>;
|
||||
samsung,color-space = <0>;
|
||||
samsung,dynamic-range = <0>;
|
||||
samsung,ycbcr-coeff = <0>;
|
||||
samsung,color-depth = <1>;
|
||||
samsung,link-rate = <0x0a>;
|
||||
samsung,lane-count = <1>;
|
||||
samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
|
||||
hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&ehci {
|
||||
|
|
|
|||
|
|
@ -157,12 +157,10 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dp_hpd_gpio>;
|
||||
samsung,color-space = <0>;
|
||||
samsung,dynamic-range = <0>;
|
||||
samsung,ycbcr-coeff = <0>;
|
||||
samsung,color-depth = <1>;
|
||||
samsung,link-rate = <0x06>;
|
||||
samsung,lane-count = <2>;
|
||||
samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
|
||||
hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
|
|
|
|||
|
|
@ -102,8 +102,6 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dp_hpd>;
|
||||
samsung,color-space = <0>;
|
||||
samsung,dynamic-range = <0>;
|
||||
samsung,ycbcr-coeff = <0>;
|
||||
samsung,color-depth = <1>;
|
||||
samsung,link-rate = <0x0a>;
|
||||
samsung,lane-count = <4>;
|
||||
|
|
|
|||
|
|
@ -157,8 +157,6 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dp_hpd_gpio>;
|
||||
samsung,color-space = <0>;
|
||||
samsung,dynamic-range = <0>;
|
||||
samsung,ycbcr-coeff = <0>;
|
||||
samsung,color-depth = <1>;
|
||||
samsung,link-rate = <0x0a>;
|
||||
samsung,lane-count = <2>;
|
||||
|
|
|
|||
|
|
@ -91,8 +91,8 @@
|
|||
clock-frequency = <141666666>;
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@c1109880 {
|
||||
compatible = "amlogic,meson8-pinctrl";
|
||||
pinctrl_cbus: pinctrl@c1109880 {
|
||||
compatible = "amlogic,meson8-cbus-pinctrl";
|
||||
reg = <0xc1109880 0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -108,29 +108,6 @@
|
|||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio_ao: ao-bank@c1108030 {
|
||||
reg = <0xc8100014 0x4>,
|
||||
<0xc810002c 0x4>,
|
||||
<0xc8100024 0x8>;
|
||||
reg-names = "mux", "pull", "gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
uart_ao_a_pins: uart_ao_a {
|
||||
mux {
|
||||
groups = "uart_tx_ao_a", "uart_rx_ao_a";
|
||||
function = "uart_ao";
|
||||
};
|
||||
};
|
||||
|
||||
i2c_ao_pins: i2c_mst_ao {
|
||||
mux {
|
||||
groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
|
||||
function = "i2c_mst_ao";
|
||||
};
|
||||
};
|
||||
|
||||
spi_nor_pins: nor {
|
||||
mux {
|
||||
groups = "nor_d", "nor_q", "nor_c", "nor_cs";
|
||||
|
|
@ -157,4 +134,34 @@
|
|||
};
|
||||
};
|
||||
|
||||
pinctrl_aobus: pinctrl@c8100084 {
|
||||
compatible = "amlogic,meson8-aobus-pinctrl";
|
||||
reg = <0xc8100084 0xc>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
gpio_ao: ao-bank@c1108030 {
|
||||
reg = <0xc8100014 0x4>,
|
||||
<0xc810002c 0x4>,
|
||||
<0xc8100024 0x8>;
|
||||
reg-names = "mux", "pull", "gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
uart_ao_a_pins: uart_ao_a {
|
||||
mux {
|
||||
groups = "uart_tx_ao_a", "uart_rx_ao_a";
|
||||
function = "uart_ao";
|
||||
};
|
||||
};
|
||||
|
||||
i2c_ao_pins: i2c_mst_ao {
|
||||
mux {
|
||||
groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
|
||||
function = "i2c_mst_ao";
|
||||
};
|
||||
};
|
||||
};
|
||||
}; /* end of / */
|
||||
|
|
|
|||
|
|
@ -155,8 +155,8 @@
|
|||
reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@c1109880 {
|
||||
compatible = "amlogic,meson8b-pinctrl";
|
||||
pinctrl_cbus: pinctrl@c1109880 {
|
||||
compatible = "amlogic,meson8b-cbus-pinctrl";
|
||||
reg = <0xc1109880 0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -171,6 +171,14 @@
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_aobus: pinctrl@c8100084 {
|
||||
compatible = "amlogic,meson8b-aobus-pinctrl";
|
||||
reg = <0xc8100084 0xc>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
gpio_ao: ao-bank@c1108030 {
|
||||
reg = <0xc8100014 0x4>,
|
||||
|
|
|
|||
|
|
@ -329,6 +329,7 @@
|
|||
regulator-name = "V28";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
|
||||
regulator-always-on; /* due to battery cover sensor */
|
||||
};
|
||||
|
||||
|
|
@ -336,30 +337,35 @@
|
|||
regulator-name = "VCSI";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
|
||||
};
|
||||
|
||||
&vaux3 {
|
||||
regulator-name = "VMMC2_30";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
|
||||
};
|
||||
|
||||
&vaux4 {
|
||||
regulator-name = "VCAM_ANA_28";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
|
||||
};
|
||||
|
||||
&vmmc1 {
|
||||
regulator-name = "VMMC1";
|
||||
regulator-min-microvolt = <1850000>;
|
||||
regulator-max-microvolt = <3150000>;
|
||||
regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
|
||||
};
|
||||
|
||||
&vmmc2 {
|
||||
regulator-name = "V28_A";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
|
||||
regulator-always-on; /* due VIO leak to AIC34 VDDs */
|
||||
};
|
||||
|
||||
|
|
@ -367,6 +373,7 @@
|
|||
regulator-name = "VPLL";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
|
|
@ -374,6 +381,7 @@
|
|||
regulator-name = "VSDI_CSI";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
|
|
@ -381,6 +389,7 @@
|
|||
regulator-name = "VMMC2_IO_18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
|
||||
};
|
||||
|
||||
&vio {
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@
|
|||
0x480bd800 0x017c>;
|
||||
interrupts = <24>;
|
||||
iommus = <&mmu_isp>;
|
||||
syscon = <&scm_conf 0xdc>;
|
||||
syscon = <&scm_conf 0x6c>;
|
||||
ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
|
||||
#clock-cells = <1>;
|
||||
ports {
|
||||
|
|
|
|||
|
|
@ -70,7 +70,7 @@
|
|||
compatible = "arm,cortex-a9-twd-timer";
|
||||
clocks = <&mpu_periphclk>;
|
||||
reg = <0x48240600 0x20>;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -472,7 +472,7 @@
|
|||
ldo1_reg: ldo1 {
|
||||
/* VDDAPHY_CAM: vdda_csiport */
|
||||
regulator-name = "ldo1";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
|
|
@ -498,7 +498,7 @@
|
|||
ldo4_reg: ldo4 {
|
||||
/* VDDAPHY_DISP: vdda_dsiport/hdmi */
|
||||
regulator-name = "ldo4";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -513,7 +513,7 @@
|
|||
ldo1_reg: ldo1 {
|
||||
/* VDDAPHY_CAM: vdda_csiport */
|
||||
regulator-name = "ldo1";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
|
|
@ -537,7 +537,7 @@
|
|||
ldo4_reg: ldo4 {
|
||||
/* VDDAPHY_DISP: vdda_dsiport/hdmi */
|
||||
regulator-name = "ldo4";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -269,7 +269,7 @@
|
|||
omap5_pmx_wkup: pinmux@c840 {
|
||||
compatible = "ti,omap5-padconf",
|
||||
"pinctrl-single";
|
||||
reg = <0xc840 0x0038>;
|
||||
reg = <0xc840 0x003c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -666,7 +666,7 @@
|
|||
};
|
||||
|
||||
sata0: sata@29000000 {
|
||||
compatible = "generic-ahci";
|
||||
compatible = "qcom,apq8064-ahci", "generic-ahci";
|
||||
status = "disabled";
|
||||
reg = <0x29000000 0x180>;
|
||||
interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
|
||||
|
|
@ -688,6 +688,7 @@
|
|||
|
||||
phys = <&sata_phy0>;
|
||||
phy-names = "sata-phy";
|
||||
ports-implemented = <0x1>;
|
||||
};
|
||||
|
||||
/* Temporary fixed regulator */
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
|
|
@ -460,8 +460,6 @@
|
|||
clock-names = "core", "iface";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
spmi_bus: spmi@fc4cf000 {
|
||||
|
|
@ -479,16 +477,6 @@
|
|||
interrupt-controller;
|
||||
#interrupt-cells = <4>;
|
||||
};
|
||||
|
||||
blsp2_dma: dma-controller@f9944000 {
|
||||
compatible = "qcom,bam-v1.4.0";
|
||||
reg = <0xf9944000 0x19000>;
|
||||
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP2_AHB_CLK>;
|
||||
clock-names = "bam_clk";
|
||||
#dma-cells = <1>;
|
||||
qcom,ee = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
smd {
|
||||
|
|
|
|||
|
|
@ -661,6 +661,7 @@
|
|||
};
|
||||
|
||||
&pcie_bus_clk {
|
||||
clock-frequency = <100000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -143,19 +143,11 @@
|
|||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
scif0_pins: serial0 {
|
||||
renesas,groups = "scif0_data_d";
|
||||
renesas,function = "scif0";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
renesas,groups = "scif_clk";
|
||||
renesas,function = "scif_clk";
|
||||
};
|
||||
|
||||
ether_pins: ether {
|
||||
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
renesas,function = "eth";
|
||||
|
|
@ -229,11 +221,6 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -414,6 +401,7 @@
|
|||
};
|
||||
|
||||
&pcie_bus_clk {
|
||||
clock-frequency = <100000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1083,9 +1083,8 @@
|
|||
pcie_bus_clk: pcie_bus_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "pcie_bus";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* External SCIF clock */
|
||||
|
|
@ -1094,7 +1093,6 @@
|
|||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* External USB clock - can be overridden by the board */
|
||||
|
|
@ -1112,7 +1110,6 @@
|
|||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "can_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Special CPG clocks */
|
||||
|
|
|
|||
|
|
@ -125,8 +125,6 @@
|
|||
};
|
||||
|
||||
®_dc1sw {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-name = "vcc-lcd";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -63,6 +63,9 @@ CONFIG_INPUT_TOUCHSCREEN=y
|
|||
CONFIG_TOUCHSCREEN_BU21013=y
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_AB8500_PONKEY=y
|
||||
CONFIG_RMI4_CORE=y
|
||||
CONFIG_RMI4_I2C=y
|
||||
CONFIG_RMI4_F11=y
|
||||
# CONFIG_SERIO is not set
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
|
|
|
|||
|
|
@ -276,7 +276,7 @@ static inline int __attribute_const__ cpuid_feature_extract_field(u32 features,
|
|||
int feature = (features >> field) & 15;
|
||||
|
||||
/* feature registers are signed values */
|
||||
if (feature > 8)
|
||||
if (feature > 7)
|
||||
feature -= 16;
|
||||
|
||||
return feature;
|
||||
|
|
|
|||
|
|
@ -84,6 +84,7 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#ifdef CONFIG_CPU_CP15_MMU
|
||||
static inline unsigned int get_domain(void)
|
||||
{
|
||||
unsigned int domain;
|
||||
|
|
@ -103,6 +104,16 @@ static inline void set_domain(unsigned val)
|
|||
: : "r" (val) : "memory");
|
||||
isb();
|
||||
}
|
||||
#else
|
||||
static inline unsigned int get_domain(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void set_domain(unsigned val)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_USE_DOMAINS
|
||||
#define modify_domain(dom,type) \
|
||||
|
|
|
|||
|
|
@ -236,7 +236,7 @@ ENTRY(__setup_mpu)
|
|||
mov r0, #CONFIG_VECTORS_BASE @ Cover from VECTORS_BASE
|
||||
ldr r5,=(MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL)
|
||||
/* Writing N to bits 5:1 (RSR_SZ) --> region size 2^N+1 */
|
||||
mov r6, #(((PAGE_SHIFT - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN)
|
||||
mov r6, #(((2 * PAGE_SHIFT - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN)
|
||||
|
||||
setup_region r0, r5, r6, MPU_DATA_SIDE @ VECTORS_BASE, PL0 NA, enabled
|
||||
beq 3f @ Memory-map not unified
|
||||
|
|
|
|||
|
|
@ -512,7 +512,7 @@ static void __init elf_hwcap_fixup(void)
|
|||
*/
|
||||
if (cpuid_feature_extract(CPUID_EXT_ISAR3, 12) > 1 ||
|
||||
(cpuid_feature_extract(CPUID_EXT_ISAR3, 12) == 1 &&
|
||||
cpuid_feature_extract(CPUID_EXT_ISAR3, 20) >= 3))
|
||||
cpuid_feature_extract(CPUID_EXT_ISAR4, 20) >= 3))
|
||||
elf_hwcap &= ~HWCAP_SWP;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1112,10 +1112,17 @@ static void __init hyp_cpu_pm_init(void)
|
|||
{
|
||||
cpu_pm_register_notifier(&hyp_init_cpu_pm_nb);
|
||||
}
|
||||
static void __init hyp_cpu_pm_exit(void)
|
||||
{
|
||||
cpu_pm_unregister_notifier(&hyp_init_cpu_pm_nb);
|
||||
}
|
||||
#else
|
||||
static inline void hyp_cpu_pm_init(void)
|
||||
{
|
||||
}
|
||||
static inline void hyp_cpu_pm_exit(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
static void teardown_common_resources(void)
|
||||
|
|
@ -1141,9 +1148,7 @@ static int init_subsystems(void)
|
|||
/*
|
||||
* Register CPU Hotplug notifier
|
||||
*/
|
||||
cpu_notifier_register_begin();
|
||||
err = __register_cpu_notifier(&hyp_init_cpu_nb);
|
||||
cpu_notifier_register_done();
|
||||
err = register_cpu_notifier(&hyp_init_cpu_nb);
|
||||
if (err) {
|
||||
kvm_err("Cannot register KVM init CPU notifier (%d)\n", err);
|
||||
return err;
|
||||
|
|
@ -1193,6 +1198,8 @@ static void teardown_hyp_mode(void)
|
|||
free_hyp_pgds();
|
||||
for_each_possible_cpu(cpu)
|
||||
free_page(per_cpu(kvm_arm_hyp_stack_page, cpu));
|
||||
unregister_cpu_notifier(&hyp_init_cpu_nb);
|
||||
hyp_cpu_pm_exit();
|
||||
}
|
||||
|
||||
static int init_vhe_mode(void)
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue