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arm: dts: add qspi support for imx7d sabresd 

add qspi support for imx7d sabresd

Signed-off-by: Han Xu <han.xu@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Han Xu 2019-08-14 19:17:44 -05:00 committed by Dong Aisheng
parent 777f3a3eb1
commit 9a829f97bc
4 changed files with 67 additions and 0 deletions
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1
arch/arm/boot/dts/Makefile
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@ -607,6 +607,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-sbc-imx7.dtb \
imx7d-sdb.dtb \
imx7d-sdb-m4.dtb \
imx7d-sdb-qspi.dtb \
imx7d-sdb-reva.dtb \
imx7d-sdb-sht11.dtb \
imx7d-zii-rmu2.dtb \

9
arch/arm/boot/dts/imx7d-sdb-qspi.dts 100644
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@ -0,0 +1,9 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx7d-sdb.dts"
#include "imx7d-sdb-qspi.dtsi"

44
arch/arm/boot/dts/imx7d-sdb-qspi.dtsi 100644
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@ -0,0 +1,44 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* disable epdc, conflict with qspi */
/* &epdc { */
/* status = "disabled"; */
/* }; */
&iomuxc {
qspi1 {
pinctrl_qspi1_1: qspi1grp_1 {
fsl,pins = <
MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51
MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51
MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51
MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51
MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51
MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51
>;
};
};
};
&qspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi1_1>;
status = "okay";
ddrsmp=<0>;
flash0: mx25l51245g@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "macronix,mx25l51245g";
spi-max-frequency = <29000000>;
/* take off one dummy cycle */
spi-nor,ddr-quad-read-dummy = <5>;
reg = <0>;
};
};

13
arch/arm/boot/dts/imx7d.dtsi
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@ -211,6 +211,19 @@
status = "disabled";
};
qspi1: spi@30bb0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7d-qspi";
reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
<&clks IMX7D_QSPI_ROOT_CLK>;
clock-names = "qspi_en", "qspi";
status = "disabled";
};
sim2: sim@30ba0000 {
compatible = "fsl,imx7d-sim";
reg = <0x30ba0000 0x10000>;