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PCI: mobiveil: Make mobiveil_host_init() can be used to re-init host

Make the mobiveil_host_init() function can be used to re-init
host controller's PAB and GPEX CSR register block, as NXP
integrated Mobiveil IP has to reset and then re-init the PAB
and GPEX CSR registers upon hot-reset.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
5.4-rM2-2.2.x-imx-squashed
Hou Zhiqiang 2019-06-25 09:09:14 +00:00 committed by Dong Aisheng
parent f619c54210
commit 9a9fe7dbd9
2 changed files with 24 additions and 22 deletions

View File

@ -215,16 +215,21 @@ static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET); writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
} }
static int mobiveil_host_init(struct mobiveil_pcie *pcie) int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit)
{ {
u32 value, pab_ctrl, type; u32 value, pab_ctrl, type;
struct resource_entry *win; struct resource_entry *win;
/* setup bus numbers */ pcie->ib_wins_configured = 0;
value = csr_readl(pcie, PCI_PRIMARY_BUS); pcie->ob_wins_configured = 0;
value &= 0xff000000;
value |= 0x00ff0100; if (!reinit) {
csr_writel(pcie, value, PCI_PRIMARY_BUS); /* setup bus numbers */
value = csr_readl(pcie, PCI_PRIMARY_BUS);
value &= 0xff000000;
value |= 0x00ff0100;
csr_writel(pcie, value, PCI_PRIMARY_BUS);
}
/* /*
* program Bus Master Enable Bit in Command Register in PAB Config * program Bus Master Enable Bit in Command Register in PAB Config
@ -270,7 +275,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
/* Get the I/O and memory ranges from DT */ /* Get the I/O and memory ranges from DT */
resource_list_for_each_entry(win, &pcie->resources) { resource_list_for_each_entry(win, pcie->resources) {
if (resource_type(win->res) == IORESOURCE_MEM) { if (resource_type(win->res) == IORESOURCE_MEM) {
type = MEM_WINDOW_TYPE; type = MEM_WINDOW_TYPE;
} else if (resource_type(win->res) == IORESOURCE_IO) { } else if (resource_type(win->res) == IORESOURCE_IO) {
@ -541,8 +546,6 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
resource_size_t iobase; resource_size_t iobase;
int ret; int ret;
INIT_LIST_HEAD(&pcie->resources);
ret = mobiveil_pcie_parse_dt(pcie); ret = mobiveil_pcie_parse_dt(pcie);
if (ret) { if (ret) {
dev_err(dev, "Parsing DT failed, ret: %x\n", ret); dev_err(dev, "Parsing DT failed, ret: %x\n", ret);
@ -551,34 +554,35 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
/* parse the host bridge base addresses from the device tree file */ /* parse the host bridge base addresses from the device tree file */
ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
&pcie->resources, &iobase); &bridge->windows, &iobase);
if (ret) { if (ret) {
dev_err(dev, "Getting bridge resources failed\n"); dev_err(dev, "Getting bridge resources failed\n");
return ret; return ret;
} }
pcie->resources = &bridge->windows;
/* /*
* configure all inbound and outbound windows and prepare the RC for * configure all inbound and outbound windows and prepare the RC for
* config access * config access
*/ */
ret = mobiveil_host_init(pcie); ret = mobiveil_host_init(pcie, false);
if (ret) { if (ret) {
dev_err(dev, "Failed to initialize host\n"); dev_err(dev, "Failed to initialize host\n");
goto error; return ret;
} }
ret = mobiveil_pcie_interrupt_init(pcie); ret = mobiveil_pcie_interrupt_init(pcie);
if (ret) { if (ret) {
dev_err(dev, "Interrupt init failed\n"); dev_err(dev, "Interrupt init failed\n");
goto error; return ret;
} }
ret = devm_request_pci_bus_resources(dev, &pcie->resources); ret = devm_request_pci_bus_resources(dev, pcie->resources);
if (ret) if (ret)
goto error; return ret;
/* Initialize bridge */ /* Initialize bridge */
list_splice_init(&pcie->resources, &bridge->windows);
bridge->dev.parent = dev; bridge->dev.parent = dev;
bridge->sysdata = pcie; bridge->sysdata = pcie;
bridge->busnr = pcie->rp.root_bus_nr; bridge->busnr = pcie->rp.root_bus_nr;
@ -589,13 +593,13 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
ret = mobiveil_bringup_link(pcie); ret = mobiveil_bringup_link(pcie);
if (ret) { if (ret) {
dev_info(dev, "link bring-up failed\n"); dev_info(dev, "link bring-up failed\n");
goto error; return ret;
} }
/* setup the kernel resources for the newly added PCIe root bus */ /* setup the kernel resources for the newly added PCIe root bus */
ret = pci_scan_root_bus_bridge(bridge); ret = pci_scan_root_bus_bridge(bridge);
if (ret) if (ret)
goto error; return ret;
bus = bridge->bus; bus = bridge->bus;
@ -605,7 +609,4 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
pci_bus_add_devices(bus); pci_bus_add_devices(bus);
return 0; return 0;
error:
pci_free_resource_list(&pcie->resources);
return ret;
} }

View File

@ -153,7 +153,7 @@ struct mobiveil_pab_ops {
struct mobiveil_pcie { struct mobiveil_pcie {
struct platform_device *pdev; struct platform_device *pdev;
struct list_head resources; struct list_head *resources;
void __iomem *csr_axi_slave_base; /* PAB registers base */ void __iomem *csr_axi_slave_base; /* PAB registers base */
phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */ phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */
void __iomem *apb_csr_base; /* MSI register base */ void __iomem *apb_csr_base; /* MSI register base */
@ -167,6 +167,7 @@ struct mobiveil_pcie {
}; };
int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie); int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit);
bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie); bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie);
int mobiveil_bringup_link(struct mobiveil_pcie *pcie); int mobiveil_bringup_link(struct mobiveil_pcie *pcie);
void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr, void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,