PCI: mobiveil: Make mobiveil_host_init() can be used to re-init host
Make the mobiveil_host_init() function can be used to re-init host controller's PAB and GPEX CSR register block, as NXP integrated Mobiveil IP has to reset and then re-init the PAB and GPEX CSR registers upon hot-reset. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>5.4-rM2-2.2.x-imx-squashed
parent
f619c54210
commit
9a9fe7dbd9
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@ -215,16 +215,21 @@ static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
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writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
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writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
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}
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}
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static int mobiveil_host_init(struct mobiveil_pcie *pcie)
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int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit)
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{
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{
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u32 value, pab_ctrl, type;
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u32 value, pab_ctrl, type;
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struct resource_entry *win;
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struct resource_entry *win;
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/* setup bus numbers */
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pcie->ib_wins_configured = 0;
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value = csr_readl(pcie, PCI_PRIMARY_BUS);
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pcie->ob_wins_configured = 0;
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value &= 0xff000000;
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value |= 0x00ff0100;
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if (!reinit) {
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csr_writel(pcie, value, PCI_PRIMARY_BUS);
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/* setup bus numbers */
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value = csr_readl(pcie, PCI_PRIMARY_BUS);
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value &= 0xff000000;
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value |= 0x00ff0100;
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csr_writel(pcie, value, PCI_PRIMARY_BUS);
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}
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/*
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/*
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* program Bus Master Enable Bit in Command Register in PAB Config
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* program Bus Master Enable Bit in Command Register in PAB Config
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@ -270,7 +275,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
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program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
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program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
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/* Get the I/O and memory ranges from DT */
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/* Get the I/O and memory ranges from DT */
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resource_list_for_each_entry(win, &pcie->resources) {
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resource_list_for_each_entry(win, pcie->resources) {
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if (resource_type(win->res) == IORESOURCE_MEM) {
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if (resource_type(win->res) == IORESOURCE_MEM) {
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type = MEM_WINDOW_TYPE;
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type = MEM_WINDOW_TYPE;
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} else if (resource_type(win->res) == IORESOURCE_IO) {
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} else if (resource_type(win->res) == IORESOURCE_IO) {
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@ -541,8 +546,6 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
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resource_size_t iobase;
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resource_size_t iobase;
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int ret;
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int ret;
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INIT_LIST_HEAD(&pcie->resources);
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ret = mobiveil_pcie_parse_dt(pcie);
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ret = mobiveil_pcie_parse_dt(pcie);
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if (ret) {
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if (ret) {
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dev_err(dev, "Parsing DT failed, ret: %x\n", ret);
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dev_err(dev, "Parsing DT failed, ret: %x\n", ret);
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@ -551,34 +554,35 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
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/* parse the host bridge base addresses from the device tree file */
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/* parse the host bridge base addresses from the device tree file */
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ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
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ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
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&pcie->resources, &iobase);
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&bridge->windows, &iobase);
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if (ret) {
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if (ret) {
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dev_err(dev, "Getting bridge resources failed\n");
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dev_err(dev, "Getting bridge resources failed\n");
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return ret;
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return ret;
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}
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}
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pcie->resources = &bridge->windows;
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/*
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/*
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* configure all inbound and outbound windows and prepare the RC for
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* configure all inbound and outbound windows and prepare the RC for
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* config access
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* config access
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*/
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*/
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ret = mobiveil_host_init(pcie);
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ret = mobiveil_host_init(pcie, false);
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if (ret) {
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if (ret) {
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dev_err(dev, "Failed to initialize host\n");
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dev_err(dev, "Failed to initialize host\n");
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goto error;
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return ret;
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}
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}
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ret = mobiveil_pcie_interrupt_init(pcie);
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ret = mobiveil_pcie_interrupt_init(pcie);
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if (ret) {
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if (ret) {
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dev_err(dev, "Interrupt init failed\n");
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dev_err(dev, "Interrupt init failed\n");
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goto error;
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return ret;
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}
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}
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ret = devm_request_pci_bus_resources(dev, &pcie->resources);
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ret = devm_request_pci_bus_resources(dev, pcie->resources);
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if (ret)
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if (ret)
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goto error;
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return ret;
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/* Initialize bridge */
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/* Initialize bridge */
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list_splice_init(&pcie->resources, &bridge->windows);
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bridge->dev.parent = dev;
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bridge->dev.parent = dev;
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bridge->sysdata = pcie;
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bridge->sysdata = pcie;
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bridge->busnr = pcie->rp.root_bus_nr;
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bridge->busnr = pcie->rp.root_bus_nr;
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@ -589,13 +593,13 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
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ret = mobiveil_bringup_link(pcie);
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ret = mobiveil_bringup_link(pcie);
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if (ret) {
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if (ret) {
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dev_info(dev, "link bring-up failed\n");
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dev_info(dev, "link bring-up failed\n");
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goto error;
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return ret;
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}
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}
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/* setup the kernel resources for the newly added PCIe root bus */
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/* setup the kernel resources for the newly added PCIe root bus */
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ret = pci_scan_root_bus_bridge(bridge);
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ret = pci_scan_root_bus_bridge(bridge);
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if (ret)
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if (ret)
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goto error;
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return ret;
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bus = bridge->bus;
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bus = bridge->bus;
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@ -605,7 +609,4 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
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pci_bus_add_devices(bus);
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pci_bus_add_devices(bus);
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return 0;
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return 0;
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error:
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pci_free_resource_list(&pcie->resources);
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return ret;
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}
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}
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@ -153,7 +153,7 @@ struct mobiveil_pab_ops {
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struct mobiveil_pcie {
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struct mobiveil_pcie {
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struct platform_device *pdev;
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struct platform_device *pdev;
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struct list_head resources;
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struct list_head *resources;
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void __iomem *csr_axi_slave_base; /* PAB registers base */
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void __iomem *csr_axi_slave_base; /* PAB registers base */
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phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */
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phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */
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void __iomem *apb_csr_base; /* MSI register base */
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void __iomem *apb_csr_base; /* MSI register base */
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@ -167,6 +167,7 @@ struct mobiveil_pcie {
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};
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};
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int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
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int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
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int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit);
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bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie);
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bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie);
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int mobiveil_bringup_link(struct mobiveil_pcie *pcie);
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int mobiveil_bringup_link(struct mobiveil_pcie *pcie);
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void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
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void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
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