drm/i915: Ignore fenced commands for gpu access on gen4
Userspace should not have been declaring that it needed fenced GPU access with gen4+ as those GPUs have no fenced commands, but to be on the safe side it is easier to ignore userspace in case they did. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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@ -432,6 +432,7 @@ i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
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struct drm_i915_gem_object *obj;
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struct drm_i915_gem_exec_object2 *entry;
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int ret, retry;
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bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
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/* Attempt to pin all of the buffers into the GTT.
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* This is done in 3 phases:
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@ -460,6 +461,7 @@ i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
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}
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need_fence =
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has_fenced_gpu_access &&
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entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
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obj->tiling_mode != I915_TILING_NONE;
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need_mappable =
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@ -484,6 +486,7 @@ i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
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bool need_fence;
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need_fence =
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has_fenced_gpu_access &&
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entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
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obj->tiling_mode != I915_TILING_NONE;
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@ -498,18 +501,20 @@ i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
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break;
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}
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if (need_fence) {
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ret = i915_gem_object_get_fence(obj, ring, 1);
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if (ret)
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break;
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} else if (entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
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obj->tiling_mode == I915_TILING_NONE) {
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/* XXX pipelined! */
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ret = i915_gem_object_put_fence(obj);
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if (ret)
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break;
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if (has_fenced_gpu_access) {
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if (need_fence) {
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ret = i915_gem_object_get_fence(obj, ring, 1);
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if (ret)
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break;
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} else if (entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
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obj->tiling_mode == I915_TILING_NONE) {
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/* XXX pipelined! */
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ret = i915_gem_object_put_fence(obj);
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if (ret)
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break;
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}
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obj->pending_fenced_gpu_access = need_fence;
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}
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obj->pending_fenced_gpu_access = need_fence;
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entry->offset = obj->gtt_offset;
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entry++;
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