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drm/i915/ehl: Set proper eu slice/subslice parameters for EHL

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EHL has a different number of subslices.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190322175847.25707-5-rodrigo.vivi@intel.com
This commit is contained in:
Bob Paauwe 2019-03-22 10:58:46 -07:00 committed by Rodrigo Vivi
parent 759c9ab55b
commit 9b7598a99a
1 changed files with 9 additions and 3 deletions
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6
drivers/gpu/drm/i915/intel_device_info.c
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@ -156,9 +156,15 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
u8 eu_en; u8 eu_en;
int s; int s;
if (IS_ELKHARTLAKE(dev_priv)) {
sseu->max_slices = 1;
sseu->max_subslices = 4;
sseu->max_eus_per_subslice = 8;
} else {
sseu->max_slices = 1; sseu->max_slices = 1;
sseu->max_subslices = 8; sseu->max_subslices = 8;
sseu->max_eus_per_subslice = 8; sseu->max_eus_per_subslice = 8;
}
s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE); ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);