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drm/tegra: Changes for v4.16-rc1 

The bulk of these changes are preparation work and addition of support
 for Tegra186. Currently only HDMI output (the primary output on Jetson
 TX2) is supported, but the hardware is also capable of doing DSI and
 DisplayPort.
 
 Tegra DRM now also uses the atomic commit helpers instead of the open-
 coded variant that was only doing half its job. As a bit of a byproduct
 of the Tegra186 support the driver also gained HDMI 2.0 as well as zpos
 property support.
 
 Along the way there are also a few patches to clean up a few things and
 fix minor issues.
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Merge tag 'drm/tegra/for-4.16-rc1-fixes' of git://anongit.freedesktop.org/tegra/linux into drm-next

drm/tegra: Changes for v4.16-rc1

The bulk of these changes are preparation work and addition of support
for Tegra186. Currently only HDMI output (the primary output on Jetson
TX2) is supported, but the hardware is also capable of doing DSI and
DisplayPort.

Tegra DRM now also uses the atomic commit helpers instead of the open-
coded variant that was only doing half its job. As a bit of a byproduct
of the Tegra186 support the driver also gained HDMI 2.0 as well as zpos
property support.

Along the way there are also a few patches to clean up a few things and
fix minor issues.

* tag 'drm/tegra/for-4.16-rc1-fixes' of git://anongit.freedesktop.org/tegra/linux: (51 commits)
  drm/tegra: dc: Properly cleanup overlay planes
  drm/tegra: dc: Fix possible_crtcs mask for planes
  drm/tegra: dc: Restore YUV overlay support
  drm/tegra: dc: Implement legacy blending
  drm/tegra: Correct timeout in tegra_syncpt_wait
  drm/tegra: gem: Correct iommu_map_sg() error checking
  drm/tegra: dc: Link DC1 to DC0 on Tegra20
  drm/tegra: Fix non-debugfs builds
  drm/tegra: dpaux: Keep reset defaults for hybrid pad parameters
  drm/tegra: Mark Tegra186 display hub PM functions __maybe_unused
  drm/tegra: Use IOMMU groups
  gpu: host1x: Use IOMMU groups
  drm/tegra: Implement zpos property
  drm/tegra: dc: Remove redundant spinlock
  drm/tegra: dc: Use direct offset to plane registers
  drm/tegra: dc: Support more formats
  drm/tegra: fb: Force alpha formats
  drm/tegra: dpaux: Add Tegra186 support
  drm/tegra: dpaux: Implement runtime PM
  drm/tegra: sor: Support HDMI 2.0 modes
  ...
hifive-unleashed-5.1
Dave Airlie 2018-01-12 11:46:19 +10:00
parent 323b20c4af 8f62142e49
commit 9be712ef46
23 changed files with 4102 additions and 1849 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
View File

@ -206,21 +206,33 @@ of the following host1x client modules:
- "nvidia,tegra132-sor": for Tegra132
- "nvidia,tegra210-sor": for Tegra210
- "nvidia,tegra210-sor1": for Tegra210
- "nvidia,tegra186-sor": for Tegra186
- "nvidia,tegra186-sor1": for Tegra186
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller.
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- sor: clock input for the SOR hardware
- source: source clock for the SOR clock
- out: SOR output clock
- parent: input for the pixel clock
- dp: reference clock for the SOR clock
- safe: safe reference for the SOR clock during power up
For Tegra186 and later:
- pad: SOR pad output clock (on Tegra186 and later)
Obsolete:
- source: source clock for the SOR clock (obsolete, use "out" instead)
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- sor
Required properties on Tegra186 and later:
- nvidia,interface: index of the SOR interface
Optional properties:
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection

2
drivers/gpu/drm/tegra/Makefile
View File

@ -5,6 +5,8 @@ tegra-drm-y := \
drm.o \
gem.o \
fb.o \
hub.o \
plane.o \
dc.o \
output.o \
rgb.o \

1934
drivers/gpu/drm/tegra/dc.c
View File

File diff suppressed because it is too large Load Diff

289
drivers/gpu/drm/tegra/dc.h
View File

@ -18,6 +18,24 @@
struct tegra_output;
struct tegra_dc_state {
struct drm_crtc_state base;
struct clk *clk;
unsigned long pclk;
unsigned int div;
u32 planes;
};
static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
{
if (state)
return container_of(state, struct tegra_dc_state, base);
return NULL;
}
struct tegra_dc_stats {
unsigned long frames;
unsigned long vblank;
@ -25,21 +43,35 @@ struct tegra_dc_stats {
unsigned long overflow;
};
struct tegra_windowgroup_soc {
unsigned int index;
unsigned int dc;
const unsigned int *windows;
unsigned int num_windows;
};
struct tegra_dc_soc_info {
bool supports_border_color;
bool supports_background_color;
bool supports_interlacing;
bool supports_cursor;
bool supports_block_linear;
bool supports_blending;
unsigned int pitch_align;
bool has_powergate;
bool broken_reset;
bool coupled_pm;
bool has_nvdisplay;
const struct tegra_windowgroup_soc *wgrps;
unsigned int num_wgrps;
const u32 *primary_formats;
unsigned int num_primary_formats;
const u32 *overlay_formats;
unsigned int num_overlay_formats;
};
struct tegra_dc {
struct host1x_client client;
struct host1x_syncpt *syncpt;
struct device *dev;
spinlock_t lock;
struct drm_crtc base;
unsigned int powergate;
@ -56,11 +88,6 @@ struct tegra_dc {
struct list_head list;
struct drm_info_list *debugfs_files;
struct drm_minor *minor;
struct dentry *debugfs;
/* page-flip handling */
struct drm_pending_vblank_event *event;
const struct tegra_dc_soc_info *soc;
@ -110,6 +137,7 @@ struct tegra_dc_window {
unsigned int bits_per_pixel;
unsigned int stride[2];
unsigned long base[3];
unsigned int zpos;
bool bottom_up;
struct tegra_bo_tiling tiling;
@ -118,6 +146,7 @@ struct tegra_dc_window {
};
/* from dc.c */
bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev);
void tegra_dc_commit(struct tegra_dc *dc);
int tegra_dc_state_setup_clock(struct tegra_dc *dc,
struct drm_crtc_state *crtc_state,
@ -167,15 +196,26 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
#define DC_CMD_INT_ENABLE 0x039
#define DC_CMD_INT_TYPE 0x03a
#define DC_CMD_INT_POLARITY 0x03b
#define CTXSW_INT (1 << 0)
#define FRAME_END_INT (1 << 1)
#define VBLANK_INT (1 << 2)
#define WIN_A_UF_INT (1 << 8)
#define WIN_B_UF_INT (1 << 9)
#define WIN_C_UF_INT (1 << 10)
#define WIN_A_OF_INT (1 << 14)
#define WIN_B_OF_INT (1 << 15)
#define WIN_C_OF_INT (1 << 16)
#define CTXSW_INT (1 << 0)
#define FRAME_END_INT (1 << 1)
#define VBLANK_INT (1 << 2)
#define V_PULSE3_INT (1 << 4)
#define V_PULSE2_INT (1 << 5)
#define REGION_CRC_INT (1 << 6)
#define REG_TMOUT_INT (1 << 7)
#define WIN_A_UF_INT (1 << 8)
#define WIN_B_UF_INT (1 << 9)
#define WIN_C_UF_INT (1 << 10)
#define MSF_INT (1 << 12)
#define WIN_A_OF_INT (1 << 14)
#define WIN_B_OF_INT (1 << 15)
#define WIN_C_OF_INT (1 << 16)
#define HEAD_UF_INT (1 << 23)
#define SD3_BUCKET_WALK_DONE_INT (1 << 24)
#define DSC_OBUF_UF_INT (1 << 26)
#define DSC_RBUF_UF_INT (1 << 27)
#define DSC_BBUF_UF_INT (1 << 28)
#define DSC_TO_UF_INT (1 << 29)
#define DC_CMD_SIGNAL_RAISE1 0x03c
#define DC_CMD_SIGNAL_RAISE2 0x03d
@ -196,6 +236,8 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
#define WIN_B_UPDATE (1 << 10)
#define WIN_C_UPDATE (1 << 11)
#define CURSOR_UPDATE (1 << 15)
#define COMMON_ACTREQ (1 << 16)
#define COMMON_UPDATE (1 << 17)
#define NC_HOST_TRIG (1 << 24)
#define DC_CMD_DISPLAY_WINDOW_HEADER 0x042
@ -238,6 +280,10 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
#define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328
#define DC_COM_CRC_CHECKSUM_LATCHED 0x329
#define DC_COM_RG_UNDERFLOW 0x365
#define UNDERFLOW_MODE_RED (1 << 8)
#define UNDERFLOW_REPORT_ENABLE (1 << 0)
#define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400
#define H_PULSE0_ENABLE (1 << 8)
#define H_PULSE1_ENABLE (1 << 10)
@ -249,10 +295,10 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
#define HDMI_ENABLE (1 << 30)
#define DSI_ENABLE (1 << 29)
#define SOR1_TIMING_CYA (1 << 27)
#define SOR1_ENABLE (1 << 26)
#define SOR_ENABLE (1 << 25)
#define CURSOR_ENABLE (1 << 16)
#define SOR_ENABLE(x) (1 << (25 + (x)))
#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
#define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24)
#define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16)
@ -360,29 +406,33 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
#define DISP_ORDER_BLUE_RED (1 << 9)
#define DC_DISP_DISP_COLOR_CONTROL 0x430
#define BASE_COLOR_SIZE666 (0 << 0)
#define BASE_COLOR_SIZE111 (1 << 0)
#define BASE_COLOR_SIZE222 (2 << 0)
#define BASE_COLOR_SIZE333 (3 << 0)
#define BASE_COLOR_SIZE444 (4 << 0)
#define BASE_COLOR_SIZE555 (5 << 0)
#define BASE_COLOR_SIZE565 (6 << 0)
#define BASE_COLOR_SIZE332 (7 << 0)
#define BASE_COLOR_SIZE888 (8 << 0)
#define BASE_COLOR_SIZE666 ( 0 << 0)
#define BASE_COLOR_SIZE111 ( 1 << 0)
#define BASE_COLOR_SIZE222 ( 2 << 0)
#define BASE_COLOR_SIZE333 ( 3 << 0)
#define BASE_COLOR_SIZE444 ( 4 << 0)
#define BASE_COLOR_SIZE555 ( 5 << 0)
#define BASE_COLOR_SIZE565 ( 6 << 0)
#define BASE_COLOR_SIZE332 ( 7 << 0)
#define BASE_COLOR_SIZE888 ( 8 << 0)
#define BASE_COLOR_SIZE101010 (10 << 0)
#define BASE_COLOR_SIZE121212 (12 << 0)
#define DITHER_CONTROL_MASK (3 << 8)
#define DITHER_CONTROL_DISABLE (0 << 8)
#define DITHER_CONTROL_ORDERED (2 << 8)
#define DITHER_CONTROL_ERRDIFF (3 << 8)
#define BASE_COLOR_SIZE_MASK (0xf << 0)
#define BASE_COLOR_SIZE_666 (0 << 0)
#define BASE_COLOR_SIZE_111 (1 << 0)
#define BASE_COLOR_SIZE_222 (2 << 0)
#define BASE_COLOR_SIZE_333 (3 << 0)
#define BASE_COLOR_SIZE_444 (4 << 0)
#define BASE_COLOR_SIZE_555 (5 << 0)
#define BASE_COLOR_SIZE_565 (6 << 0)
#define BASE_COLOR_SIZE_332 (7 << 0)
#define BASE_COLOR_SIZE_888 (8 << 0)
#define BASE_COLOR_SIZE_666 ( 0 << 0)
#define BASE_COLOR_SIZE_111 ( 1 << 0)
#define BASE_COLOR_SIZE_222 ( 2 << 0)
#define BASE_COLOR_SIZE_333 ( 3 << 0)
#define BASE_COLOR_SIZE_444 ( 4 << 0)
#define BASE_COLOR_SIZE_555 ( 5 << 0)
#define BASE_COLOR_SIZE_565 ( 6 << 0)
#define BASE_COLOR_SIZE_332 ( 7 << 0)
#define BASE_COLOR_SIZE_888 ( 8 << 0)
#define BASE_COLOR_SIZE_101010 ( 10 << 0)
#define BASE_COLOR_SIZE_121212 ( 12 << 0)
#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
#define SC1_H_QUALIFIER_NONE (1 << 16)
@ -449,6 +499,12 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
#define DC_DISP_SD_HW_K_VALUES 0x4dd
#define DC_DISP_SD_MAN_K_VALUES 0x4de
#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4e4
#define BACKGROUND_COLOR_ALPHA(x) (((x) & 0xff) << 24)
#define BACKGROUND_COLOR_BLUE(x) (((x) & 0xff) << 16)
#define BACKGROUND_COLOR_GREEN(x) (((x) & 0xff) << 8)
#define BACKGROUND_COLOR_RED(x) (((x) & 0xff) << 0)
#define DC_DISP_INTERLACE_CONTROL 0x4e5
#define INTERLACE_STATUS (1 << 2)
#define INTERLACE_START (1 << 1)
@ -467,6 +523,35 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
#define CURSOR_SRC_BLEND_MASK (3 << 8)
#define CURSOR_ALPHA 0xff
#define DC_WIN_CORE_ACT_CONTROL 0x50e
#define VCOUNTER (0 << 0)
#define HCOUNTER (1 << 0)
#define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA 0x543
#define LATENCY_CTL_MODE_ENABLE (1 << 2)
#define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB 0x544
#define WATERMARK_MASK 0x1fffffff
#define DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER 0x560
#define PIPE_METER_INT(x) (((x) & 0xff) << 8)
#define PIPE_METER_FRAC(x) (((x) & 0xff) << 0)
#define DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG 0x561
#define MEMPOOL_ENTRIES(x) (((x) & 0xffff) << 0)
#define DC_WIN_CORE_IHUB_WGRP_FETCH_METER 0x562
#define SLOTS(x) (((x) & 0xff) << 0)
#define DC_WIN_CORE_IHUB_LINEBUF_CONFIG 0x563
#define MODE_TWO_LINES (0 << 14)
#define MODE_FOUR_LINES (1 << 14)
#define DC_WIN_CORE_IHUB_THREAD_GROUP 0x568
#define THREAD_NUM_MASK (0x1f << 1)
#define THREAD_NUM(x) (((x) & 0x1f) << 1)
#define THREAD_GROUP_ENABLE (1 << 0)
#define DC_WIN_CSC_YOF 0x611
#define DC_WIN_CSC_KYRGB 0x612
#define DC_WIN_CSC_KUR 0x613
@ -502,9 +587,9 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
#define WIN_COLOR_DEPTH_P4 2
#define WIN_COLOR_DEPTH_P8 3
#define WIN_COLOR_DEPTH_B4G4R4A4 4
#define WIN_COLOR_DEPTH_B5G5R5A 5
#define WIN_COLOR_DEPTH_B5G5R5A1 5
#define WIN_COLOR_DEPTH_B5G6R5 6
#define WIN_COLOR_DEPTH_AB5G5R5 7
#define WIN_COLOR_DEPTH_A1B5G5R5 7
#define WIN_COLOR_DEPTH_B8G8R8A8 12
#define WIN_COLOR_DEPTH_R8G8B8A8 13
#define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14
@ -519,18 +604,32 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
#define WIN_COLOR_DEPTH_YUV422R 23
#define WIN_COLOR_DEPTH_YCbCr422RA 24
#define WIN_COLOR_DEPTH_YUV422RA 25
#define WIN_COLOR_DEPTH_R4G4B4A4 27
#define WIN_COLOR_DEPTH_R5G5B5A 28
#define WIN_COLOR_DEPTH_AR5G5B5 29
#define WIN_COLOR_DEPTH_B5G5R5X1 30
#define WIN_COLOR_DEPTH_X1B5G5R5 31
#define WIN_COLOR_DEPTH_R5G5B5X1 32
#define WIN_COLOR_DEPTH_X1R5G5B5 33
#define WIN_COLOR_DEPTH_R5G6B5 34
#define WIN_COLOR_DEPTH_A8R8G8B8 35
#define WIN_COLOR_DEPTH_A8B8G8R8 36
#define WIN_COLOR_DEPTH_B8G8R8X8 37
#define WIN_COLOR_DEPTH_R8G8B8X8 38
#define WIN_COLOR_DEPTH_X8B8G8R8 65
#define WIN_COLOR_DEPTH_X8R8G8B8 66
#define DC_WIN_POSITION 0x704
#define H_POSITION(x) (((x) & 0x1fff) << 0)
#define V_POSITION(x) (((x) & 0x1fff) << 16)
#define H_POSITION(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */
#define V_POSITION(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
#define DC_WIN_SIZE 0x705
#define H_SIZE(x) (((x) & 0x1fff) << 0)
#define V_SIZE(x) (((x) & 0x1fff) << 16)
#define H_SIZE(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */
#define V_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
#define DC_WIN_PRESCALED_SIZE 0x706
#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0)
#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16)
#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
#define DC_WIN_H_INITIAL_DDA 0x707
#define DC_WIN_V_INITIAL_DDA 0x708
@ -546,11 +645,24 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
#define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0)
#define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16)
#define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16)
#define DC_WIN_DV_CONTROL 0x70e
#define DC_WIN_BLEND_NOKEY 0x70f
#define BLEND_WEIGHT1(x) (((x) & 0xff) << 16)
#define BLEND_WEIGHT0(x) (((x) & 0xff) << 8)
#define DC_WIN_BLEND_1WIN 0x710
#define BLEND_CONTROL_FIX (0 << 2)
#define BLEND_CONTROL_ALPHA (1 << 2)
#define BLEND_COLOR_KEY_NONE (0 << 0)
#define BLEND_COLOR_KEY_0 (1 << 0)
#define BLEND_COLOR_KEY_1 (2 << 0)
#define BLEND_COLOR_KEY_BOTH (3 << 0)
#define DC_WIN_BLEND_2WIN_X 0x711
#define BLEND_CONTROL_DEPENDENT (2 << 2)
#define DC_WIN_BLEND_2WIN_Y 0x712
#define DC_WIN_BLEND_3WIN_XY 0x713
@ -575,8 +687,97 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
#define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0)
#define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4)
#define DC_WINBUF_START_ADDR_HI 0x80d
#define DC_WINBUF_CDE_CONTROL 0x82f
#define ENABLE_SURFACE (1 << 0)
#define DC_WINBUF_AD_UFLOW_STATUS 0xbca
#define DC_WINBUF_BD_UFLOW_STATUS 0xdca
#define DC_WINBUF_CD_UFLOW_STATUS 0xfca
/* Tegra186 and later */
#define DC_DISP_CORE_SOR_SET_CONTROL(x) (0x403 + (x))
#define PROTOCOL_MASK (0xf << 8)
#define PROTOCOL_SINGLE_TMDS_A (0x1 << 8)
#define DC_WIN_CORE_WINDOWGROUP_SET_CONTROL 0x702
#define OWNER_MASK (0xf << 0)
#define OWNER(x) (((x) & 0xf) << 0)
#define DC_WIN_CROPPED_SIZE 0x706
#define DC_WIN_PLANAR_STORAGE 0x709
#define PITCH(x) (((x) >> 6) & 0x1fff)
#define DC_WIN_SET_PARAMS 0x70d
#define CLAMP_BEFORE_BLEND (1 << 15)
#define DEGAMMA_NONE (0 << 13)
#define DEGAMMA_SRGB (1 << 13)
#define DEGAMMA_YUV8_10 (2 << 13)
#define DEGAMMA_YUV12 (3 << 13)
#define INPUT_RANGE_BYPASS (0 << 10)
#define INPUT_RANGE_LIMITED (1 << 10)
#define INPUT_RANGE_FULL (2 << 10)
#define COLOR_SPACE_RGB (0 << 8)
#define COLOR_SPACE_YUV_601 (1 << 8)
#define COLOR_SPACE_YUV_709 (2 << 8)
#define COLOR_SPACE_YUV_2020 (3 << 8)
#define DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER 0x70e
#define HORIZONTAL_TAPS_2 (1 << 3)
#define HORIZONTAL_TAPS_5 (4 << 3)
#define VERTICAL_TAPS_2 (1 << 0)
#define VERTICAL_TAPS_5 (4 << 0)
#define DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE 0x711
#define INPUT_SCALER_USE422 (1 << 2)
#define INPUT_SCALER_VBYPASS (1 << 1)
#define INPUT_SCALER_HBYPASS (1 << 0)
#define DC_WIN_BLEND_LAYER_CONTROL 0x716
#define COLOR_KEY_NONE (0 << 25)
#define COLOR_KEY_SRC (1 << 25)
#define COLOR_KEY_DST (2 << 25)
#define BLEND_BYPASS (1 << 24)
#define K2(x) (((x) & 0xff) << 16)
#define K1(x) (((x) & 0xff) << 8)
#define WINDOW_LAYER_DEPTH(x) (((x) & 0xff) << 0)
#define DC_WIN_BLEND_MATCH_SELECT 0x717
#define BLEND_FACTOR_DST_ALPHA_ZERO (0 << 12)
#define BLEND_FACTOR_DST_ALPHA_ONE (1 << 12)
#define BLEND_FACTOR_DST_ALPHA_NEG_K1_TIMES_SRC (2 << 12)
#define BLEND_FACTOR_DST_ALPHA_K2 (3 << 12)
#define BLEND_FACTOR_SRC_ALPHA_ZERO (0 << 8)
#define BLEND_FACTOR_SRC_ALPHA_K1 (1 << 8)
#define BLEND_FACTOR_SRC_ALPHA_K2 (2 << 8)
#define BLEND_FACTOR_SRC_ALPHA_NEG_K1_TIMES_DST (3 << 8)
#define BLEND_FACTOR_DST_COLOR_ZERO (0 << 4)
#define BLEND_FACTOR_DST_COLOR_ONE (1 << 4)
#define BLEND_FACTOR_DST_COLOR_K1 (2 << 4)
#define BLEND_FACTOR_DST_COLOR_K2 (3 << 4)
#define BLEND_FACTOR_DST_COLOR_K1_TIMES_DST (4 << 4)
#define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_DST (5 << 4)
#define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC (6 << 4)
#define BLEND_FACTOR_DST_COLOR_NEG_K1 (7 << 4)
#define BLEND_FACTOR_SRC_COLOR_ZERO (0 << 0)
#define BLEND_FACTOR_SRC_COLOR_ONE (1 << 0)
#define BLEND_FACTOR_SRC_COLOR_K1 (2 << 0)
#define BLEND_FACTOR_SRC_COLOR_K1_TIMES_DST (3 << 0)
#define BLEND_FACTOR_SRC_COLOR_NEG_K1_TIMES_DST (4 << 0)
#define BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC (5 << 0)
#define DC_WIN_BLEND_NOMATCH_SELECT 0x718
#define DC_WIN_PRECOMP_WGRP_PARAMS 0x724
#define SWAP_UV (1 << 0)
#define DC_WIN_WINDOW_SET_CONTROL 0x730
#define CONTROL_CSC_ENABLE (1 << 5)
#define DC_WINBUF_CROPPED_POINT 0x806
#define OFFSET_Y(x) (((x) & 0xffff) << 16)
#define OFFSET_X(x) (((x) & 0xffff) << 0)
#endif /* TEGRA_DC_H */

130
drivers/gpu/drm/tegra/dpaux.c
View File

@ -15,6 +15,7 @@
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pm_runtime.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/regulator/consumer.h>
@ -321,6 +322,9 @@ static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)
case DPAUX_PADCTL_FUNC_I2C:
value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |
DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
DPAUX_HYBRID_PADCTL_MODE_I2C;
break;
@ -467,52 +471,37 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
return PTR_ERR(dpaux->clk);
}
err = clk_prepare_enable(dpaux->clk);
if (err < 0) {
dev_err(&pdev->dev, "failed to enable module clock: %d\n",
err);
return err;
}
if (dpaux->rst)
reset_control_deassert(dpaux->rst);
dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
if (IS_ERR(dpaux->clk_parent)) {
dev_err(&pdev->dev, "failed to get parent clock: %ld\n",
PTR_ERR(dpaux->clk_parent));
err = PTR_ERR(dpaux->clk_parent);
goto assert_reset;
}
err = clk_prepare_enable(dpaux->clk_parent);
if (err < 0) {
dev_err(&pdev->dev, "failed to enable parent clock: %d\n",
err);
goto assert_reset;
return PTR_ERR(dpaux->clk_parent);
}
err = clk_set_rate(dpaux->clk_parent, 270000000);
if (err < 0) {
dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
err);
goto disable_parent_clk;
return err;
}
dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd");
if (IS_ERR(dpaux->vdd)) {
dev_err(&pdev->dev, "failed to get VDD supply: %ld\n",
PTR_ERR(dpaux->vdd));
err = PTR_ERR(dpaux->vdd);
goto disable_parent_clk;
return PTR_ERR(dpaux->vdd);
}
platform_set_drvdata(pdev, dpaux);
pm_runtime_enable(&pdev->dev);
pm_runtime_get_sync(&pdev->dev);
err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
dev_name(dpaux->dev), dpaux);
if (err < 0) {
dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
dpaux->irq, err);
goto disable_parent_clk;
return err;
}
disable_irq(dpaux->irq);
@ -522,7 +511,7 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
err = drm_dp_aux_register(&dpaux->aux);
if (err < 0)
goto disable_parent_clk;
return err;
/*
* Assume that by default the DPAUX/I2C pads will be used for HDMI,
@ -560,47 +549,97 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
list_add_tail(&dpaux->list, &dpaux_list);
mutex_unlock(&dpaux_lock);
platform_set_drvdata(pdev, dpaux);
return 0;
disable_parent_clk:
clk_disable_unprepare(dpaux->clk_parent);
assert_reset:
if (dpaux->rst)
reset_control_assert(dpaux->rst);
clk_disable_unprepare(dpaux->clk);
return err;
}
static int tegra_dpaux_remove(struct platform_device *pdev)
{
struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
cancel_work_sync(&dpaux->work);
/* make sure pads are powered down when not in use */
tegra_dpaux_pad_power_down(dpaux);
pm_runtime_put(&pdev->dev);
pm_runtime_disable(&pdev->dev);
drm_dp_aux_unregister(&dpaux->aux);
mutex_lock(&dpaux_lock);
list_del(&dpaux->list);
mutex_unlock(&dpaux_lock);
cancel_work_sync(&dpaux->work);
clk_disable_unprepare(dpaux->clk_parent);
if (dpaux->rst)
reset_control_assert(dpaux->rst);
clk_disable_unprepare(dpaux->clk);
return 0;
}
#ifdef CONFIG_PM
static int tegra_dpaux_suspend(struct device *dev)
{
struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
int err = 0;
if (dpaux->rst) {
err = reset_control_assert(dpaux->rst);
if (err < 0) {
dev_err(dev, "failed to assert reset: %d\n", err);
return err;
}
}
usleep_range(1000, 2000);
clk_disable_unprepare(dpaux->clk_parent);
clk_disable_unprepare(dpaux->clk);
return err;
}
static int tegra_dpaux_resume(struct device *dev)
{
struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
int err;
err = clk_prepare_enable(dpaux->clk);
if (err < 0) {
dev_err(dev, "failed to enable clock: %d\n", err);
return err;
}
err = clk_prepare_enable(dpaux->clk_parent);
if (err < 0) {
dev_err(dev, "failed to enable parent clock: %d\n", err);
goto disable_clk;
}
usleep_range(1000, 2000);
if (dpaux->rst) {
err = reset_control_deassert(dpaux->rst);
if (err < 0) {
dev_err(dev, "failed to deassert reset: %d\n", err);
goto disable_parent;
}
usleep_range(1000, 2000);
}
return 0;
disable_parent:
clk_disable_unprepare(dpaux->clk_parent);
disable_clk:
clk_disable_unprepare(dpaux->clk);
return err;
}
#endif
static const struct dev_pm_ops tegra_dpaux_pm_ops = {
SET_RUNTIME_PM_OPS(tegra_dpaux_suspend, tegra_dpaux_resume, NULL)
};
static const struct of_device_id tegra_dpaux_of_match[] = {
{ .compatible = "nvidia,tegra186-dpaux", },
{ .compatible = "nvidia,tegra210-dpaux", },
{ .compatible = "nvidia,tegra124-dpaux", },
{ },
@ -611,6 +650,7 @@ struct platform_driver tegra_dpaux_driver = {
.driver = {
.name = "tegra-dpaux",
.of_match_table = tegra_dpaux_of_match,
.pm = &tegra_dpaux_pm_ops,
},
.probe = tegra_dpaux_probe,
.remove = tegra_dpaux_remove,

176
drivers/gpu/drm/tegra/drm.c
View File

@ -33,97 +33,91 @@ struct tegra_drm_file {
struct mutex lock;
};
static void tegra_atomic_schedule(struct tegra_drm *tegra,
struct drm_atomic_state *state)
static int tegra_atomic_check(struct drm_device *drm,
struct drm_atomic_state *state)
{
tegra->commit.state = state;
schedule_work(&tegra->commit.work);
}
static void tegra_atomic_complete(struct tegra_drm *tegra,
struct drm_atomic_state *state)
{
struct drm_device *drm = tegra->drm;
/*
* Everything below can be run asynchronously without the need to grab
* any modeset locks at all under one condition: It must be guaranteed
* that the asynchronous work has either been cancelled (if the driver
* supports it, which at least requires that the framebuffers get
* cleaned up with drm_atomic_helper_cleanup_planes()) or completed
* before the new state gets committed on the software side with
* drm_atomic_helper_swap_state().
*
* This scheme allows new atomic state updates to be prepared and
* checked in parallel to the asynchronous completion of the previous
* update. Which is important since compositors need to figure out the
* composition of the next frame right after having submitted the
* current layout.
*/
drm_atomic_helper_commit_modeset_disables(drm, state);
drm_atomic_helper_commit_modeset_enables(drm, state);
drm_atomic_helper_commit_planes(drm, state,
DRM_PLANE_COMMIT_ACTIVE_ONLY);
drm_atomic_helper_wait_for_vblanks(drm, state);
drm_atomic_helper_cleanup_planes(drm, state);
drm_atomic_state_put(state);
}
static void tegra_atomic_work(struct work_struct *work)
{
struct tegra_drm *tegra = container_of(work, struct tegra_drm,
commit.work);
tegra_atomic_complete(tegra, tegra->commit.state);
}
static int tegra_atomic_commit(struct drm_device *drm,
struct drm_atomic_state *state, bool nonblock)
{
struct tegra_drm *tegra = drm->dev_private;
int err;
err = drm_atomic_helper_prepare_planes(drm, state);
if (err)
err = drm_atomic_helper_check_modeset(drm, state);
if (err < 0)
return err;
/* serialize outstanding nonblocking commits */
mutex_lock(&tegra->commit.lock);
flush_work(&tegra->commit.work);
/*
* This is the point of no return - everything below never fails except
* when the hw goes bonghits. Which means we can commit the new state on
* the software side now.
*/
err = drm_atomic_helper_swap_state(state, true);
if (err) {
mutex_unlock(&tegra->commit.lock);
drm_atomic_helper_cleanup_planes(drm, state);
err = drm_atomic_normalize_zpos(drm, state);
if (err < 0)
return err;
}
drm_atomic_state_get(state);
if (nonblock)
tegra_atomic_schedule(tegra, state);
else
tegra_atomic_complete(tegra, state);
err = drm_atomic_helper_check_planes(drm, state);
if (err < 0)
return err;
if (state->legacy_cursor_update)
state->async_update = !drm_atomic_helper_async_check(drm, state);
mutex_unlock(&tegra->commit.lock);
return 0;
}
static const struct drm_mode_config_funcs tegra_drm_mode_funcs = {
static struct drm_atomic_state *
tegra_atomic_state_alloc(struct drm_device *drm)
{
struct tegra_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state || drm_atomic_state_init(drm, &state->base) < 0) {
kfree(state);
return NULL;
}
return &state->base;
}
static void tegra_atomic_state_clear(struct drm_atomic_state *state)
{
struct tegra_atomic_state *tegra = to_tegra_atomic_state(state);
drm_atomic_state_default_clear(state);
tegra->clk_disp = NULL;
tegra->dc = NULL;
tegra->rate = 0;
}
static void tegra_atomic_state_free(struct drm_atomic_state *state)
{
drm_atomic_state_default_release(state);
kfree(state);
}
static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
.fb_create = tegra_fb_create,
#ifdef CONFIG_DRM_FBDEV_EMULATION
.output_poll_changed = drm_fb_helper_output_poll_changed,
#endif
.atomic_check = drm_atomic_helper_check,
.atomic_commit = tegra_atomic_commit,
.atomic_check = tegra_atomic_check,
.atomic_commit = drm_atomic_helper_commit,
.atomic_state_alloc = tegra_atomic_state_alloc,
.atomic_state_clear = tegra_atomic_state_clear,
.atomic_state_free = tegra_atomic_state_free,
};
static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
{
struct drm_device *drm = old_state->dev;
struct tegra_drm *tegra = drm->dev_private;
if (tegra->hub) {
drm_atomic_helper_commit_modeset_disables(drm, old_state);
tegra_display_hub_atomic_commit(drm, old_state);
drm_atomic_helper_commit_planes(drm, old_state, 0);
drm_atomic_helper_commit_modeset_enables(drm, old_state);
drm_atomic_helper_commit_hw_done(old_state);
drm_atomic_helper_wait_for_vblanks(drm, old_state);
drm_atomic_helper_cleanup_planes(drm, old_state);
} else {
drm_atomic_helper_commit_tail_rpm(old_state);
}
}
static const struct drm_mode_config_helper_funcs
tegra_drm_mode_config_helpers = {
.atomic_commit_tail = tegra_atomic_commit_tail,
};
static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
@ -172,9 +166,6 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
mutex_init(&tegra->clients_lock);
INIT_LIST_HEAD(&tegra->clients);
mutex_init(&tegra->commit.lock);
INIT_WORK(&tegra->commit.work, tegra_atomic_work);
drm->dev_private = tegra;
tegra->drm = drm;
@ -188,7 +179,8 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
drm->mode_config.allow_fb_modifiers = true;
drm->mode_config.funcs = &tegra_drm_mode_funcs;
drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
err = tegra_drm_fb_prepare(drm);
if (err < 0)
@ -200,6 +192,12 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
if (err < 0)
goto fbdev;
if (tegra->hub) {
err = tegra_display_hub_prepare(tegra->hub);
if (err < 0)
goto device;
}
/*
* We don't use the drm_irq_install() helpers provided by the DRM
* core, so we need to set this manually in order to allow the
@ -212,16 +210,19 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
err = drm_vblank_init(drm, drm->mode_config.num_crtc);
if (err < 0)
goto device;
goto hub;
drm_mode_config_reset(drm);
err = tegra_drm_fb_init(drm);
if (err < 0)
goto device;
goto hub;
return 0;
hub:
if (tegra->hub)
tegra_display_hub_cleanup(tegra->hub);
device:
host1x_device_exit(device);
fbdev:
@ -651,7 +652,8 @@ static int tegra_syncpt_wait(struct drm_device *drm, void *data,
if (!sp)
return -EINVAL;
return host1x_syncpt_wait(sp, args->thresh, args->timeout,
return host1x_syncpt_wait(sp, args->thresh,
msecs_to_jiffies(args->timeout),
&args->value);
}
@ -1139,8 +1141,7 @@ int tegra_drm_unregister_client(struct tegra_drm *tegra,
return 0;
}
void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size,
dma_addr_t *dma)
void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
{
struct iova *alloc;
void *virt;
@ -1308,6 +1309,10 @@ static const struct of_device_id host1x_drm_subdevs[] = {
{ .compatible = "nvidia,tegra210-sor", },
{ .compatible = "nvidia,tegra210-sor1", },
{ .compatible = "nvidia,tegra210-vic", },
{ .compatible = "nvidia,tegra186-display", },
{ .compatible = "nvidia,tegra186-dc", },
{ .compatible = "nvidia,tegra186-sor", },
{ .compatible = "nvidia,tegra186-sor1", },
{ .compatible = "nvidia,tegra186-vic", },
{ /* sentinel */ }
};
@ -1323,6 +1328,7 @@ static struct host1x_driver host1x_drm_driver = {
};
static struct platform_driver * const drivers[] = {
&tegra_display_hub_driver,
&tegra_dc_driver,
&tegra_hdmi_driver,
&tegra_dsi_driver,

26
drivers/gpu/drm/tegra/drm.h
View File

@ -16,6 +16,7 @@
#include <linux/of_gpio.h>
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
#include <drm/drm_encoder.h>
@ -23,6 +24,7 @@
#include <drm/drm_fixed.h>
#include "gem.h"
#include "hub.h"
#include "trace.h"
struct reset_control;
@ -40,10 +42,25 @@ struct tegra_fbdev {
};
#endif
struct tegra_atomic_state {
struct drm_atomic_state base;
struct clk *clk_disp;
struct tegra_dc *dc;
unsigned long rate;
};
static inline struct tegra_atomic_state *
to_tegra_atomic_state(struct drm_atomic_state *state)
{
return container_of(state, struct tegra_atomic_state, base);
}
struct tegra_drm {
struct drm_device *drm;
struct iommu_domain *domain;
struct iommu_group *group;
struct mutex mm_lock;
struct drm_mm mm;
@ -62,11 +79,7 @@ struct tegra_drm {
unsigned int pitch_align;
struct {
struct drm_atomic_state *state;
struct work_struct work;
struct mutex lock;
} commit;
struct tegra_display_hub *hub;
struct drm_atomic_state *state;
};
@ -152,6 +165,8 @@ int tegra_output_probe(struct tegra_output *output);
void tegra_output_remove(struct tegra_output *output);
int tegra_output_init(struct drm_device *drm, struct tegra_output *output);
void tegra_output_exit(struct tegra_output *output);
void tegra_output_find_possible_crtcs(struct tegra_output *output,
struct drm_device *drm);
int tegra_output_connector_get_modes(struct drm_connector *connector);
enum drm_connector_status
@ -189,6 +204,7 @@ void tegra_drm_fb_exit(struct drm_device *drm);
void tegra_drm_fb_suspend(struct drm_device *drm);
void tegra_drm_fb_resume(struct drm_device *drm);
extern struct platform_driver tegra_display_hub_driver;
extern struct platform_driver tegra_dc_driver;
extern struct platform_driver tegra_hdmi_driver;
extern struct platform_driver tegra_dsi_driver;

226
drivers/gpu/drm/tegra/dsi.c
View File

@ -65,8 +65,6 @@ struct tegra_dsi {
struct clk *clk;
struct drm_info_list *debugfs_files;
struct drm_minor *minor;
struct dentry *debugfs;
unsigned long flags;
enum mipi_dsi_pixel_format format;
@ -122,12 +120,89 @@ static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
writel(value, dsi->regs + (offset << 2));
}
#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
static const struct debugfs_reg32 tegra_dsi_regs[] = {
DEBUGFS_REG32(DSI_INCR_SYNCPT),
DEBUGFS_REG32(DSI_INCR_SYNCPT_CONTROL),
DEBUGFS_REG32(DSI_INCR_SYNCPT_ERROR),
DEBUGFS_REG32(DSI_CTXSW),
DEBUGFS_REG32(DSI_RD_DATA),
DEBUGFS_REG32(DSI_WR_DATA),
DEBUGFS_REG32(DSI_POWER_CONTROL),
DEBUGFS_REG32(DSI_INT_ENABLE),
DEBUGFS_REG32(DSI_INT_STATUS),
DEBUGFS_REG32(DSI_INT_MASK),
DEBUGFS_REG32(DSI_HOST_CONTROL),
DEBUGFS_REG32(DSI_CONTROL),
DEBUGFS_REG32(DSI_SOL_DELAY),
DEBUGFS_REG32(DSI_MAX_THRESHOLD),
DEBUGFS_REG32(DSI_TRIGGER),
DEBUGFS_REG32(DSI_TX_CRC),
DEBUGFS_REG32(DSI_STATUS),
DEBUGFS_REG32(DSI_INIT_SEQ_CONTROL),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_0),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_1),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_2),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_3),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_4),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_5),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_6),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_7),
DEBUGFS_REG32(DSI_PKT_SEQ_0_LO),
DEBUGFS_REG32(DSI_PKT_SEQ_0_HI),
DEBUGFS_REG32(DSI_PKT_SEQ_1_LO),
DEBUGFS_REG32(DSI_PKT_SEQ_1_HI),
DEBUGFS_REG32(DSI_PKT_SEQ_2_LO),
DEBUGFS_REG32(DSI_PKT_SEQ_2_HI),
DEBUGFS_REG32(DSI_PKT_SEQ_3_LO),
DEBUGFS_REG32(DSI_PKT_SEQ_3_HI),
DEBUGFS_REG32(DSI_PKT_SEQ_4_LO),
DEBUGFS_REG32(DSI_PKT_SEQ_4_HI),
DEBUGFS_REG32(DSI_PKT_SEQ_5_LO),
DEBUGFS_REG32(DSI_PKT_SEQ_5_HI),
DEBUGFS_REG32(DSI_DCS_CMDS),
DEBUGFS_REG32(DSI_PKT_LEN_0_1),
DEBUGFS_REG32(DSI_PKT_LEN_2_3),
DEBUGFS_REG32(DSI_PKT_LEN_4_5),
DEBUGFS_REG32(DSI_PKT_LEN_6_7),
DEBUGFS_REG32(DSI_PHY_TIMING_0),
DEBUGFS_REG32(DSI_PHY_TIMING_1),
DEBUGFS_REG32(DSI_PHY_TIMING_2),
DEBUGFS_REG32(DSI_BTA_TIMING),
DEBUGFS_REG32(DSI_TIMEOUT_0),
DEBUGFS_REG32(DSI_TIMEOUT_1),
DEBUGFS_REG32(DSI_TO_TALLY),
DEBUGFS_REG32(DSI_PAD_CONTROL_0),
DEBUGFS_REG32(DSI_PAD_CONTROL_CD),
DEBUGFS_REG32(DSI_PAD_CD_STATUS),
DEBUGFS_REG32(DSI_VIDEO_MODE_CONTROL),
DEBUGFS_REG32(DSI_PAD_CONTROL_1),
DEBUGFS_REG32(DSI_PAD_CONTROL_2),
DEBUGFS_REG32(DSI_PAD_CONTROL_3),
DEBUGFS_REG32(DSI_PAD_CONTROL_4),
DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL),
DEBUGFS_REG32(DSI_GANGED_MODE_START),
DEBUGFS_REG32(DSI_GANGED_MODE_SIZE),
DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT),
DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15),
};
static int tegra_dsi_show_regs(struct seq_file *s, void *data)
{
struct drm_info_node *node = s->private;
struct tegra_dsi *dsi = node->info_ent->data;
struct drm_crtc *crtc = dsi->output.encoder.crtc;
struct drm_device *drm = node->minor->dev;
unsigned int i;
int err = 0;
drm_modeset_lock_all(drm);
@ -137,93 +212,12 @@ static int tegra_dsi_show_regs(struct seq_file *s, void *data)
goto unlock;
}
#define DUMP_REG(name) \
seq_printf(s, "%-32s %#05x %08x\n", #name, name, \
tegra_dsi_readl(dsi, name))
for (i = 0; i < ARRAY_SIZE(tegra_dsi_regs); i++) {
unsigned int offset = tegra_dsi_regs[i].offset;
DUMP_REG(DSI_INCR_SYNCPT);
DUMP_REG(DSI_INCR_SYNCPT_CONTROL);
DUMP_REG(DSI_INCR_SYNCPT_ERROR);
DUMP_REG(DSI_CTXSW);
DUMP_REG(DSI_RD_DATA);
DUMP_REG(DSI_WR_DATA);
DUMP_REG(DSI_POWER_CONTROL);
DUMP_REG(DSI_INT_ENABLE);
DUMP_REG(DSI_INT_STATUS);
DUMP_REG(DSI_INT_MASK);
DUMP_REG(DSI_HOST_CONTROL);
DUMP_REG(DSI_CONTROL);
DUMP_REG(DSI_SOL_DELAY);
DUMP_REG(DSI_MAX_THRESHOLD);
DUMP_REG(DSI_TRIGGER);
DUMP_REG(DSI_TX_CRC);
DUMP_REG(DSI_STATUS);
DUMP_REG(DSI_INIT_SEQ_CONTROL);
DUMP_REG(DSI_INIT_SEQ_DATA_0);
DUMP_REG(DSI_INIT_SEQ_DATA_1);
DUMP_REG(DSI_INIT_SEQ_DATA_2);
DUMP_REG(DSI_INIT_SEQ_DATA_3);
DUMP_REG(DSI_INIT_SEQ_DATA_4);
DUMP_REG(DSI_INIT_SEQ_DATA_5);
DUMP_REG(DSI_INIT_SEQ_DATA_6);
DUMP_REG(DSI_INIT_SEQ_DATA_7);
DUMP_REG(DSI_PKT_SEQ_0_LO);
DUMP_REG(DSI_PKT_SEQ_0_HI);
DUMP_REG(DSI_PKT_SEQ_1_LO);
DUMP_REG(DSI_PKT_SEQ_1_HI);
DUMP_REG(DSI_PKT_SEQ_2_LO);
DUMP_REG(DSI_PKT_SEQ_2_HI);
DUMP_REG(DSI_PKT_SEQ_3_LO);
DUMP_REG(DSI_PKT_SEQ_3_HI);
DUMP_REG(DSI_PKT_SEQ_4_LO);
DUMP_REG(DSI_PKT_SEQ_4_HI);
DUMP_REG(DSI_PKT_SEQ_5_LO);
DUMP_REG(DSI_PKT_SEQ_5_HI);
DUMP_REG(DSI_DCS_CMDS);
DUMP_REG(DSI_PKT_LEN_0_1);
DUMP_REG(DSI_PKT_LEN_2_3);
DUMP_REG(DSI_PKT_LEN_4_5);
DUMP_REG(DSI_PKT_LEN_6_7);
DUMP_REG(DSI_PHY_TIMING_0);
DUMP_REG(DSI_PHY_TIMING_1);
DUMP_REG(DSI_PHY_TIMING_2);
DUMP_REG(DSI_BTA_TIMING);
DUMP_REG(DSI_TIMEOUT_0);
DUMP_REG(DSI_TIMEOUT_1);
DUMP_REG(DSI_TO_TALLY);
DUMP_REG(DSI_PAD_CONTROL_0);
DUMP_REG(DSI_PAD_CONTROL_CD);
DUMP_REG(DSI_PAD_CD_STATUS);
DUMP_REG(DSI_VIDEO_MODE_CONTROL);
DUMP_REG(DSI_PAD_CONTROL_1);
DUMP_REG(DSI_PAD_CONTROL_2);
DUMP_REG(DSI_PAD_CONTROL_3);
DUMP_REG(DSI_PAD_CONTROL_4);
DUMP_REG(DSI_GANGED_MODE_CONTROL);
DUMP_REG(DSI_GANGED_MODE_START);
DUMP_REG(DSI_GANGED_MODE_SIZE);
DUMP_REG(DSI_RAW_DATA_BYTE_COUNT);
DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL);
DUMP_REG(DSI_INIT_SEQ_DATA_8);
DUMP_REG(DSI_INIT_SEQ_DATA_9);
DUMP_REG(DSI_INIT_SEQ_DATA_10);
DUMP_REG(DSI_INIT_SEQ_DATA_11);
DUMP_REG(DSI_INIT_SEQ_DATA_12);
DUMP_REG(DSI_INIT_SEQ_DATA_13);
DUMP_REG(DSI_INIT_SEQ_DATA_14);
DUMP_REG(DSI_INIT_SEQ_DATA_15);
#undef DUMP_REG
seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs[i].name,
offset, tegra_dsi_readl(dsi, offset));
}
unlock:
drm_modeset_unlock_all(drm);
@ -234,58 +228,46 @@ static struct drm_info_list debugfs_files[] = {
{ "regs", tegra_dsi_show_regs, 0, NULL },
};
static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi,
struct drm_minor *minor)
static int tegra_dsi_late_register(struct drm_connector *connector)
{
const char *name = dev_name(dsi->dev);
unsigned int i;
struct tegra_output *output = connector_to_output(connector);
unsigned int i, count = ARRAY_SIZE(debugfs_files);
struct drm_minor *minor = connector->dev->primary;
struct dentry *root = connector->debugfs_entry;
struct tegra_dsi *dsi = to_dsi(output);
int err;
dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root);
if (!dsi->debugfs)
return -ENOMEM;
dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
GFP_KERNEL);
if (!dsi->debugfs_files) {
err = -ENOMEM;
goto remove;
}
if (!dsi->debugfs_files)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
for (i = 0; i < count; i++)
dsi->debugfs_files[i].data = dsi;
err = drm_debugfs_create_files(dsi->debugfs_files,
ARRAY_SIZE(debugfs_files),
dsi->debugfs, minor);
err = drm_debugfs_create_files(dsi->debugfs_files, count, root, minor);
if (err < 0)
goto free;
dsi->minor = minor;
return 0;
free:
kfree(dsi->debugfs_files);
dsi->debugfs_files = NULL;
remove:
debugfs_remove(dsi->debugfs);
dsi->debugfs = NULL;
return err;
}
static void tegra_dsi_debugfs_exit(struct tegra_dsi *dsi)
static void tegra_dsi_early_unregister(struct drm_connector *connector)
{
drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files),
dsi->minor);
dsi->minor = NULL;
struct tegra_output *output = connector_to_output(connector);
unsigned int count = ARRAY_SIZE(debugfs_files);
struct tegra_dsi *dsi = to_dsi(output);
drm_debugfs_remove_files(dsi->debugfs_files, count,
connector->dev->primary);
kfree(dsi->debugfs_files);
dsi->debugfs_files = NULL;
debugfs_remove(dsi->debugfs);
dsi->debugfs = NULL;
}
#define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
@ -827,6 +809,8 @@ static const struct drm_connector_funcs tegra_dsi_connector_funcs = {
.destroy = tegra_output_connector_destroy,
.atomic_duplicate_state = tegra_dsi_connector_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
.late_register = tegra_dsi_late_register,
.early_unregister = tegra_dsi_early_unregister,
};
static enum drm_mode_status
@ -1080,12 +1064,6 @@ static int tegra_dsi_init(struct host1x_client *client)
dsi->output.encoder.possible_crtcs = 0x3;
}
if (IS_ENABLED(CONFIG_DEBUG_FS)) {
err = tegra_dsi_debugfs_init(dsi, drm->primary);
if (err < 0)
dev_err(dsi->dev, "debugfs setup failed: %d\n", err);
}
return 0;
}
@ -1094,10 +1072,6 @@ static int tegra_dsi_exit(struct host1x_client *client)
struct tegra_dsi *dsi = host1x_client_to_dsi(client);
tegra_output_exit(&dsi->output);
if (IS_ENABLED(CONFIG_DEBUG_FS))
tegra_dsi_debugfs_exit(dsi);
regulator_disable(dsi->vdd);
return 0;

36
drivers/gpu/drm/tegra/fb.c
View File

@ -54,17 +54,40 @@ int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer,
struct tegra_fb *fb = to_tegra_fb(framebuffer);
uint64_t modifier = fb->base.modifier;
switch (fourcc_mod_tegra_mod(modifier)) {
case NV_FORMAT_MOD_TEGRA_TILED:
switch (modifier) {
case DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED:
tiling->mode = TEGRA_BO_TILING_MODE_TILED;
tiling->value = 0;
break;
case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(0):
case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0):
tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
tiling->value = fourcc_mod_tegra_param(modifier);
if (tiling->value > 5)
return -EINVAL;
tiling->value = 0;
break;
case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1):
tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
tiling->value = 1;
break;
case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2):
tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
tiling->value = 2;
break;
case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3):
tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
tiling->value = 3;
break;
case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4):
tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
tiling->value = 4;
break;
case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5):
tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
tiling->value = 5;
break;
default:
@ -230,6 +253,7 @@ static int tegra_fbdev_probe(struct drm_fb_helper *helper,
cmd.height = sizes->surface_height;
cmd.pitches[0] = round_up(sizes->surface_width * bytes_per_pixel,
tegra->pitch_align);
cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
sizes->surface_depth);

15
drivers/gpu/drm/tegra/gem.c
View File

@ -114,7 +114,7 @@ static const struct host1x_bo_ops tegra_bo_ops = {
static int tegra_bo_iommu_map(struct tegra_drm *tegra, struct tegra_bo *bo)
{
int prot = IOMMU_READ | IOMMU_WRITE;
ssize_t err;
int err;
if (bo->mm)
return -EBUSY;
@ -128,22 +128,21 @@ static int tegra_bo_iommu_map(struct tegra_drm *tegra, struct tegra_bo *bo)
err = drm_mm_insert_node_generic(&tegra->mm,
bo->mm, bo->gem.size, PAGE_SIZE, 0, 0);
if (err < 0) {
dev_err(tegra->drm->dev, "out of I/O virtual memory: %zd\n",
dev_err(tegra->drm->dev, "out of I/O virtual memory: %d\n",
err);
goto unlock;
}
bo->paddr = bo->mm->start;
err = iommu_map_sg(tegra->domain, bo->paddr, bo->sgt->sgl,
bo->sgt->nents, prot);
if (err < 0) {
dev_err(tegra->drm->dev, "failed to map buffer: %zd\n", err);
bo->size = iommu_map_sg(tegra->domain, bo->paddr, bo->sgt->sgl,
bo->sgt->nents, prot);
if (!bo->size) {
dev_err(tegra->drm->dev, "failed to map buffer\n");
err = -ENOMEM;
goto remove;
}
bo->size = err;
mutex_unlock(&tegra->mm_lock);
return 0;

504
drivers/gpu/drm/tegra/hdmi.c
View File

@ -79,8 +79,6 @@ struct tegra_hdmi {
bool dvi;
struct drm_info_list *debugfs_files;
struct drm_minor *minor;
struct dentry *debugfs;
};
static inline struct tegra_hdmi *
@ -910,6 +908,249 @@ tegra_hdmi_connector_detect(struct drm_connector *connector, bool force)
return status;
}
#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
static const struct debugfs_reg32 tegra_hdmi_regs[] = {
DEBUGFS_REG32(HDMI_CTXSW),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2),
DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB),
DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB),
DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB),
DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB),
DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB),
DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB),
DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB),
DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB),
DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB),
DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB),
DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB),
DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB),
DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL),
DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE),
DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB),
DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB),
DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB),
DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2),
DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1),
DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI),
DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB),
DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2),
DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT),
DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0),
DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1),
DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2),
DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)),
DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)),
DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)),
DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)),
DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)),
DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)),
DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)),
DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH),
DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD),
DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0),
DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N),
DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK),
DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL),
DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL),
DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH),
DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT),
DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL),
DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0),
DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1),
DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2),
DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0),
DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1),
DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2),
DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3),
DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG),
DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE),
DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS),
DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK),
DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE),
DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT),
};
static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
{
struct drm_info_node *node = s->private;
struct tegra_hdmi *hdmi = node->info_ent->data;
struct drm_crtc *crtc = hdmi->output.encoder.crtc;
struct drm_device *drm = node->minor->dev;
unsigned int i;
int err = 0;
drm_modeset_lock_all(drm);
if (!crtc || !crtc->state->active) {
err = -EBUSY;
goto unlock;
}
for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) {
unsigned int offset = tegra_hdmi_regs[i].offset;
seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name,
offset, tegra_hdmi_readl(hdmi, offset));
}
unlock:
drm_modeset_unlock_all(drm);
return err;
}
static struct drm_info_list debugfs_files[] = {
{ "regs", tegra_hdmi_show_regs, 0, NULL },
};
static int tegra_hdmi_late_register(struct drm_connector *connector)
{
struct tegra_output *output = connector_to_output(connector);
unsigned int i, count = ARRAY_SIZE(debugfs_files);
struct drm_minor *minor = connector->dev->primary;
struct dentry *root = connector->debugfs_entry;
struct tegra_hdmi *hdmi = to_hdmi(output);
int err;
hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
GFP_KERNEL);
if (!hdmi->debugfs_files)
return -ENOMEM;
for (i = 0; i < count; i++)
hdmi->debugfs_files[i].data = hdmi;
err = drm_debugfs_create_files(hdmi->debugfs_files, count, root, minor);
if (err < 0)
goto free;
return 0;
free:
kfree(hdmi->debugfs_files);
hdmi->debugfs_files = NULL;
return err;
}
static void tegra_hdmi_early_unregister(struct drm_connector *connector)
{
struct tegra_output *output = connector_to_output(connector);
struct drm_minor *minor = connector->dev->primary;
unsigned int count = ARRAY_SIZE(debugfs_files);
struct tegra_hdmi *hdmi = to_hdmi(output);
drm_debugfs_remove_files(hdmi->debugfs_files, count, minor);
kfree(hdmi->debugfs_files);
hdmi->debugfs_files = NULL;
}
static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
.reset = drm_atomic_helper_connector_reset,
.detect = tegra_hdmi_connector_detect,
@ -917,6 +1158,8 @@ static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
.destroy = tegra_output_connector_destroy,
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
.late_register = tegra_hdmi_late_register,
.early_unregister = tegra_hdmi_early_unregister,
};
static enum drm_mode_status
@ -1225,254 +1468,6 @@ static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = {
.atomic_check = tegra_hdmi_encoder_atomic_check,
};
static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
{
struct drm_info_node *node = s->private;
struct tegra_hdmi *hdmi = node->info_ent->data;
struct drm_crtc *crtc = hdmi->output.encoder.crtc;
struct drm_device *drm = node->minor->dev;
int err = 0;
drm_modeset_lock_all(drm);
if (!crtc || !crtc->state->active) {
err = -EBUSY;
goto unlock;
}
#define DUMP_REG(name) \
seq_printf(s, "%-56s %#05x %08x\n", #name, name, \
tegra_hdmi_readl(hdmi, name))
DUMP_REG(HDMI_CTXSW);
DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL);
DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0));
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1));
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2));
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3));
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4));
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5));
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6));
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7));
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8));
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9));
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10));
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11));
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12));
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13));
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14));
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15));
DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
DUMP_REG(HDMI_NV_PDISP_SCRATCH);
DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1);
DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
DUMP_REG(HDMI_NV_PDISP_INT_STATUS);
DUMP_REG(HDMI_NV_PDISP_INT_MASK);
DUMP_REG(HDMI_NV_PDISP_INT_ENABLE);
DUMP_REG(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
#undef DUMP_REG
unlock:
drm_modeset_unlock_all(drm);
return err;
}
static struct drm_info_list debugfs_files[] = {
{ "regs", tegra_hdmi_show_regs, 0, NULL },
};
static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi,
struct drm_minor *minor)
{
unsigned int i;
int err;
hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root);
if (!hdmi->debugfs)
return -ENOMEM;
hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
GFP_KERNEL);
if (!hdmi->debugfs_files) {
err = -ENOMEM;
goto remove;
}
for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
hdmi->debugfs_files[i].data = hdmi;
err = drm_debugfs_create_files(hdmi->debugfs_files,
ARRAY_SIZE(debugfs_files),
hdmi->debugfs, minor);
if (err < 0)
goto free;
hdmi->minor = minor;
return 0;
free:
kfree(hdmi->debugfs_files);
hdmi->debugfs_files = NULL;
remove:
debugfs_remove(hdmi->debugfs);
hdmi->debugfs = NULL;
return err;
}
static void tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi)
{
drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files),
hdmi->minor);
hdmi->minor = NULL;
kfree(hdmi->debugfs_files);
hdmi->debugfs_files = NULL;
debugfs_remove(hdmi->debugfs);
hdmi->debugfs = NULL;
}
static int tegra_hdmi_init(struct host1x_client *client)
{
struct drm_device *drm = dev_get_drvdata(client->parent);
@ -1505,12 +1500,6 @@ static int tegra_hdmi_init(struct host1x_client *client)
hdmi->output.encoder.possible_crtcs = 0x3;
if (IS_ENABLED(CONFIG_DEBUG_FS)) {
err = tegra_hdmi_debugfs_init(hdmi, drm->primary);
if (err < 0)
dev_err(client->dev, "debugfs setup failed: %d\n", err);
}
err = regulator_enable(hdmi->hdmi);
if (err < 0) {
dev_err(client->dev, "failed to enable HDMI regulator: %d\n",
@ -1543,9 +1532,6 @@ static int tegra_hdmi_exit(struct host1x_client *client)
regulator_disable(hdmi->pll);
regulator_disable(hdmi->hdmi);
if (IS_ENABLED(CONFIG_DEBUG_FS))
tegra_hdmi_debugfs_exit(hdmi);
return 0;
}

806
drivers/gpu/drm/tegra/hub.c 100644
View File

@ -0,0 +1,806 @@
/*
* Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/clk.h>
#include <linux/host1x.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_graph.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc_helper.h>
#include "drm.h"
#include "dc.h"
#include "plane.h"
static const u32 tegra_shared_plane_formats[] = {
DRM_FORMAT_ARGB1555,
DRM_FORMAT_RGB565,
DRM_FORMAT_RGBA5551,
DRM_FORMAT_ARGB8888,
DRM_FORMAT_ABGR8888,
/* new on Tegra114 */
DRM_FORMAT_ABGR4444,
DRM_FORMAT_ABGR1555,
DRM_FORMAT_BGRA5551,
DRM_FORMAT_XRGB1555,
DRM_FORMAT_RGBX5551,
DRM_FORMAT_XBGR1555,
DRM_FORMAT_BGRX5551,
DRM_FORMAT_BGR565,
DRM_FORMAT_XRGB8888,
DRM_FORMAT_XBGR8888,
/* planar formats */
DRM_FORMAT_UYVY,
DRM_FORMAT_YUYV,
DRM_FORMAT_YUV420,
DRM_FORMAT_YUV422,
};
static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
unsigned int offset)
{
if (offset >= 0x500 && offset <= 0x581) {
offset = 0x000 + (offset - 0x500);
return plane->offset + offset;
}
if (offset >= 0x700 && offset <= 0x73c) {
offset = 0x180 + (offset - 0x700);
return plane->offset + offset;
}
if (offset >= 0x800 && offset <= 0x83e) {
offset = 0x1c0 + (offset - 0x800);
return plane->offset + offset;
}
dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
return plane->offset + offset;
}
static inline u32 tegra_plane_readl(struct tegra_plane *plane,
unsigned int offset)
{
return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
}
static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
unsigned int offset)
{
tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
}
static int tegra_windowgroup_enable(struct tegra_windowgroup *wgrp)
{
mutex_lock(&wgrp->lock);
if (wgrp->usecount == 0) {
pm_runtime_get_sync(wgrp->parent);
reset_control_deassert(wgrp->rst);
}
wgrp->usecount++;
mutex_unlock(&wgrp->lock);
return 0;
}
static void tegra_windowgroup_disable(struct tegra_windowgroup *wgrp)
{
int err;
mutex_lock(&wgrp->lock);
if (wgrp->usecount == 1) {
err = reset_control_assert(wgrp->rst);
if (err < 0) {
pr_err("failed to assert reset for window group %u\n",
wgrp->index);
}
pm_runtime_put(wgrp->parent);
}
wgrp->usecount--;
mutex_unlock(&wgrp->lock);
}
int tegra_display_hub_prepare(struct tegra_display_hub *hub)
{
unsigned int i;
/*
* XXX Enabling/disabling windowgroups needs to happen when the owner
* display controller is disabled. There's currently no good point at
* which this could be executed, so unconditionally enable all window
* groups for now.
*/
for (i = 0; i < hub->soc->num_wgrps; i++) {
struct tegra_windowgroup *wgrp = &hub->wgrps[i];
tegra_windowgroup_enable(wgrp);
}
return 0;
}
void tegra_display_hub_cleanup(struct tegra_display_hub *hub)
{
unsigned int i;
/*
* XXX Remove this once window groups can be more fine-grainedly
* enabled and disabled.
*/
for (i = 0; i < hub->soc->num_wgrps; i++) {
struct tegra_windowgroup *wgrp = &hub->wgrps[i];
tegra_windowgroup_disable(wgrp);
}
}
static void tegra_shared_plane_update(struct tegra_plane *plane)
{
struct tegra_dc *dc = plane->dc;
unsigned long timeout;
u32 mask, value;
mask = COMMON_UPDATE | WIN_A_UPDATE << plane->base.index;
tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL);
timeout = jiffies + msecs_to_jiffies(1000);
while (time_before(jiffies, timeout)) {
value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
if ((value & mask) == 0)
break;
usleep_range(100, 400);
}
}
static void tegra_shared_plane_activate(struct tegra_plane *plane)
{
struct tegra_dc *dc = plane->dc;
unsigned long timeout;
u32 mask, value;
mask = COMMON_ACTREQ | WIN_A_ACT_REQ << plane->base.index;
tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL);
timeout = jiffies + msecs_to_jiffies(1000);
while (time_before(jiffies, timeout)) {
value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
if ((value & mask) == 0)
break;
usleep_range(100, 400);
}
}
static unsigned int
tegra_shared_plane_get_owner(struct tegra_plane *plane, struct tegra_dc *dc)
{
unsigned int offset =
tegra_plane_offset(plane, DC_WIN_CORE_WINDOWGROUP_SET_CONTROL);
return tegra_dc_readl(dc, offset) & OWNER_MASK;
}
static bool tegra_dc_owns_shared_plane(struct tegra_dc *dc,
struct tegra_plane *plane)
{
struct device *dev = dc->dev;
if (tegra_shared_plane_get_owner(plane, dc) == dc->pipe) {
if (plane->dc == dc)
return true;
dev_WARN(dev, "head %u owns window %u but is not attached\n",
dc->pipe, plane->index);
}
return false;
}
static int tegra_shared_plane_set_owner(struct tegra_plane *plane,
struct tegra_dc *new)
{
unsigned int offset =
tegra_plane_offset(plane, DC_WIN_CORE_WINDOWGROUP_SET_CONTROL);
struct tegra_dc *old = plane->dc, *dc = new ? new : old;
struct device *dev = new ? new->dev : old->dev;
unsigned int owner, index = plane->index;
u32 value;
value = tegra_dc_readl(dc, offset);
owner = value & OWNER_MASK;
if (new && (owner != OWNER_MASK && owner != new->pipe)) {
dev_WARN(dev, "window %u owned by head %u\n", index, owner);
return -EBUSY;
}
/*
* This seems to happen whenever the head has been disabled with one
* or more windows being active. This is harmless because we'll just
* reassign the window to the new head anyway.
*/
if (old && owner == OWNER_MASK)
dev_dbg(dev, "window %u not owned by head %u but %u\n", index,
old->pipe, owner);
value &= ~OWNER_MASK;
if (new)
value |= OWNER(new->pipe);
else
value |= OWNER_MASK;
tegra_dc_writel(dc, value, offset);
plane->dc = new;
return 0;
}
static void tegra_dc_assign_shared_plane(struct tegra_dc *dc,
struct tegra_plane *plane)
{
u32 value;
int err;
if (!tegra_dc_owns_shared_plane(dc, plane)) {
err = tegra_shared_plane_set_owner(plane, dc);
if (err < 0)
return;
}
value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_LINEBUF_CONFIG);
value |= MODE_FOUR_LINES;
tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_LINEBUF_CONFIG);
value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_FETCH_METER);
value = SLOTS(1);
tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_FETCH_METER);
/* disable watermark */
value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA);
value &= ~LATENCY_CTL_MODE_ENABLE;
tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA);
value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB);
value |= WATERMARK_MASK;
tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB);
/* pipe meter */
value = tegra_plane_readl(plane, DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER);
value = PIPE_METER_INT(0) | PIPE_METER_FRAC(0);
tegra_plane_writel(plane, value, DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER);
/* mempool entries */
value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG);
value = MEMPOOL_ENTRIES(0x331);
tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG);
value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_THREAD_GROUP);
value &= ~THREAD_NUM_MASK;
value |= THREAD_NUM(plane->base.index);
value |= THREAD_GROUP_ENABLE;
tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_THREAD_GROUP);
tegra_shared_plane_update(plane);
tegra_shared_plane_activate(plane);
}
static void tegra_dc_remove_shared_plane(struct tegra_dc *dc,
struct tegra_plane *plane)
{
tegra_shared_plane_set_owner(plane, NULL);
}
static int tegra_shared_plane_atomic_check(struct drm_plane *plane,
struct drm_plane_state *state)
{
struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
struct tegra_shared_plane *tegra = to_tegra_shared_plane(plane);
struct tegra_bo_tiling *tiling = &plane_state->tiling;
struct tegra_dc *dc = to_tegra_dc(state->crtc);
int err;
/* no need for further checks if the plane is being disabled */
if (!state->crtc || !state->fb)
return 0;
err = tegra_plane_format(state->fb->format->format,
&plane_state->format,
&plane_state->swap);
if (err < 0)
return err;
err = tegra_fb_get_tiling(state->fb, tiling);
if (err < 0)
return err;
if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
!dc->soc->supports_block_linear) {
DRM_ERROR("hardware doesn't support block linear mode\n");
return -EINVAL;
}
/*
* Tegra doesn't support different strides for U and V planes so we
* error out if the user tries to display a framebuffer with such a
* configuration.
*/
if (state->fb->format->num_planes > 2) {
if (state->fb->pitches[2] != state->fb->pitches[1]) {
DRM_ERROR("unsupported UV-plane configuration\n");
return -EINVAL;
}
}
/* XXX scaling is not yet supported, add a check here */
err = tegra_plane_state_add(&tegra->base, state);
if (err < 0)
return err;
return 0;
}
static void tegra_shared_plane_atomic_disable(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
struct tegra_dc *dc = to_tegra_dc(old_state->crtc);
struct tegra_plane *p = to_tegra_plane(plane);
u32 value;
/* rien ne va plus */
if (!old_state || !old_state->crtc)
return;
/*
* XXX Legacy helpers seem to sometimes call ->atomic_disable() even
* on planes that are already disabled. Make sure we fallback to the
* head for this particular state instead of crashing.
*/
if (WARN_ON(p->dc == NULL))
p->dc = dc;
pm_runtime_get_sync(dc->dev);
value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
value &= ~WIN_ENABLE;
tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
tegra_dc_remove_shared_plane(dc, p);
pm_runtime_put(dc->dev);
}
static void tegra_shared_plane_atomic_update(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
unsigned int zpos = plane->state->normalized_zpos;
struct drm_framebuffer *fb = plane->state->fb;
struct tegra_plane *p = to_tegra_plane(plane);
struct tegra_bo *bo;
dma_addr_t base;
u32 value;
/* rien ne va plus */
if (!plane->state->crtc || !plane->state->fb)
return;
if (!plane->state->visible) {
tegra_shared_plane_atomic_disable(plane, old_state);
return;
}
pm_runtime_get_sync(dc->dev);
tegra_dc_assign_shared_plane(dc, p);
tegra_plane_writel(p, VCOUNTER, DC_WIN_CORE_ACT_CONTROL);
/* blending */
value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
tegra_plane_writel(p, value, DC_WIN_BLEND_MATCH_SELECT);
value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
tegra_plane_writel(p, value, DC_WIN_BLEND_NOMATCH_SELECT);
value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - zpos);
tegra_plane_writel(p, value, DC_WIN_BLEND_LAYER_CONTROL);
/* bypass scaling */
value = HORIZONTAL_TAPS_5 | VERTICAL_TAPS_5;
tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER);
value = INPUT_SCALER_VBYPASS | INPUT_SCALER_HBYPASS;
tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE);
/* disable compression */
tegra_plane_writel(p, 0, DC_WINBUF_CDE_CONTROL);
bo = tegra_fb_get_plane(fb, 0);
base = bo->paddr;
tegra_plane_writel(p, state->format, DC_WIN_COLOR_DEPTH);
tegra_plane_writel(p, 0, DC_WIN_PRECOMP_WGRP_PARAMS);
value = V_POSITION(plane->state->crtc_y) |
H_POSITION(plane->state->crtc_x);
tegra_plane_writel(p, value, DC_WIN_POSITION);
value = V_SIZE(plane->state->crtc_h) | H_SIZE(plane->state->crtc_w);
tegra_plane_writel(p, value, DC_WIN_SIZE);
value = WIN_ENABLE | COLOR_EXPAND;
tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
value = V_SIZE(plane->state->crtc_h) | H_SIZE(plane->state->crtc_w);
tegra_plane_writel(p, value, DC_WIN_CROPPED_SIZE);
tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI);
tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR);
value = PITCH(fb->pitches[0]);
tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE);
value = CLAMP_BEFORE_BLEND | DEGAMMA_SRGB | INPUT_RANGE_FULL;
tegra_plane_writel(p, value, DC_WIN_SET_PARAMS);
value = OFFSET_X(plane->state->src_y >> 16) |
OFFSET_Y(plane->state->src_x >> 16);
tegra_plane_writel(p, value, DC_WINBUF_CROPPED_POINT);
if (dc->soc->supports_block_linear) {
unsigned long height = state->tiling.value;
/* XXX */
switch (state->tiling.mode) {
case TEGRA_BO_TILING_MODE_PITCH:
value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(0) |
DC_WINBUF_SURFACE_KIND_PITCH;
break;
/* XXX not supported on Tegra186 and later */
case TEGRA_BO_TILING_MODE_TILED:
value = DC_WINBUF_SURFACE_KIND_TILED;
break;
case TEGRA_BO_TILING_MODE_BLOCK:
value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
DC_WINBUF_SURFACE_KIND_BLOCK;
break;
}
tegra_plane_writel(p, value, DC_WINBUF_SURFACE_KIND);
}
/* disable gamut CSC */
value = tegra_plane_readl(p, DC_WIN_WINDOW_SET_CONTROL);
value &= ~CONTROL_CSC_ENABLE;
tegra_plane_writel(p, value, DC_WIN_WINDOW_SET_CONTROL);
pm_runtime_put(dc->dev);
}
static const struct drm_plane_helper_funcs tegra_shared_plane_helper_funcs = {
.atomic_check = tegra_shared_plane_atomic_check,
.atomic_update = tegra_shared_plane_atomic_update,
.atomic_disable = tegra_shared_plane_atomic_disable,
};
struct drm_plane *tegra_shared_plane_create(struct drm_device *drm,
struct tegra_dc *dc,
unsigned int wgrp,
unsigned int index)
{
enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY;
struct tegra_drm *tegra = drm->dev_private;
struct tegra_display_hub *hub = tegra->hub;
/* planes can be assigned to arbitrary CRTCs */
unsigned int possible_crtcs = 0x7;
struct tegra_shared_plane *plane;
unsigned int num_formats;
struct drm_plane *p;
const u32 *formats;
int err;
plane = kzalloc(sizeof(*plane), GFP_KERNEL);
if (!plane)
return ERR_PTR(-ENOMEM);
plane->base.offset = 0x0a00 + 0x0300 * index;
plane->base.index = index;
plane->wgrp = &hub->wgrps[wgrp];
plane->wgrp->parent = dc->dev;
p = &plane->base.base;
num_formats = ARRAY_SIZE(tegra_shared_plane_formats);
formats = tegra_shared_plane_formats;
err = drm_universal_plane_init(drm, p, possible_crtcs,
&tegra_plane_funcs, formats,
num_formats, NULL, type, NULL);
if (err < 0) {
kfree(plane);
return ERR_PTR(err);
}
drm_plane_helper_add(p, &tegra_shared_plane_helper_funcs);
drm_plane_create_zpos_property(p, 0, 0, 255);
return p;
}
static void tegra_display_hub_update(struct tegra_dc *dc)
{
u32 value;
pm_runtime_get_sync(dc->dev);
value = tegra_dc_readl(dc, DC_CMD_IHUB_COMMON_MISC_CTL);
value &= ~LATENCY_EVENT;
tegra_dc_writel(dc, value, DC_CMD_IHUB_COMMON_MISC_CTL);
value = tegra_dc_readl(dc, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER);
value = CURS_SLOTS(1) | WGRP_SLOTS(1);
tegra_dc_writel(dc, value, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER);
tegra_dc_writel(dc, COMMON_UPDATE, DC_CMD_STATE_CONTROL);
tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
tegra_dc_writel(dc, COMMON_ACTREQ, DC_CMD_STATE_CONTROL);
tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
pm_runtime_put(dc->dev);
}
void tegra_display_hub_atomic_commit(struct drm_device *drm,
struct drm_atomic_state *state)
{
struct tegra_atomic_state *s = to_tegra_atomic_state(state);
struct tegra_drm *tegra = drm->dev_private;
struct tegra_display_hub *hub = tegra->hub;
struct device *dev = hub->client.dev;
int err;
if (s->clk_disp) {
err = clk_set_rate(s->clk_disp, s->rate);
if (err < 0)
dev_err(dev, "failed to set rate of %pC to %lu Hz\n",
s->clk_disp, s->rate);
err = clk_set_parent(hub->clk_disp, s->clk_disp);
if (err < 0)
dev_err(dev, "failed to set parent of %pC to %pC: %d\n",
hub->clk_disp, s->clk_disp, err);
}
if (s->dc)
tegra_display_hub_update(s->dc);
}
static int tegra_display_hub_init(struct host1x_client *client)
{
struct tegra_display_hub *hub = to_tegra_display_hub(client);
struct drm_device *drm = dev_get_drvdata(client->parent);
struct tegra_drm *tegra = drm->dev_private;
tegra->hub = hub;
return 0;
}
static int tegra_display_hub_exit(struct host1x_client *client)
{
struct drm_device *drm = dev_get_drvdata(client->parent);
struct tegra_drm *tegra = drm->dev_private;
tegra->hub = NULL;
return 0;
}
static const struct host1x_client_ops tegra_display_hub_ops = {
.init = tegra_display_hub_init,
.exit = tegra_display_hub_exit,
};
static int tegra_display_hub_probe(struct platform_device *pdev)
{
struct tegra_display_hub *hub;
unsigned int i;
int err;
hub = devm_kzalloc(&pdev->dev, sizeof(*hub), GFP_KERNEL);
if (!hub)
return -ENOMEM;
hub->soc = of_device_get_match_data(&pdev->dev);
hub->clk_disp = devm_clk_get(&pdev->dev, "disp");
if (IS_ERR(hub->clk_disp)) {
err = PTR_ERR(hub->clk_disp);
return err;
}
hub->clk_dsc = devm_clk_get(&pdev->dev, "dsc");
if (IS_ERR(hub->clk_dsc)) {
err = PTR_ERR(hub->clk_dsc);
return err;
}
hub->clk_hub = devm_clk_get(&pdev->dev, "hub");
if (IS_ERR(hub->clk_hub)) {
err = PTR_ERR(hub->clk_hub);
return err;
}
hub->rst = devm_reset_control_get(&pdev->dev, "misc");
if (IS_ERR(hub->rst)) {
err = PTR_ERR(hub->rst);
return err;
}
hub->wgrps = devm_kcalloc(&pdev->dev, hub->soc->num_wgrps,
sizeof(*hub->wgrps), GFP_KERNEL);
if (!hub->wgrps)
return -ENOMEM;
for (i = 0; i < hub->soc->num_wgrps; i++) {
struct tegra_windowgroup *wgrp = &hub->wgrps[i];
char id[8];
snprintf(id, sizeof(id), "wgrp%u", i);
mutex_init(&wgrp->lock);
wgrp->usecount = 0;
wgrp->index = i;
wgrp->rst = devm_reset_control_get(&pdev->dev, id);
if (IS_ERR(wgrp->rst))
return PTR_ERR(wgrp->rst);
err = reset_control_assert(wgrp->rst);
if (err < 0)
return err;
}
/* XXX: enable clock across reset? */
err = reset_control_assert(hub->rst);
if (err < 0)
return err;
platform_set_drvdata(pdev, hub);
pm_runtime_enable(&pdev->dev);
INIT_LIST_HEAD(&hub->client.list);
hub->client.ops = &tegra_display_hub_ops;
hub->client.dev = &pdev->dev;
err = host1x_client_register(&hub->client);
if (err < 0)
dev_err(&pdev->dev, "failed to register host1x client: %d\n",
err);
return err;
}
static int tegra_display_hub_remove(struct platform_device *pdev)
{
struct tegra_display_hub *hub = platform_get_drvdata(pdev);
int err;
err = host1x_client_unregister(&hub->client);
if (err < 0) {
dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
err);
}
pm_runtime_disable(&pdev->dev);
return err;
}
static int __maybe_unused tegra_display_hub_suspend(struct device *dev)
{
struct tegra_display_hub *hub = dev_get_drvdata(dev);
int err;
err = reset_control_assert(hub->rst);
if (err < 0)
return err;
clk_disable_unprepare(hub->clk_hub);
clk_disable_unprepare(hub->clk_dsc);
clk_disable_unprepare(hub->clk_disp);
return 0;
}
static int __maybe_unused tegra_display_hub_resume(struct device *dev)
{
struct tegra_display_hub *hub = dev_get_drvdata(dev);
int err;
err = clk_prepare_enable(hub->clk_disp);
if (err < 0)
return err;
err = clk_prepare_enable(hub->clk_dsc);
if (err < 0)
goto disable_disp;
err = clk_prepare_enable(hub->clk_hub);
if (err < 0)
goto disable_dsc;
err = reset_control_deassert(hub->rst);
if (err < 0)
goto disable_hub;
return 0;
disable_hub:
clk_disable_unprepare(hub->clk_hub);
disable_dsc:
clk_disable_unprepare(hub->clk_dsc);
disable_disp:
clk_disable_unprepare(hub->clk_disp);
return err;
}
static const struct dev_pm_ops tegra_display_hub_pm_ops = {
SET_RUNTIME_PM_OPS(tegra_display_hub_suspend,
tegra_display_hub_resume, NULL)
};
static const struct tegra_display_hub_soc tegra186_display_hub = {
.num_wgrps = 6,
};
static const struct of_device_id tegra_display_hub_of_match[] = {
{
.compatible = "nvidia,tegra186-display",
.data = &tegra186_display_hub
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, tegra_display_hub_of_match);
struct platform_driver tegra_display_hub_driver = {
.driver = {
.name = "tegra-display-hub",
.of_match_table = tegra_display_hub_of_match,
.pm = &tegra_display_hub_pm_ops,
},
.probe = tegra_display_hub_probe,
.remove = tegra_display_hub_remove,
};

81
drivers/gpu/drm/tegra/hub.h 100644
View File

@ -0,0 +1,81 @@
/*
* Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef TEGRA_HUB_H
#define TEGRA_HUB_H 1
#include <drm/drmP.h>
#include <drm/drm_plane.h>
#include "plane.h"
struct tegra_dc;
struct tegra_windowgroup {
unsigned int usecount;
struct mutex lock;
unsigned int index;
struct device *parent;
struct reset_control *rst;
};
struct tegra_shared_plane {
struct tegra_plane base;
struct tegra_windowgroup *wgrp;
};
static inline struct tegra_shared_plane *
to_tegra_shared_plane(struct drm_plane *plane)
{
return container_of(plane, struct tegra_shared_plane, base.base);
}
struct tegra_display_hub_soc {
unsigned int num_wgrps;
};
struct tegra_display_hub {
struct host1x_client client;
struct clk *clk_disp;
struct clk *clk_dsc;
struct clk *clk_hub;
struct reset_control *rst;
const struct tegra_display_hub_soc *soc;
struct tegra_windowgroup *wgrps;
};
static inline struct tegra_display_hub *
to_tegra_display_hub(struct host1x_client *client)
{
return container_of(client, struct tegra_display_hub, client);
}
struct tegra_dc;
struct tegra_plane;
int tegra_display_hub_prepare(struct tegra_display_hub *hub);
void tegra_display_hub_cleanup(struct tegra_display_hub *hub);
struct drm_plane *tegra_shared_plane_create(struct drm_device *drm,
struct tegra_dc *dc,
unsigned int wgrp,
unsigned int index);
void tegra_display_hub_atomic_commit(struct drm_device *drm,
struct drm_atomic_state *state);
#define DC_CMD_IHUB_COMMON_MISC_CTL 0x068
#define LATENCY_EVENT (1 << 3)
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER 0x451
#define CURS_SLOTS(x) (((x) & 0xff) << 8)
#define WGRP_SLOTS(x) (((x) & 0xff) << 0)
#endif /* TEGRA_HUB_H */

24
drivers/gpu/drm/tegra/output.c
View File

@ -9,7 +9,9 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_panel.h>
#include "drm.h"
#include "dc.h"
#include <media/cec-notifier.h>
@ -218,3 +220,25 @@ void tegra_output_exit(struct tegra_output *output)
if (output->panel)
drm_panel_detach(output->panel);
}
void tegra_output_find_possible_crtcs(struct tegra_output *output,
struct drm_device *drm)
{
struct device *dev = output->dev;
struct drm_crtc *crtc;
unsigned int mask = 0;
drm_for_each_crtc(crtc, drm) {
struct tegra_dc *dc = to_tegra_dc(crtc);
if (tegra_dc_has_output(dc, dev))
mask |= drm_crtc_mask(crtc);
}
if (mask == 0) {
dev_warn(dev, "missing output definition for heads in DT\n");
mask = 0x3;
}
output->encoder.possible_crtcs = mask;
}

383
drivers/gpu/drm/tegra/plane.c 100644
View File

@ -0,0 +1,383 @@
/*
* Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_plane_helper.h>
#include "dc.h"
#include "plane.h"
static void tegra_plane_destroy(struct drm_plane *plane)
{
struct tegra_plane *p = to_tegra_plane(plane);
drm_plane_cleanup(plane);
kfree(p);
}
static void tegra_plane_reset(struct drm_plane *plane)
{
struct tegra_plane_state *state;
if (plane->state)
__drm_atomic_helper_plane_destroy_state(plane->state);
kfree(plane->state);
plane->state = NULL;
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (state) {
plane->state = &state->base;
plane->state->plane = plane;
}
}
static struct drm_plane_state *
tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
{
struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
struct tegra_plane_state *copy;
unsigned int i;
copy = kmalloc(sizeof(*copy), GFP_KERNEL);
if (!copy)
return NULL;
__drm_atomic_helper_plane_duplicate_state(plane, &copy->base);
copy->tiling = state->tiling;
copy->format = state->format;
copy->swap = state->swap;
copy->opaque = state->opaque;
for (i = 0; i < 3; i++)
copy->dependent[i] = state->dependent[i];
return &copy->base;
}
static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
struct drm_plane_state *state)
{
__drm_atomic_helper_plane_destroy_state(state);
kfree(state);
}
const struct drm_plane_funcs tegra_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
.destroy = tegra_plane_destroy,
.reset = tegra_plane_reset,
.atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
.atomic_destroy_state = tegra_plane_atomic_destroy_state,
};
int tegra_plane_state_add(struct tegra_plane *plane,
struct drm_plane_state *state)
{
struct drm_crtc_state *crtc_state;
struct tegra_dc_state *tegra;
struct drm_rect clip;
int err;
/* Propagate errors from allocation or locking failures. */
crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
if (IS_ERR(crtc_state))
return PTR_ERR(crtc_state);
clip.x1 = 0;
clip.y1 = 0;
clip.x2 = crtc_state->mode.hdisplay;
clip.y2 = crtc_state->mode.vdisplay;
/* Check plane state for visibility and calculate clipping bounds */
err = drm_atomic_helper_check_plane_state(state, crtc_state, &clip,
0, INT_MAX, true, true);
if (err < 0)
return err;
tegra = to_dc_state(crtc_state);
tegra->planes |= WIN_A_ACT_REQ << plane->index;
return 0;
}
int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap)
{
/* assume no swapping of fetched data */
if (swap)
*swap = BYTE_SWAP_NOSWAP;
switch (fourcc) {
case DRM_FORMAT_ARGB4444:
*format = WIN_COLOR_DEPTH_B4G4R4A4;
break;
case DRM_FORMAT_ARGB1555:
*format = WIN_COLOR_DEPTH_B5G5R5A1;
break;
case DRM_FORMAT_RGB565:
*format = WIN_COLOR_DEPTH_B5G6R5;
break;
case DRM_FORMAT_RGBA5551:
*format = WIN_COLOR_DEPTH_A1B5G5R5;
break;
case DRM_FORMAT_ARGB8888:
*format = WIN_COLOR_DEPTH_B8G8R8A8;
break;
case DRM_FORMAT_ABGR8888:
*format = WIN_COLOR_DEPTH_R8G8B8A8;
break;
case DRM_FORMAT_ABGR4444:
*format = WIN_COLOR_DEPTH_R4G4B4A4;
break;
case DRM_FORMAT_ABGR1555:
*format = WIN_COLOR_DEPTH_R5G5B5A;
break;
case DRM_FORMAT_BGRA5551:
*format = WIN_COLOR_DEPTH_AR5G5B5;
break;
case DRM_FORMAT_XRGB1555:
*format = WIN_COLOR_DEPTH_B5G5R5X1;
break;
case DRM_FORMAT_RGBX5551:
*format = WIN_COLOR_DEPTH_X1B5G5R5;
break;
case DRM_FORMAT_XBGR1555:
*format = WIN_COLOR_DEPTH_R5G5B5X1;
break;
case DRM_FORMAT_BGRX5551:
*format = WIN_COLOR_DEPTH_X1R5G5B5;
break;
case DRM_FORMAT_BGR565:
*format = WIN_COLOR_DEPTH_R5G6B5;
break;
case DRM_FORMAT_BGRA8888:
*format = WIN_COLOR_DEPTH_A8R8G8B8;
break;
case DRM_FORMAT_RGBA8888:
*format = WIN_COLOR_DEPTH_A8B8G8R8;
break;
case DRM_FORMAT_XRGB8888:
*format = WIN_COLOR_DEPTH_B8G8R8X8;
break;
case DRM_FORMAT_XBGR8888:
*format = WIN_COLOR_DEPTH_R8G8B8X8;
break;
case DRM_FORMAT_UYVY:
*format = WIN_COLOR_DEPTH_YCbCr422;
break;
case DRM_FORMAT_YUYV:
if (!swap)
return -EINVAL;
*format = WIN_COLOR_DEPTH_YCbCr422;
*swap = BYTE_SWAP_SWAP2;
break;
case DRM_FORMAT_YUV420:
*format = WIN_COLOR_DEPTH_YCbCr420P;
break;
case DRM_FORMAT_YUV422:
*format = WIN_COLOR_DEPTH_YCbCr422P;
break;
default:
return -EINVAL;
}
return 0;
}
bool tegra_plane_format_is_yuv(unsigned int format, bool *planar)
{
switch (format) {
case WIN_COLOR_DEPTH_YCbCr422:
case WIN_COLOR_DEPTH_YUV422:
if (planar)
*planar = false;
return true;
case WIN_COLOR_DEPTH_YCbCr420P:
case WIN_COLOR_DEPTH_YUV420P:
case WIN_COLOR_DEPTH_YCbCr422P:
case WIN_COLOR_DEPTH_YUV422P:
case WIN_COLOR_DEPTH_YCbCr422R:
case WIN_COLOR_DEPTH_YUV422R:
case WIN_COLOR_DEPTH_YCbCr422RA:
case WIN_COLOR_DEPTH_YUV422RA:
if (planar)
*planar = true;
return true;
}
if (planar)
*planar = false;
return false;
}
static bool __drm_format_has_alpha(u32 format)
{
switch (format) {
case DRM_FORMAT_ARGB1555:
case DRM_FORMAT_RGBA5551:
case DRM_FORMAT_ABGR8888:
case DRM_FORMAT_ARGB8888:
return true;
}
return false;
}
/*
* This is applicable to Tegra20 and Tegra30 only where the opaque formats can
* be emulated using the alpha formats and alpha blending disabled.
*/
bool tegra_plane_format_has_alpha(unsigned int format)
{
switch (format) {
case WIN_COLOR_DEPTH_B5G5R5A1:
case WIN_COLOR_DEPTH_A1B5G5R5:
case WIN_COLOR_DEPTH_R8G8B8A8:
case WIN_COLOR_DEPTH_B8G8R8A8:
return true;
}
return false;
}
int tegra_plane_format_get_alpha(unsigned int opaque, unsigned int *alpha)
{
if (tegra_plane_format_is_yuv(opaque, NULL)) {
*alpha = opaque;
return 0;
}
switch (opaque) {
case WIN_COLOR_DEPTH_B5G5R5X1:
*alpha = WIN_COLOR_DEPTH_B5G5R5A1;
return 0;
case WIN_COLOR_DEPTH_X1B5G5R5:
*alpha = WIN_COLOR_DEPTH_A1B5G5R5;
return 0;
case WIN_COLOR_DEPTH_R8G8B8X8:
*alpha = WIN_COLOR_DEPTH_R8G8B8A8;
return 0;
case WIN_COLOR_DEPTH_B8G8R8X8:
*alpha = WIN_COLOR_DEPTH_B8G8R8A8;
return 0;
}
return -EINVAL;
}
unsigned int tegra_plane_get_overlap_index(struct tegra_plane *plane,
struct tegra_plane *other)
{
unsigned int index = 0, i;
WARN_ON(plane == other);
for (i = 0; i < 3; i++) {
if (i == plane->index)
continue;
if (i == other->index)
break;
index++;
}
return index;
}
void tegra_plane_check_dependent(struct tegra_plane *tegra,
struct tegra_plane_state *state)
{
struct drm_plane_state *old, *new;
struct drm_plane *plane;
unsigned int zpos[2];
unsigned int i;
for (i = 0; i < 3; i++)
state->dependent[i] = false;
for (i = 0; i < 2; i++)
zpos[i] = 0;
for_each_oldnew_plane_in_state(state->base.state, plane, old, new, i) {
struct tegra_plane *p = to_tegra_plane(plane);
unsigned index;
/* skip this plane and planes on different CRTCs */
if (p == tegra || new->crtc != state->base.crtc)
continue;
index = tegra_plane_get_overlap_index(tegra, p);
/*
* If any of the other planes is on top of this plane and uses
* a format with an alpha component, mark this plane as being
* dependent, meaning it's alpha value will be 1 minus the sum
* of alpha components of the overlapping planes.
*/
if (p->index > tegra->index) {
if (__drm_format_has_alpha(new->fb->format->format))
state->dependent[index] = true;
/* keep track of the Z position */
zpos[index] = p->index;
}
}
/*
* The region where three windows overlap is the intersection of the
* two regions where two windows overlap. It contributes to the area
* if any of the windows on top of it have an alpha component.
*/
for (i = 0; i < 2; i++)
state->dependent[2] = state->dependent[2] ||
state->dependent[i];
/*
* However, if any of the windows on top of this window is opaque, it
* will completely conceal this window within that area, so avoid the
* window from contributing to the area.
*/
for (i = 0; i < 2; i++) {
if (zpos[i] > tegra->index)
state->dependent[2] = state->dependent[2] &&
state->dependent[i];
}
}

70
drivers/gpu/drm/tegra/plane.h 100644
View File

@ -0,0 +1,70 @@
/*
* Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef TEGRA_PLANE_H
#define TEGRA_PLANE_H 1
#include <drm/drm_plane.h>
struct tegra_bo;
struct tegra_dc;
struct tegra_plane {
struct drm_plane base;
struct tegra_dc *dc;
unsigned int offset;
unsigned int index;
};
struct tegra_cursor {
struct tegra_plane base;
struct tegra_bo *bo;
unsigned int width;
unsigned int height;
};
static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
{
return container_of(plane, struct tegra_plane, base);
}
struct tegra_plane_state {
struct drm_plane_state base;
struct tegra_bo_tiling tiling;
u32 format;
u32 swap;
/* used for legacy blending support only */
bool opaque;
bool dependent[3];
};
static inline struct tegra_plane_state *
to_tegra_plane_state(struct drm_plane_state *state)
{
if (state)
return container_of(state, struct tegra_plane_state, base);
return NULL;
}
extern const struct drm_plane_funcs tegra_plane_funcs;
int tegra_plane_state_add(struct tegra_plane *plane,
struct drm_plane_state *state);
int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap);
bool tegra_plane_format_is_yuv(unsigned int format, bool *planar);
bool tegra_plane_format_has_alpha(unsigned int format);
int tegra_plane_format_get_alpha(unsigned int opaque, unsigned int *alpha);
void tegra_plane_check_dependent(struct tegra_plane *tegra,
struct tegra_plane_state *state);
#endif /* TEGRA_PLANE_H */

1115
drivers/gpu/drm/tegra/sor.c
View File

File diff suppressed because it is too large Load Diff

16
drivers/gpu/drm/tegra/sor.h
View File

@ -89,6 +89,8 @@
#define SOR_PLL0 0x17
#define SOR_PLL0_ICHPMP_MASK (0xf << 24)
#define SOR_PLL0_ICHPMP(x) (((x) & 0xf) << 24)
#define SOR_PLL0_FILTER_MASK (0xf << 16)
#define SOR_PLL0_FILTER(x) (((x) & 0xf) << 16)
#define SOR_PLL0_VCOCAP_MASK (0xf << 8)
#define SOR_PLL0_VCOCAP(x) (((x) & 0xf) << 8)
#define SOR_PLL0_VCOCAP_RST SOR_PLL0_VCOCAP(3)
@ -122,10 +124,16 @@
#define SOR_PLL2_SEQ_PLL_PULLDOWN (1 << 16)
#define SOR_PLL3 0x1a
#define SOR_PLL3_BG_TEMP_COEF_MASK (0xf << 28)
#define SOR_PLL3_BG_TEMP_COEF(x) (((x) & 0xf) << 28)
#define SOR_PLL3_BG_VREF_LEVEL_MASK (0xf << 24)
#define SOR_PLL3_BG_VREF_LEVEL(x) (((x) & 0xf) << 24)
#define SOR_PLL3_PLL_VDD_MODE_1V8 (0 << 13)
#define SOR_PLL3_PLL_VDD_MODE_3V3 (1 << 13)
#define SOR_PLL3_AVDD10_LEVEL_MASK (0xf << 8)
#define SOR_PLL3_AVDD10_LEVEL(x) (((x) & 0xf) << 8)
#define SOR_PLL3_AVDD14_LEVEL_MASK (0xf << 4)
#define SOR_PLL3_AVDD14_LEVEL(x) (((x) & 0xf) << 4)
#define SOR_CSTM 0x1b
#define SOR_CSTM_ROTCLK_MASK (0xf << 24)
@ -334,6 +342,10 @@
#define SOR_DP_LQ_CSTM1 0x70
#define SOR_DP_LQ_CSTM2 0x71
#define SOR_DP_PADCTL2 0x73
#define SOR_DP_PADCTL_SPAREPLL_MASK (0xff << 24)
#define SOR_DP_PADCTL_SPAREPLL(x) (((x) & 0xff) << 24)
#define SOR_HDMI_AUDIO_INFOFRAME_CTRL 0x9a
#define SOR_HDMI_AUDIO_INFOFRAME_STATUS 0x9b
#define SOR_HDMI_AUDIO_INFOFRAME_HEADER 0x9c
@ -370,4 +382,8 @@
#define SOR_HDMI_VSI_INFOFRAME_STATUS 0x124
#define SOR_HDMI_VSI_INFOFRAME_HEADER 0x125
#define SOR_HDMI2_CTRL 0x13e
#define SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4 (1 << 1)
#define SOR_HDMI2_CTRL_SCRAMBLE (1 << 0)
#endif

20
drivers/gpu/drm/tegra/vic.c
View File

@ -115,7 +115,7 @@ static int vic_boot(struct vic *vic)
}
static void *vic_falcon_alloc(struct falcon *falcon, size_t size,
dma_addr_t *iova)
dma_addr_t *iova)
{
struct tegra_drm *tegra = falcon->data;
@ -138,13 +138,14 @@ static const struct falcon_ops vic_falcon_ops = {
static int vic_init(struct host1x_client *client)
{
struct tegra_drm_client *drm = host1x_to_drm_client(client);
struct iommu_group *group = iommu_group_get(client->dev);
struct drm_device *dev = dev_get_drvdata(client->parent);
struct tegra_drm *tegra = dev->dev_private;
struct vic *vic = to_vic(drm);
int err;
if (tegra->domain) {
err = iommu_attach_device(tegra->domain, vic->dev);
if (group && tegra->domain) {
err = iommu_attach_group(tegra->domain, group);
if (err < 0) {
dev_err(vic->dev, "failed to attach to domain: %d\n",
err);
@ -158,13 +159,13 @@ static int vic_init(struct host1x_client *client)
vic->falcon.data = tegra;
err = falcon_load_firmware(&vic->falcon);
if (err < 0)
goto detach_device;
goto detach;
}
vic->channel = host1x_channel_request(client->dev);
if (!vic->channel) {
err = -ENOMEM;
goto detach_device;
goto detach;
}
client->syncpts[0] = host1x_syncpt_request(client, 0);
@ -183,9 +184,9 @@ free_syncpt:
host1x_syncpt_free(client->syncpts[0]);
free_channel:
host1x_channel_put(vic->channel);
detach_device:
if (tegra->domain)
iommu_detach_device(tegra->domain, vic->dev);
detach:
if (group && tegra->domain)
iommu_detach_group(tegra->domain, group);
return err;
}
@ -193,6 +194,7 @@ detach_device:
static int vic_exit(struct host1x_client *client)
{
struct tegra_drm_client *drm = host1x_to_drm_client(client);
struct iommu_group *group = iommu_group_get(client->dev);
struct drm_device *dev = dev_get_drvdata(client->parent);
struct tegra_drm *tegra = dev->dev_private;
struct vic *vic = to_vic(drm);
@ -206,7 +208,7 @@ static int vic_exit(struct host1x_client *client)
host1x_channel_put(vic->channel);
if (vic->domain) {
iommu_detach_device(vic->domain, vic->dev);
iommu_detach_group(vic->domain, group);
vic->domain = NULL;
}

11
drivers/gpu/host1x/bus.c
View File

@ -211,8 +211,7 @@ int host1x_device_init(struct host1x_device *device)
dev_err(&device->dev,
"failed to initialize %s: %d\n",
dev_name(client->dev), err);
mutex_unlock(&device->clients_lock);
return err;
goto teardown;
}
}
}
@ -220,6 +219,14 @@ int host1x_device_init(struct host1x_device *device)
mutex_unlock(&device->clients_lock);
return 0;
teardown:
list_for_each_entry_continue_reverse(client, &device->clients, list)
if (client->ops->exit)
client->ops->exit(client);
mutex_unlock(&device->clients_lock);
return err;
}
EXPORT_SYMBOL(host1x_device_init);

34
drivers/gpu/host1x/dev.c
View File

@ -218,20 +218,27 @@ static int host1x_probe(struct platform_device *pdev)
return err;
}
if (iommu_present(&platform_bus_type)) {
host->group = iommu_group_get(&pdev->dev);
if (host->group) {
struct iommu_domain_geometry *geometry;
unsigned long order;
host->domain = iommu_domain_alloc(&platform_bus_type);
if (!host->domain)
return -ENOMEM;
if (!host->domain) {
err = -ENOMEM;
goto put_group;
}
err = iommu_attach_group(host->domain, host->group);
if (err) {
if (err == -ENODEV) {
iommu_domain_free(host->domain);
host->domain = NULL;
iommu_group_put(host->group);
host->group = NULL;
goto skip_iommu;
}
err = iommu_attach_device(host->domain, &pdev->dev);
if (err == -ENODEV) {
iommu_domain_free(host->domain);
host->domain = NULL;
goto skip_iommu;
} else if (err) {
goto fail_free_domain;
}
@ -294,13 +301,15 @@ fail_unprepare_disable:
fail_free_channels:
host1x_channel_list_free(&host->channel_list);
fail_detach_device:
if (host->domain) {
if (host->group && host->domain) {
put_iova_domain(&host->iova);
iommu_detach_device(host->domain, &pdev->dev);
iommu_detach_group(host->domain, host->group);
}
fail_free_domain:
if (host->domain)
iommu_domain_free(host->domain);
put_group:
iommu_group_put(host->group);
return err;
}
@ -317,8 +326,9 @@ static int host1x_remove(struct platform_device *pdev)
if (host->domain) {
put_iova_domain(&host->iova);
iommu_detach_device(host->domain, &pdev->dev);
iommu_detach_group(host->domain, host->group);
iommu_domain_free(host->domain);
iommu_group_put(host->group);
}
return 0;

1
drivers/gpu/host1x/dev.h
View File

@ -117,6 +117,7 @@ struct host1x {
struct clk *clk;
struct reset_control *rst;
struct iommu_group *group;
struct iommu_domain *domain;
struct iova_domain iova;
dma_addr_t iova_end;

38
include/uapi/drm/drm_fourcc.h
View File

@ -178,7 +178,7 @@ extern "C" {
#define DRM_FORMAT_MOD_VENDOR_NONE 0
#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
#define DRM_FORMAT_MOD_VENDOR_NV 0x03
#define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03
#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
@ -188,7 +188,7 @@ extern "C" {
#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
#define fourcc_mod_code(vendor, val) \
((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL))
((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
/*
* Format Modifier tokens:
@ -338,29 +338,17 @@ extern "C" {
*/
#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
/* NVIDIA Tegra frame buffer modifiers */
/*
* Some modifiers take parameters, for example the number of vertical GOBs in
* a block. Reserve the lower 32 bits for parameters
*/
#define __fourcc_mod_tegra_mode_shift 32
#define fourcc_mod_tegra_code(val, params) \
fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params))
#define fourcc_mod_tegra_mod(m) \
(m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
#define fourcc_mod_tegra_param(m) \
(m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
/* NVIDIA frame buffer modifiers */
/*
* Tegra Tiled Layout, used by Tegra 2, 3 and 4.
*
* Pixels are arranged in simple tiles of 16 x 16 bytes.
*/
#define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0)
#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
/*
* Tegra 16Bx2 Block Linear layout, used by TK1/TX1
* 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later
*
* Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
* vertically by a power of 2 (1 to 32 GOBs) to form a block.
@ -380,7 +368,21 @@ extern "C" {
* Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
* in full detail.
*/
#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v)
#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))
#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
fourcc_mod_code(NVIDIA, 0x10)
#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
fourcc_mod_code(NVIDIA, 0x11)
#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
fourcc_mod_code(NVIDIA, 0x12)
#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
fourcc_mod_code(NVIDIA, 0x13)
#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
fourcc_mod_code(NVIDIA, 0x14)
#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
fourcc_mod_code(NVIDIA, 0x15)
/*
* Broadcom VC4 "T" format