diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f10f55690749..c547f03904bc 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1193,77 +1193,74 @@ found:
 		}
 	}
 
-	if (min_dco_index > 2) {
-		WARN(1, "No valid parameters found for pixel clock: %dHz\n",
-		     clock);
+	if (WARN(min_dco_index > 2,
+		 "No valid parameters found for pixel clock: %dHz\n", clock))
 		return false;
-	} else {
-		wrpll_params->central_freq = dco_central_freq[min_dco_index];
 
-		switch (dco_central_freq[min_dco_index]) {
-		case 9600000000ULL:
-			wrpll_params->central_freq = 0;
-			break;
-		case 9000000000ULL:
-			wrpll_params->central_freq = 1;
-			break;
-		case 8400000000ULL:
-			wrpll_params->central_freq = 3;
-		}
-
-		switch (candidate_p0[min_dco_index]) {
-		case 1:
-			wrpll_params->pdiv = 0;
-			break;
-		case 2:
-			wrpll_params->pdiv = 1;
-			break;
-		case 3:
-			wrpll_params->pdiv = 2;
-			break;
-		case 7:
-			wrpll_params->pdiv = 4;
-			break;
-		default:
-			WARN(1, "Incorrect PDiv\n");
-		}
-
-		switch (candidate_p2[min_dco_index]) {
-		case 5:
-			wrpll_params->kdiv = 0;
-			break;
-		case 2:
-			wrpll_params->kdiv = 1;
-			break;
-		case 3:
-			wrpll_params->kdiv = 2;
-			break;
-		case 1:
-			wrpll_params->kdiv = 3;
-			break;
-		default:
-			WARN(1, "Incorrect KDiv\n");
-		}
-
-		wrpll_params->qdiv_ratio = candidate_p1[min_dco_index];
-		wrpll_params->qdiv_mode =
-			(wrpll_params->qdiv_ratio == 1) ? 0 : 1;
-
-		dco_freq = candidate_p0[min_dco_index] *
-			candidate_p1[min_dco_index] *
-			candidate_p2[min_dco_index] * afe_clock;
-
-		/*
-		 * Intermediate values are in Hz.
-		 * Divide by MHz to match bsepc
-		 */
-		wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1)));
-		wrpll_params->dco_fraction =
-			div_u64(((div_u64(dco_freq, 24) -
-				  wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));
+	wrpll_params->central_freq = dco_central_freq[min_dco_index];
 
+	switch (dco_central_freq[min_dco_index]) {
+	case 9600000000ULL:
+		wrpll_params->central_freq = 0;
+		break;
+	case 9000000000ULL:
+		wrpll_params->central_freq = 1;
+		break;
+	case 8400000000ULL:
+		wrpll_params->central_freq = 3;
 	}
 
+	switch (candidate_p0[min_dco_index]) {
+	case 1:
+		wrpll_params->pdiv = 0;
+		break;
+	case 2:
+		wrpll_params->pdiv = 1;
+		break;
+	case 3:
+		wrpll_params->pdiv = 2;
+		break;
+	case 7:
+		wrpll_params->pdiv = 4;
+		break;
+	default:
+		WARN(1, "Incorrect PDiv\n");
+	}
+
+	switch (candidate_p2[min_dco_index]) {
+	case 5:
+		wrpll_params->kdiv = 0;
+		break;
+	case 2:
+		wrpll_params->kdiv = 1;
+		break;
+	case 3:
+		wrpll_params->kdiv = 2;
+		break;
+	case 1:
+		wrpll_params->kdiv = 3;
+		break;
+	default:
+		WARN(1, "Incorrect KDiv\n");
+	}
+
+	wrpll_params->qdiv_ratio = candidate_p1[min_dco_index];
+	wrpll_params->qdiv_mode =
+		(wrpll_params->qdiv_ratio == 1) ? 0 : 1;
+
+	dco_freq = candidate_p0[min_dco_index] *
+		candidate_p1[min_dco_index] *
+		candidate_p2[min_dco_index] * afe_clock;
+
+	/*
+	 * Intermediate values are in Hz.
+	 * Divide by MHz to match bsepc
+	 */
+	wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1)));
+	wrpll_params->dco_fraction =
+		div_u64(((div_u64(dco_freq, 24) -
+			  wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));
+
 	return true;
 }