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V4L/DVB (13584): DiBXXX0: fix most of the Codingstyle violations from the previous patch

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This patch changes most of the Codingstyle violations which were
introduced by the previous patch. Line length less that 80 chars are
not corrected.

Signed-off-by: Olivier Grenie <Olivier.Grenie@dibcom.fr>
Signed-off-by: Patrick Boettcher <pboettcher@kernellabs.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Olivier Grenie 2009-12-07 07:49:40 -03:00 committed by Mauro Carvalho Chehab
parent 03245a5ee6
commit 9c78303681
7 changed files with 379 additions and 374 deletions
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484
drivers/media/dvb/dvb-usb/dib0700_devices.c
View file

@ -131,93 +131,95 @@ static int bristol_tuner_attach(struct dvb_usb_adapter *adap)
/* MT226x */ /* MT226x */
static struct dibx000_agc_config stk7700d_7000p_mt2266_agc_config[2] = { static struct dibx000_agc_config stk7700d_7000p_mt2266_agc_config[2] = {
{ {
BAND_UHF, // band_caps BAND_UHF,
/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=1, P_agc_inv_pwm2=1, /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=1, P_agc_inv_pwm2=1,
* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */ * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */
(0 << 15) | (0 << 14) | (1 << 11) | (1 << 10) | (1 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), // setup (0 << 15) | (0 << 14) | (1 << 11) | (1 << 10) | (1 << 9) | (0 << 8)
| (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
1130, // inv_gain 1130,
21, // time_stabiliz 21,
0, // alpha_level 0,
118, // thlock 118,
0, // wbd_inv 0,
3530, // wbd_ref 3530,
1, // wbd_sel 1,
0, // wbd_alpha 0,
65535, // agc1_max 65535,
33770, // agc1_min 33770,
65535, // agc2_max 65535,
23592, // agc2_min 23592,
0, // agc1_pt1 0,
62, // agc1_pt2 62,
255, // agc1_pt3 255,
64, // agc1_slope1 64,
64, // agc1_slope2 64,
132, // agc2_pt1 132,
192, // agc2_pt2 192,
80, // agc2_slope1 80,
80, // agc2_slope2 80,
17, // alpha_mant 17,
27, // alpha_exp 27,
23, // beta_mant 23,
51, // beta_exp 51,
1, // perform_agc_softsplit 1,
}, { }, {
BAND_VHF | BAND_LBAND, // band_caps BAND_VHF | BAND_LBAND,
/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=1, P_agc_inv_pwm2=1, /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=1, P_agc_inv_pwm2=1,
* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */ * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */
(0 << 15) | (0 << 14) | (1 << 11) | (1 << 10) | (1 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), // setup (0 << 15) | (0 << 14) | (1 << 11) | (1 << 10) | (1 << 9) | (0 << 8)
| (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0),
2372, // inv_gain 2372,
21, // time_stabiliz 21,
0, // alpha_level 0,
118, // thlock 118,
0, // wbd_inv 0,
3530, // wbd_ref 3530,
1, // wbd_sel 1,
0, // wbd_alpha 0,
65535, // agc1_max 65535,
0, // agc1_min 0,
65535, // agc2_max 65535,
23592, // agc2_min 23592,
0, // agc1_pt1 0,
128, // agc1_pt2 128,
128, // agc1_pt3 128,
128, // agc1_slope1 128,
0, // agc1_slope2 0,
128, // agc2_pt1 128,
253, // agc2_pt2 253,
81, // agc2_slope1 81,
0, // agc2_slope2 0,
17, // alpha_mant 17,
27, // alpha_exp 27,
23, // beta_mant 23,
51, // beta_exp 51,
1, // perform_agc_softsplit 1,
} }
}; };
static struct dibx000_bandwidth_config stk7700d_mt2266_pll_config = { static struct dibx000_bandwidth_config stk7700d_mt2266_pll_config = {
60000, 30000, // internal, sampling 60000, 30000,
1, 8, 3, 1, 0, // pll_cfg: prediv, ratio, range, reset, bypass 1, 8, 3, 1, 0,
0, 0, 1, 1, 2, // misc: refdiv, bypclk_div, IO_CLK_en_core, ADClkSrc, modulo 0, 0, 1, 1, 2,
(3 << 14) | (1 << 12) | (524 << 0), // sad_cfg: refsel, sel, freq_15k (3 << 14) | (1 << 12) | (524 << 0),
0, // ifreq 0,
20452225, // timf 20452225,
}; };
static struct dib7000p_config stk7700d_dib7000p_mt2266_config[] = { static struct dib7000p_config stk7700d_dib7000p_mt2266_config[] = {
@ -934,47 +936,48 @@ static struct dvb_usb_rc_key dib0700_rc_keys[] = {
/* STK7700P: Hauppauge Nova-T Stick, AVerMedia Volar */ /* STK7700P: Hauppauge Nova-T Stick, AVerMedia Volar */
static struct dibx000_agc_config stk7700p_7000m_mt2060_agc_config = { static struct dibx000_agc_config stk7700p_7000m_mt2060_agc_config = {
BAND_UHF | BAND_VHF, // band_caps BAND_UHF | BAND_VHF,
/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */ * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */
(0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), // setup (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
| (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0),
712, // inv_gain 712,
41, // time_stabiliz 41,
0, // alpha_level 0,
118, // thlock 118,
0, // wbd_inv 0,
4095, // wbd_ref 4095,
0, // wbd_sel 0,
0, // wbd_alpha 0,
42598, // agc1_max 42598,
17694, // agc1_min 17694,
45875, // agc2_max 45875,
2621, // agc2_min 2621,
0, // agc1_pt1 0,
76, // agc1_pt2 76,
139, // agc1_pt3 139,
52, // agc1_slope1 52,
59, // agc1_slope2 59,
107, // agc2_pt1 107,
172, // agc2_pt2 172,
57, // agc2_slope1 57,
70, // agc2_slope2 70,
21, // alpha_mant 21,
25, // alpha_exp 25,
28, // beta_mant 28,
48, // beta_exp 48,
1, // perform_agc_softsplit 1,
{ 0, // split_min { 0,
107, // split_max 107,
51800, // global_split_min 51800,
24700 // global_split_max 24700
}, },
}; };
@ -983,54 +986,55 @@ static struct dibx000_agc_config stk7700p_7000p_mt2060_agc_config = {
/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */ * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */
(0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), // setup (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
| (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0),
712, // inv_gain 712,
41, // time_stabiliz 41,
0, // alpha_level 0,
118, // thlock 118,
0, // wbd_inv 0,
4095, // wbd_ref 4095,
0, // wbd_sel 0,
0, // wbd_alpha 0,
42598, // agc1_max 42598,
16384, // agc1_min 16384,
42598, // agc2_max 42598,
0, // agc2_min 0,
0, // agc1_pt1 0,
137, // agc1_pt2 137,
255, // agc1_pt3 255,
0, // agc1_slope1 0,
255, // agc1_slope2 255,
0, // agc2_pt1 0,
0, // agc2_pt2 0,
0, // agc2_slope1 0,
41, // agc2_slope2 41,
15, // alpha_mant 15,
25, // alpha_exp 25,
28, // beta_mant 28,
48, // beta_exp 48,
0, // perform_agc_softsplit 0,
}; };
static struct dibx000_bandwidth_config stk7700p_pll_config = { static struct dibx000_bandwidth_config stk7700p_pll_config = {
60000, 30000, // internal, sampling 60000, 30000,
1, 8, 3, 1, 0, // pll_cfg: prediv, ratio, range, reset, bypass 1, 8, 3, 1, 0,
0, 0, 1, 1, 0, // misc: refdiv, bypclk_div, IO_CLK_en_core, ADClkSrc, modulo 0, 0, 1, 1, 0,
(3 << 14) | (1 << 12) | (524 << 0), // sad_cfg: refsel, sel, freq_15k (3 << 14) | (1 << 12) | (524 << 0),
60258167, // ifreq 60258167,
20452225, // timf 20452225,
30000000, // xtal 30000000,
}; };
static struct dib7000m_config stk7700p_dib7000m_config = { static struct dib7000m_config stk7700p_dib7000m_config = {
@ -1116,41 +1120,42 @@ static struct dibx000_agc_config dib7070_agc_config = {
BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND, BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND,
/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */ * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
(0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), // setup (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
| (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
600, // inv_gain 600,
10, // time_stabiliz 10,
0, // alpha_level 0,
118, // thlock 118,
0, // wbd_inv 0,
3530, // wbd_ref 3530,
1, // wbd_sel 1,
5, // wbd_alpha 5,
65535, // agc1_max 65535,
0, // agc1_min 0,
65535, // agc2_max 65535,
0, // agc2_min 0,
0, // agc1_pt1 0,
40, // agc1_pt2 40,
183, // agc1_pt3 183,
206, // agc1_slope1 206,
255, // agc1_slope2 255,
72, // agc2_pt1 72,
152, // agc2_pt2 152,
88, // agc2_slope1 88,
90, // agc2_slope2 90,
17, // alpha_mant 17,
27, // alpha_exp 27,
23, // beta_mant 23,
51, // beta_exp 51,
0, // perform_agc_softsplit 0,
}; };
static int dib7070_tuner_reset(struct dvb_frontend *fe, int onoff) static int dib7070_tuner_reset(struct dvb_frontend *fe, int onoff)
@ -1277,13 +1282,13 @@ static int stk70x0p_pid_filter_ctrl(struct dvb_usb_adapter *adapter, int onoff)
} }
static struct dibx000_bandwidth_config dib7070_bw_config_12_mhz = { static struct dibx000_bandwidth_config dib7070_bw_config_12_mhz = {
60000, 15000, // internal, sampling 60000, 15000,
1, 20, 3, 1, 0, // pll_cfg: prediv, ratio, range, reset, bypass 1, 20, 3, 1, 0,
0, 0, 1, 1, 2, // misc: refdiv, bypclk_div, IO_CLK_en_core, ADClkSrc, modulo 0, 0, 1, 1, 2,
(3 << 14) | (1 << 12) | (524 << 0), // sad_cfg: refsel, sel, freq_15k (3 << 14) | (1 << 12) | (524 << 0),
(0 << 25) | 0, // ifreq = 0.000000 MHz (0 << 25) | 0,
20452225, // timf 20452225,
12000000, // xtal_hz 12000000,
}; };
static struct dib7000p_config dib7070p_dib7000p_config = { static struct dib7000p_config dib7070p_dib7000p_config = {
@ -1567,12 +1572,14 @@ static int dib807x_tuner_attach(struct dvb_usb_adapter *adap)
return 0; return 0;
} }
static int stk80xx_pid_filter(struct dvb_usb_adapter *adapter, int index, u16 pid, int onoff) static int stk80xx_pid_filter(struct dvb_usb_adapter *adapter, int index,
u16 pid, int onoff)
{ {
return dib8000_pid_filter(adapter->fe, index, pid, onoff); return dib8000_pid_filter(adapter->fe, index, pid, onoff);
} }
static int stk80xx_pid_filter_ctrl(struct dvb_usb_adapter *adapter, int onoff) static int stk80xx_pid_filter_ctrl(struct dvb_usb_adapter *adapter,
int onoff)
{ {
return dib8000_pid_filter_ctrl(adapter->fe, onoff); return dib8000_pid_filter_ctrl(adapter->fe, onoff);
} }
@ -1648,94 +1655,98 @@ static int stk807xpvr_frontend_attach1(struct dvb_usb_adapter *adap)
struct dibx000_agc_config dib8090_agc_config[2] = { struct dibx000_agc_config dib8090_agc_config[2] = {
{ {
BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND, BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND,
/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1,
* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */ * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
(0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), // setup * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
(0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
| (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
787,// inv_gain = 1/ 90.4dB // no boost, lower gain due to ramp quantification 787,
10, // time_stabiliz 10,
0, // alpha_level 0,
118, // thlock 118,
0, // wbd_inv 0,
3530, // wbd_ref 3530,
1, // wbd_sel 1,
5, // wbd_alpha 5,
65535, // agc1_max 65535,
0, // agc1_min 0,
65535, // agc2_max 65535,
0, // agc2_min 0,
0, // agc1_pt1 0,
32, // agc1_pt2 32,
114, // agc1_pt3 // 40.4dB 114,
143, // agc1_slope1 143,
144, // agc1_slope2 144,
114, // agc2_pt1 114,
227, // agc2_pt2 227,
116, // agc2_slope1 116,
117, // agc2_slope2 117,
28, // alpha_mant // 5Hz with 90.2dB 28,
26, // alpha_exp 26,
31, // beta_mant 31,
51, // beta_exp 51,
0, // perform_agc_softsplit 0,
}, },
{ {
BAND_CBAND, BAND_CBAND,
/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1,
* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */ * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
(0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), // setup * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
(0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
| (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
787,// inv_gain = 1/ 90.4dB // no boost, lower gain due to ramp quantification 787,
10, // time_stabiliz 10,
0, // alpha_level 0,
118, // thlock 118,
0, // wbd_inv 0,
3530, // wbd_ref 3530,
1, // wbd_sel 1,
5, // wbd_alpha 5,
0, // agc1_max 0,
0, // agc1_min 0,
65535, // agc2_max 65535,
0, // agc2_min 0,
0, // agc1_pt1 0,
32, // agc1_pt2 32,
114, // agc1_pt3 // 40.4dB 114,
143, // agc1_slope1 143,
144, // agc1_slope2 144,
114, // agc2_pt1 114,
227, // agc2_pt2 227,
116, // agc2_slope1 116,
117, // agc2_slope2 117,
28, // alpha_mant // 5Hz with 90.2dB 28,
26, // alpha_exp 26,
31, // beta_mant 31,
51, // beta_exp 51,
0, // perform_agc_softsplit 0,
} }
}; };
static struct dibx000_bandwidth_config dib8090_pll_config_12mhz = { static struct dibx000_bandwidth_config dib8090_pll_config_12mhz = {
54000, 13500, // internal, sampling 54000, 13500,
1, 18, 3, 1, 0, // pll_cfg: prediv, ratio, range, reset, bypass 1, 18, 3, 1, 0,
0, 0, 1, 1, 2, // misc: refdiv, bypclk_div, IO_CLK_en_core, ADClkSrc, modulo 0, 0, 1, 1, 2,
(3 << 14) | (1 << 12) | (599 << 0), // sad_cfg: refsel, sel, freq_15k (3 << 14) | (1 << 12) | (599 << 0),
(0 << 25) | 0, // ifreq = 0 MHz (0 << 25) | 0,
20199727, // timf 20199727,
12000000, // xtal_hz 12000000,
}; };
static int dib8090_get_adc_power(struct dvb_frontend *fe) static int dib8090_get_adc_power(struct dvb_frontend *fe)
@ -1816,31 +1827,26 @@ static int dib8096_set_param_override(struct dvb_frontend *fe,
dib8000_set_wbd_ref(fe, offset); dib8000_set_wbd_ref(fe, offset);
if (band == BAND_CBAND) if (band == BAND_CBAND) {
{
deb_info("tuning in CBAND - soft-AGC startup\n"); deb_info("tuning in CBAND - soft-AGC startup\n");
/* TODO specific wbd target for dib0090 - needed for startup ? */ /* TODO specific wbd target for dib0090 - needed for startup ? */
dib0090_set_tune_state(fe, CT_AGC_START); dib0090_set_tune_state(fe, CT_AGC_START);
do do {
{
ret = dib0090_gain_control(fe); ret = dib0090_gain_control(fe);
msleep(ret); msleep(ret);
tune_state = dib0090_get_tune_state(fe); tune_state = dib0090_get_tune_state(fe);
if (tune_state == CT_AGC_STEP_0) if (tune_state == CT_AGC_STEP_0)
dib8000_set_gpio(fe, 6, 0, 1); dib8000_set_gpio(fe, 6, 0, 1);
else if (tune_state == CT_AGC_STEP_1) else if (tune_state == CT_AGC_STEP_1) {
{
dib0090_get_current_gain(fe, NULL, NULL, &rf_gain_limit, &ltgain); dib0090_get_current_gain(fe, NULL, NULL, &rf_gain_limit, &ltgain);
if (rf_gain_limit == 0) if (rf_gain_limit == 0)
dib8000_set_gpio(fe, 6, 0, 0); dib8000_set_gpio(fe, 6, 0, 0);
} }
} } while (tune_state < CT_AGC_STOP);
while(tune_state<CT_AGC_STOP);
dib0090_pwm_gain_reset(fe); dib0090_pwm_gain_reset(fe);
dib8000_pwm_agc_reset(fe); dib8000_pwm_agc_reset(fe);
dib8000_set_tune_state(fe, CT_DEMOD_START); dib8000_set_tune_state(fe, CT_DEMOD_START);
} } else {
else {
deb_info("not tuning in CBAND - standard AGC startup\n"); deb_info("not tuning in CBAND - standard AGC startup\n");
dib0090_pwm_gain_reset(fe); dib0090_pwm_gain_reset(fe);
} }

18
drivers/media/dvb/frontends/dib0070.c
View file

@ -291,7 +291,7 @@ static const struct dib0070_lna_match dib0070_lna[] = {
{ 0xffffffff, 7 }, { 0xffffffff, 7 },
}; };
#define LPF 100 // define for the loop filter 100kHz by default 16-07-06 #define LPF 100
static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch) static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch)
{ {
struct dib0070_state *state = fe->tuner_priv; struct dib0070_state *state = fe->tuner_priv;
@ -440,9 +440,9 @@ static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_par
while (freq/1000 > tmp->freq) /* find the right one */ while (freq/1000 > tmp->freq) /* find the right one */
tmp++; tmp++;
dib0070_write_reg(state, 0x0f, dib0070_write_reg(state, 0x0f,
(0 << 15) | (1 << 14) | (3 << 12) | (tmp->wbd_gain_val << 9) | (0 << 8) | (1 << 7) | (state-> (0 << 15) | (1 << 14) | (3 << 12)
current_tune_table_index-> | (tmp->wbd_gain_val << 9) | (0 << 8) | (1 << 7)
wbdmux << 0)); | (state->current_tune_table_index->wbdmux << 0));
state->wbd_gain_current = tmp->wbd_gain_val; state->wbd_gain_current = tmp->wbd_gain_val;
} else { } else {
dib0070_write_reg(state, 0x0f, dib0070_write_reg(state, 0x0f,
@ -512,18 +512,20 @@ u8 dib0070_get_rf_output(struct dvb_frontend *fe)
struct dib0070_state *state = fe->tuner_priv; struct dib0070_state *state = fe->tuner_priv;
return (dib0070_read_reg(state, 0x07) >> 11) & 0x3; return (dib0070_read_reg(state, 0x07) >> 11) & 0x3;
} }
EXPORT_SYMBOL(dib0070_get_rf_output); EXPORT_SYMBOL(dib0070_get_rf_output);
int dib0070_set_rf_output(struct dvb_frontend *fe, u8 no) int dib0070_set_rf_output(struct dvb_frontend *fe, u8 no)
{ {
struct dib0070_state *state = fe->tuner_priv; struct dib0070_state *state = fe->tuner_priv;
u16 rxrf2 = dib0070_read_reg(state, 0x07) & 0xfe7ff; u16 rxrf2 = dib0070_read_reg(state, 0x07) & 0xfe7ff;
if (no > 3) no = 3; if (no > 3)
if (no < 1) no = 1; no = 3;
if (no < 1)
no = 1;
return dib0070_write_reg(state, 0x07, rxrf2 | (no << 11)); return dib0070_write_reg(state, 0x07, rxrf2 | (no << 11));
} }
EXPORT_SYMBOL(dib0070_set_rf_output); EXPORT_SYMBOL(dib0070_set_rf_output);
static const u16 dib0070_p1f_defaults[] = static const u16 dib0070_p1f_defaults[] =
{ {

19
drivers/media/dvb/frontends/dib0090.c
View file

@ -287,12 +287,12 @@ extern void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast)
{ {
struct dib0090_state *state = fe->tuner_priv; struct dib0090_state *state = fe->tuner_priv;
if (fast) if (fast)
dib0090_write_reg(state, 0x04, 0); //1kHz dib0090_write_reg(state, 0x04, 0);
else else
dib0090_write_reg(state, 0x04, 1); //almost frozen dib0090_write_reg(state, 0x04, 1);
} }
EXPORT_SYMBOL(dib0090_dcc_freq); EXPORT_SYMBOL(dib0090_dcc_freq);
static const u16 rf_ramp_pwm_cband[] = { static const u16 rf_ramp_pwm_cband[] = {
0, /* max RF gain in 10th of dB */ 0, /* max RF gain in 10th of dB */
0, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */ 0, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */
@ -616,11 +616,11 @@ void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
else else
dib0090_write_reg(state, 0x32, (0 << 11)); dib0090_write_reg(state, 0x32, (0 << 11));
dib0090_write_reg(state, 0x39, (1 << 10)); // 0 gain by default dib0090_write_reg(state, 0x39, (1 << 10));
} }
} }
EXPORT_SYMBOL(dib0090_pwm_gain_reset); EXPORT_SYMBOL(dib0090_pwm_gain_reset);
int dib0090_gain_control(struct dvb_frontend *fe) int dib0090_gain_control(struct dvb_frontend *fe)
{ {
struct dib0090_state *state = fe->tuner_priv; struct dib0090_state *state = fe->tuner_priv;
@ -770,8 +770,8 @@ int dib0090_gain_control(struct dvb_frontend *fe)
dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly); dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly);
return ret; return ret;
} }
EXPORT_SYMBOL(dib0090_gain_control); EXPORT_SYMBOL(dib0090_gain_control);
void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt) void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt)
{ {
struct dib0090_state *state = fe->tuner_priv; struct dib0090_state *state = fe->tuner_priv;
@ -784,15 +784,15 @@ void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 *
if (rflt) if (rflt)
*rflt = (state->rf_lt_def >> 10) & 0x7; *rflt = (state->rf_lt_def >> 10) & 0x7;
} }
EXPORT_SYMBOL(dib0090_get_current_gain); EXPORT_SYMBOL(dib0090_get_current_gain);
u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner) u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner)
{ {
struct dib0090_state *st = tuner->tuner_priv; struct dib0090_state *st = tuner->tuner_priv;
return st->wbd_offset; return st->wbd_offset;
} }
EXPORT_SYMBOL(dib0090_get_wbd_offset); EXPORT_SYMBOL(dib0090_get_wbd_offset);
static const u16 dib0090_defaults[] = { static const u16 dib0090_defaults[] = {
25, 0x01, 25, 0x01,
@ -1439,7 +1439,6 @@ enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe)
return state->tune_state; return state->tune_state;
} }
EXPORT_SYMBOL(dib0090_get_tune_state); EXPORT_SYMBOL(dib0090_get_tune_state);
int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state) int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
@ -1449,7 +1448,6 @@ int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tun
state->tune_state = tune_state; state->tune_state = tune_state;
return 0; return 0;
} }
EXPORT_SYMBOL(dib0090_set_tune_state); EXPORT_SYMBOL(dib0090_set_tune_state);
static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency) static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency)
@ -1516,7 +1514,6 @@ struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapte
fe->tuner_priv = NULL; fe->tuner_priv = NULL;
return NULL; return NULL;
} }
EXPORT_SYMBOL(dib0090_register); EXPORT_SYMBOL(dib0090_register);
MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>"); MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");

2
drivers/media/dvb/frontends/dib0090.h
View file

@ -24,7 +24,7 @@ struct dib0090_io_config {
u8 pll_loopdiv:6; u8 pll_loopdiv:6;
u8 adc_clock_ratio; /* valid is 8, 7 ,6 */ u8 adc_clock_ratio; /* valid is 8, 7 ,6 */
u16 pll_int_loop_filt; // internal loop filt value. If not fill in , default is 8165 u16 pll_int_loop_filt;
}; };
struct dib0090_config { struct dib0090_config {