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V4L/DVB (13584): DiBXXX0: fix most of the Codingstyle violations from the previous patch

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This patch changes most of the Codingstyle violations which were
introduced by the previous patch. Line length less that 80 chars are
not corrected.

Signed-off-by: Olivier Grenie <Olivier.Grenie@dibcom.fr>
Signed-off-by: Patrick Boettcher <pboettcher@kernellabs.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Olivier Grenie 2009-12-07 07:49:40 -03:00 committed by Mauro Carvalho Chehab
parent 03245a5ee6
commit 9c78303681
7 changed files with 379 additions and 374 deletions
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508
drivers/media/dvb/dvb-usb/dib0700_devices.c
View file

@ -131,93 +131,95 @@ static int bristol_tuner_attach(struct dvb_usb_adapter *adap)
/* MT226x */ /* MT226x */
static struct dibx000_agc_config stk7700d_7000p_mt2266_agc_config[2] = { static struct dibx000_agc_config stk7700d_7000p_mt2266_agc_config[2] = {
{ {
BAND_UHF, // band_caps BAND_UHF,
/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=1, P_agc_inv_pwm2=1, /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=1, P_agc_inv_pwm2=1,
* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */ * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */
(0 << 15) | (0 << 14) | (1 << 11) | (1 << 10) | (1 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), // setup (0 << 15) | (0 << 14) | (1 << 11) | (1 << 10) | (1 << 9) | (0 << 8)
| (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
1130, // inv_gain 1130,
21, // time_stabiliz 21,
0, // alpha_level 0,
118, // thlock 118,
0, // wbd_inv 0,
3530, // wbd_ref 3530,
1, // wbd_sel 1,
0, // wbd_alpha 0,
65535, // agc1_max 65535,
33770, // agc1_min 33770,
65535, // agc2_max 65535,
23592, // agc2_min 23592,
0, // agc1_pt1 0,
62, // agc1_pt2 62,
255, // agc1_pt3 255,
64, // agc1_slope1 64,
64, // agc1_slope2 64,
132, // agc2_pt1 132,
192, // agc2_pt2 192,
80, // agc2_slope1 80,
80, // agc2_slope2 80,
17, // alpha_mant 17,
27, // alpha_exp 27,
23, // beta_mant 23,
51, // beta_exp 51,
1, // perform_agc_softsplit 1,
}, { }, {
BAND_VHF | BAND_LBAND, // band_caps BAND_VHF | BAND_LBAND,
/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=1, P_agc_inv_pwm2=1, /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=1, P_agc_inv_pwm2=1,
* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */ * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */
(0 << 15) | (0 << 14) | (1 << 11) | (1 << 10) | (1 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), // setup (0 << 15) | (0 << 14) | (1 << 11) | (1 << 10) | (1 << 9) | (0 << 8)
| (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0),
2372, // inv_gain 2372,
21, // time_stabiliz 21,
0, // alpha_level 0,
118, // thlock 118,
0, // wbd_inv 0,
3530, // wbd_ref 3530,
1, // wbd_sel 1,
0, // wbd_alpha 0,
65535, // agc1_max 65535,
0, // agc1_min 0,
65535, // agc2_max 65535,
23592, // agc2_min 23592,
0, // agc1_pt1 0,
128, // agc1_pt2 128,
128, // agc1_pt3 128,
128, // agc1_slope1 128,
0, // agc1_slope2 0,
128, // agc2_pt1 128,
253, // agc2_pt2 253,
81, // agc2_slope1 81,
0, // agc2_slope2 0,
17, // alpha_mant 17,
27, // alpha_exp 27,
23, // beta_mant 23,
51, // beta_exp 51,
1, // perform_agc_softsplit 1,
} }
}; };
static struct dibx000_bandwidth_config stk7700d_mt2266_pll_config = { static struct dibx000_bandwidth_config stk7700d_mt2266_pll_config = {
60000, 30000, // internal, sampling 60000, 30000,
1, 8, 3, 1, 0, // pll_cfg: prediv, ratio, range, reset, bypass 1, 8, 3, 1, 0,
0, 0, 1, 1, 2, // misc: refdiv, bypclk_div, IO_CLK_en_core, ADClkSrc, modulo 0, 0, 1, 1, 2,
(3 << 14) | (1 << 12) | (524 << 0), // sad_cfg: refsel, sel, freq_15k (3 << 14) | (1 << 12) | (524 << 0),
0, // ifreq 0,
20452225, // timf 20452225,
}; };
static struct dib7000p_config stk7700d_dib7000p_mt2266_config[] = { static struct dib7000p_config stk7700d_dib7000p_mt2266_config[] = {
@ -934,47 +936,48 @@ static struct dvb_usb_rc_key dib0700_rc_keys[] = {
/* STK7700P: Hauppauge Nova-T Stick, AVerMedia Volar */ /* STK7700P: Hauppauge Nova-T Stick, AVerMedia Volar */
static struct dibx000_agc_config stk7700p_7000m_mt2060_agc_config = { static struct dibx000_agc_config stk7700p_7000m_mt2060_agc_config = {
BAND_UHF | BAND_VHF, // band_caps BAND_UHF | BAND_VHF,
/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */ * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */
(0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), // setup (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
| (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0),
712, // inv_gain 712,
41, // time_stabiliz 41,
0, // alpha_level 0,
118, // thlock 118,
0, // wbd_inv 0,
4095, // wbd_ref 4095,
0, // wbd_sel 0,
0, // wbd_alpha 0,
42598, // agc1_max 42598,
17694, // agc1_min 17694,
45875, // agc2_max 45875,
2621, // agc2_min 2621,
0, // agc1_pt1 0,
76, // agc1_pt2 76,
139, // agc1_pt3 139,
52, // agc1_slope1 52,
59, // agc1_slope2 59,
107, // agc2_pt1 107,
172, // agc2_pt2 172,
57, // agc2_slope1 57,
70, // agc2_slope2 70,
21, // alpha_mant 21,
25, // alpha_exp 25,
28, // beta_mant 28,
48, // beta_exp 48,
1, // perform_agc_softsplit 1,
{ 0, // split_min { 0,
107, // split_max 107,
51800, // global_split_min 51800,
24700 // global_split_max 24700
}, },
}; };
@ -983,54 +986,55 @@ static struct dibx000_agc_config stk7700p_7000p_mt2060_agc_config = {
/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */ * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */
(0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), // setup (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
| (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0),
712, // inv_gain 712,
41, // time_stabiliz 41,
0, // alpha_level 0,
118, // thlock 118,
0, // wbd_inv 0,
4095, // wbd_ref 4095,
0, // wbd_sel 0,
0, // wbd_alpha 0,
42598, // agc1_max 42598,
16384, // agc1_min 16384,
42598, // agc2_max 42598,
0, // agc2_min 0,
0, // agc1_pt1 0,
137, // agc1_pt2 137,
255, // agc1_pt3 255,
0, // agc1_slope1 0,
255, // agc1_slope2 255,
0, // agc2_pt1 0,
0, // agc2_pt2 0,
0, // agc2_slope1 0,
41, // agc2_slope2 41,
15, // alpha_mant 15,
25, // alpha_exp 25,
28, // beta_mant 28,
48, // beta_exp 48,
0, // perform_agc_softsplit 0,
}; };
static struct dibx000_bandwidth_config stk7700p_pll_config = { static struct dibx000_bandwidth_config stk7700p_pll_config = {
60000, 30000, // internal, sampling 60000, 30000,
1, 8, 3, 1, 0, // pll_cfg: prediv, ratio, range, reset, bypass 1, 8, 3, 1, 0,
0, 0, 1, 1, 0, // misc: refdiv, bypclk_div, IO_CLK_en_core, ADClkSrc, modulo 0, 0, 1, 1, 0,
(3 << 14) | (1 << 12) | (524 << 0), // sad_cfg: refsel, sel, freq_15k (3 << 14) | (1 << 12) | (524 << 0),
60258167, // ifreq 60258167,
20452225, // timf 20452225,
30000000, // xtal 30000000,
}; };
static struct dib7000m_config stk7700p_dib7000m_config = { static struct dib7000m_config stk7700p_dib7000m_config = {
@ -1116,41 +1120,42 @@ static struct dibx000_agc_config dib7070_agc_config = {
BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND, BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND,
/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */ * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
(0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), // setup (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
| (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
600, // inv_gain 600,
10, // time_stabiliz 10,
0, // alpha_level 0,
118, // thlock 118,
0, // wbd_inv 0,
3530, // wbd_ref 3530,
1, // wbd_sel 1,
5, // wbd_alpha 5,
65535, // agc1_max 65535,
0, // agc1_min 0,
65535, // agc2_max 65535,
0, // agc2_min 0,
0, // agc1_pt1 0,
40, // agc1_pt2 40,
183, // agc1_pt3 183,
206, // agc1_slope1 206,
255, // agc1_slope2 255,
72, // agc2_pt1 72,
152, // agc2_pt2 152,
88, // agc2_slope1 88,
90, // agc2_slope2 90,
17, // alpha_mant 17,
27, // alpha_exp 27,
23, // beta_mant 23,
51, // beta_exp 51,
0, // perform_agc_softsplit 0,
}; };
static int dib7070_tuner_reset(struct dvb_frontend *fe, int onoff) static int dib7070_tuner_reset(struct dvb_frontend *fe, int onoff)
@ -1277,13 +1282,13 @@ static int stk70x0p_pid_filter_ctrl(struct dvb_usb_adapter *adapter, int onoff)
} }
static struct dibx000_bandwidth_config dib7070_bw_config_12_mhz = { static struct dibx000_bandwidth_config dib7070_bw_config_12_mhz = {
60000, 15000, // internal, sampling 60000, 15000,
1, 20, 3, 1, 0, // pll_cfg: prediv, ratio, range, reset, bypass 1, 20, 3, 1, 0,
0, 0, 1, 1, 2, // misc: refdiv, bypclk_div, IO_CLK_en_core, ADClkSrc, modulo 0, 0, 1, 1, 2,
(3 << 14) | (1 << 12) | (524 << 0), // sad_cfg: refsel, sel, freq_15k (3 << 14) | (1 << 12) | (524 << 0),
(0 << 25) | 0, // ifreq = 0.000000 MHz (0 << 25) | 0,
20452225, // timf 20452225,
12000000, // xtal_hz 12000000,
}; };
static struct dib7000p_config dib7070p_dib7000p_config = { static struct dib7000p_config dib7070p_dib7000p_config = {
@ -1567,12 +1572,14 @@ static int dib807x_tuner_attach(struct dvb_usb_adapter *adap)
return 0; return 0;
} }
static int stk80xx_pid_filter(struct dvb_usb_adapter *adapter, int index, u16 pid, int onoff) static int stk80xx_pid_filter(struct dvb_usb_adapter *adapter, int index,
u16 pid, int onoff)
{ {
return dib8000_pid_filter(adapter->fe, index, pid, onoff); return dib8000_pid_filter(adapter->fe, index, pid, onoff);
} }
static int stk80xx_pid_filter_ctrl(struct dvb_usb_adapter *adapter, int onoff) static int stk80xx_pid_filter_ctrl(struct dvb_usb_adapter *adapter,
int onoff)
{ {
return dib8000_pid_filter_ctrl(adapter->fe, onoff); return dib8000_pid_filter_ctrl(adapter->fe, onoff);
} }
@ -1648,94 +1655,98 @@ static int stk807xpvr_frontend_attach1(struct dvb_usb_adapter *adap)
struct dibx000_agc_config dib8090_agc_config[2] = { struct dibx000_agc_config dib8090_agc_config[2] = {
{ {
BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND, BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND,
/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1,
* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */ * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
(0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), // setup * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
(0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
| (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
787,// inv_gain = 1/ 90.4dB // no boost, lower gain due to ramp quantification 787,
10, // time_stabiliz 10,
0, // alpha_level 0,
118, // thlock 118,
0, // wbd_inv 0,
3530, // wbd_ref 3530,
1, // wbd_sel 1,
5, // wbd_alpha 5,
65535, // agc1_max 65535,
0, // agc1_min 0,
65535, // agc2_max 65535,
0, // agc2_min 0,
0, // agc1_pt1 0,
32, // agc1_pt2 32,
114, // agc1_pt3 // 40.4dB 114,
143, // agc1_slope1 143,
144, // agc1_slope2 144,
114, // agc2_pt1 114,
227, // agc2_pt2 227,
116, // agc2_slope1 116,
117, // agc2_slope2 117,
28, // alpha_mant // 5Hz with 90.2dB 28,
26, // alpha_exp 26,
31, // beta_mant 31,
51, // beta_exp 51,
0, // perform_agc_softsplit 0,
}, },
{ {
BAND_CBAND, BAND_CBAND,
/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1,
* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */ * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
(0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), // setup * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
(0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
| (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
787,// inv_gain = 1/ 90.4dB // no boost, lower gain due to ramp quantification 787,
10, // time_stabiliz 10,
0, // alpha_level 0,
118, // thlock 118,
0, // wbd_inv 0,
3530, // wbd_ref 3530,
1, // wbd_sel 1,
5, // wbd_alpha 5,
0, // agc1_max 0,
0, // agc1_min 0,
65535, // agc2_max 65535,
0, // agc2_min 0,
0, // agc1_pt1 0,
32, // agc1_pt2 32,
114, // agc1_pt3 // 40.4dB 114,
143, // agc1_slope1 143,
144, // agc1_slope2 144,
114, // agc2_pt1 114,
227, // agc2_pt2 227,
116, // agc2_slope1 116,
117, // agc2_slope2 117,
28, // alpha_mant // 5Hz with 90.2dB 28,
26, // alpha_exp 26,
31, // beta_mant 31,
51, // beta_exp 51,
0, // perform_agc_softsplit 0,
} }
}; };
static struct dibx000_bandwidth_config dib8090_pll_config_12mhz = { static struct dibx000_bandwidth_config dib8090_pll_config_12mhz = {
54000, 13500, // internal, sampling 54000, 13500,
1, 18, 3, 1, 0, // pll_cfg: prediv, ratio, range, reset, bypass 1, 18, 3, 1, 0,
0, 0, 1, 1, 2, // misc: refdiv, bypclk_div, IO_CLK_en_core, ADClkSrc, modulo 0, 0, 1, 1, 2,
(3 << 14) | (1 << 12) | (599 << 0), // sad_cfg: refsel, sel, freq_15k (3 << 14) | (1 << 12) | (599 << 0),
(0 << 25) | 0, // ifreq = 0 MHz (0 << 25) | 0,
20199727, // timf 20199727,
12000000, // xtal_hz 12000000,
}; };
static int dib8090_get_adc_power(struct dvb_frontend *fe) static int dib8090_get_adc_power(struct dvb_frontend *fe)
@ -1802,13 +1813,13 @@ static int dib8096_set_param_override(struct dvb_frontend *fe,
return ret; return ret;
switch (band) { switch (band) {
case BAND_VHF: case BAND_VHF:
offset = 100; offset = 100;
break; break;
case BAND_UHF: case BAND_UHF:
offset = 550; offset = 550;
break; break;
default: default:
offset = 0; offset = 0;
break; break;
} }
@ -1816,31 +1827,26 @@ static int dib8096_set_param_override(struct dvb_frontend *fe,
dib8000_set_wbd_ref(fe, offset); dib8000_set_wbd_ref(fe, offset);
if (band == BAND_CBAND) if (band == BAND_CBAND) {
{
deb_info("tuning in CBAND - soft-AGC startup\n"); deb_info("tuning in CBAND - soft-AGC startup\n");
/* TODO specific wbd target for dib0090 - needed for startup ? */ /* TODO specific wbd target for dib0090 - needed for startup ? */
dib0090_set_tune_state(fe, CT_AGC_START); dib0090_set_tune_state(fe, CT_AGC_START);
do do {
{ ret = dib0090_gain_control(fe);
ret = dib0090_gain_control(fe); msleep(ret);
msleep(ret); tune_state = dib0090_get_tune_state(fe);
tune_state = dib0090_get_tune_state(fe); if (tune_state == CT_AGC_STEP_0)
if (tune_state == CT_AGC_STEP_0) dib8000_set_gpio(fe, 6, 0, 1);
dib8000_set_gpio(fe, 6, 0, 1); else if (tune_state == CT_AGC_STEP_1) {
else if (tune_state == CT_AGC_STEP_1) dib0090_get_current_gain(fe, NULL, NULL, &rf_gain_limit, &ltgain);
{ if (rf_gain_limit == 0)
dib0090_get_current_gain(fe, NULL, NULL, &rf_gain_limit, &ltgain); dib8000_set_gpio(fe, 6, 0, 0);
if (rf_gain_limit == 0) }
dib8000_set_gpio(fe, 6, 0, 0); } while (tune_state < CT_AGC_STOP);
}
}
while(tune_state<CT_AGC_STOP);
dib0090_pwm_gain_reset(fe); dib0090_pwm_gain_reset(fe);
dib8000_pwm_agc_reset(fe); dib8000_pwm_agc_reset(fe);
dib8000_set_tune_state(fe, CT_DEMOD_START); dib8000_set_tune_state(fe, CT_DEMOD_START);
} } else {
else {
deb_info("not tuning in CBAND - standard AGC startup\n"); deb_info("not tuning in CBAND - standard AGC startup\n");
dib0090_pwm_gain_reset(fe); dib0090_pwm_gain_reset(fe);
} }

188
drivers/media/dvb/frontends/dib0070.c
View file

@ -163,7 +163,7 @@ static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state
adc = dib0070_read_reg(state, 0x19); adc = dib0070_read_reg(state, 0x19);
dprintk( "CAPTRIM=%hd; ADC = %hd (ADC) & %dmV", state->captrim, adc, (u32) adc*(u32)1800/(u32)1024); dprintk("CAPTRIM=%hd; ADC = %hd (ADC) & %dmV", state->captrim, adc, (u32) adc*(u32)1800/(u32)1024);
if (adc >= 400) { if (adc >= 400) {
adc -= 400; adc -= 400;
@ -174,7 +174,7 @@ static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state
} }
if (adc < state->adc_diff) { if (adc < state->adc_diff) {
dprintk( "CAPTRIM=%hd is closer to target (%hd/%hd)", state->captrim, adc, state->adc_diff); dprintk("CAPTRIM=%hd is closer to target (%hd/%hd)", state->captrim, adc, state->adc_diff);
state->adc_diff = adc; state->adc_diff = adc;
state->fcaptrim = state->captrim; state->fcaptrim = state->captrim;
@ -201,7 +201,7 @@ static int dib0070_set_ctrl_lo5(struct dvb_frontend *fe, u8 vco_bias_trim, u8 hf
{ {
struct dib0070_state *state = fe->tuner_priv; struct dib0070_state *state = fe->tuner_priv;
u16 lo5 = (third_order_filt << 14) | (0 << 13) | (1 << 12) | (3 << 9) | (cp_current << 6) | (hf_div_trim << 3) | (vco_bias_trim << 0); u16 lo5 = (third_order_filt << 14) | (0 << 13) | (1 << 12) | (3 << 9) | (cp_current << 6) | (hf_div_trim << 3) | (vco_bias_trim << 0);
dprintk( "CTRL_LO5: 0x%x", lo5); dprintk("CTRL_LO5: 0x%x", lo5);
return dib0070_write_reg(state, 0x15, lo5); return dib0070_write_reg(state, 0x15, lo5);
} }
@ -215,10 +215,10 @@ void dib0070_ctrl_agc_filter(struct dvb_frontend *fe, u8 open)
} else { } else {
dib0070_write_reg(state, 0x1b, 0x4112); dib0070_write_reg(state, 0x1b, 0x4112);
if (state->cfg->vga_filter != 0) { if (state->cfg->vga_filter != 0) {
dib0070_write_reg(state, 0x1a, state->cfg->vga_filter); dib0070_write_reg(state, 0x1a, state->cfg->vga_filter);
dprintk( "vga filter register is set to %x", state->cfg->vga_filter); dprintk("vga filter register is set to %x", state->cfg->vga_filter);
} else } else
dib0070_write_reg(state, 0x1a, 0x0009); dib0070_write_reg(state, 0x1a, 0x0009);
} }
} }
@ -255,7 +255,7 @@ static const struct dib0070_tuning dib0070_tuning_table[] = {
{ 189999, 1, 1, 3, 16, 2, 1, 0x8000 | 0x1000 }, { 189999, 1, 1, 3, 16, 2, 1, 0x8000 | 0x1000 },
{ 250000, 1, 0, 6, 12, 2, 1, 0x8000 | 0x1000 }, { 250000, 1, 0, 6, 12, 2, 1, 0x8000 | 0x1000 },
{ 569999, 2, 1, 5, 6, 2, 2, 0x4000 | 0x0800 }, /* UHF */ { 569999, 2, 1, 5, 6, 2, 2, 0x4000 | 0x0800 }, /* UHF */
{ 699999, 2, 0 ,1, 4, 2, 2, 0x4000 | 0x0800 }, { 699999, 2, 0, 1, 4, 2, 2, 0x4000 | 0x0800 },
{ 863999, 2, 1, 1, 4, 2, 2, 0x4000 | 0x0800 }, { 863999, 2, 1, 1, 4, 2, 2, 0x4000 | 0x0800 },
{ 0xffffffff, 0, 1, 0, 2, 2, 4, 0x2000 | 0x0400 }, /* LBAND or everything higher than UHF */ { 0xffffffff, 0, 1, 0, 2, 2, 4, 0x2000 | 0x0400 }, /* LBAND or everything higher than UHF */
}; };
@ -291,7 +291,7 @@ static const struct dib0070_lna_match dib0070_lna[] = {
{ 0xffffffff, 7 }, { 0xffffffff, 7 },
}; };
#define LPF 100 // define for the loop filter 100kHz by default 16-07-06 #define LPF 100
static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch) static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch)
{ {
struct dib0070_state *state = fe->tuner_priv; struct dib0070_state *state = fe->tuner_priv;
@ -313,7 +313,7 @@ static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_par
&& (state->fe->dtv_property_cache.isdbt_sb_segment_idx == (state->fe->dtv_property_cache.isdbt_sb_segment_count / 2))) && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == (state->fe->dtv_property_cache.isdbt_sb_segment_count / 2)))
|| (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0) || (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
&& (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))) && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1))))
freq += 850; freq += 850;
#endif #endif
if (state->current_rf != freq) { if (state->current_rf != freq) {
@ -340,95 +340,95 @@ static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_par
} }
if (*tune_state == CT_TUNER_START) { if (*tune_state == CT_TUNER_START) {
dprintk( "Tuning for Band: %hd (%d kHz)", band, freq); dprintk("Tuning for Band: %hd (%d kHz)", band, freq);
if (state->current_rf != freq) { if (state->current_rf != freq) {
u8 REFDIV; u8 REFDIV;
u32 FBDiv, Rest, FREF, VCOF_kHz; u32 FBDiv, Rest, FREF, VCOF_kHz;
u8 Den; u8 Den;
state->current_rf = freq; state->current_rf = freq;
state->lo4 = (state->current_tune_table_index->vco_band << 11) | (state->current_tune_table_index->hfdiv << 7); state->lo4 = (state->current_tune_table_index->vco_band << 11) | (state->current_tune_table_index->hfdiv << 7);
dib0070_write_reg(state, 0x17, 0x30); dib0070_write_reg(state, 0x17, 0x30);
VCOF_kHz = state->current_tune_table_index->vco_multi * freq * 2; VCOF_kHz = state->current_tune_table_index->vco_multi * freq * 2;
switch (band) { switch (band) {
case BAND_VHF: case BAND_VHF:
REFDIV = (u8) ((state->cfg->clock_khz + 9999) / 10000); REFDIV = (u8) ((state->cfg->clock_khz + 9999) / 10000);
break; break;
case BAND_FM: case BAND_FM:
REFDIV = (u8) ((state->cfg->clock_khz) / 1000); REFDIV = (u8) ((state->cfg->clock_khz) / 1000);
break; break;
default: default:
REFDIV = (u8) ( state->cfg->clock_khz / 10000); REFDIV = (u8) (state->cfg->clock_khz / 10000);
break; break;
} }
FREF = state->cfg->clock_khz / REFDIV; FREF = state->cfg->clock_khz / REFDIV;
switch (state->revision) { switch (state->revision) {
case DIB0070S_P1A: case DIB0070S_P1A:
FBDiv = (VCOF_kHz / state->current_tune_table_index->presc / FREF); FBDiv = (VCOF_kHz / state->current_tune_table_index->presc / FREF);
Rest = (VCOF_kHz / state->current_tune_table_index->presc) - FBDiv * FREF; Rest = (VCOF_kHz / state->current_tune_table_index->presc) - FBDiv * FREF;
break; break;
case DIB0070_P1G: case DIB0070_P1G:
case DIB0070_P1F: case DIB0070_P1F:
default: default:
FBDiv = (freq / (FREF / 2)); FBDiv = (freq / (FREF / 2));
Rest = 2 * freq - FBDiv * FREF; Rest = 2 * freq - FBDiv * FREF;
break; break;
} }
if (Rest < LPF) if (Rest < LPF)
Rest = 0; Rest = 0;
else if (Rest < 2 * LPF) else if (Rest < 2 * LPF)
Rest = 2 * LPF; Rest = 2 * LPF;
else if (Rest > (FREF - LPF)) { else if (Rest > (FREF - LPF)) {
Rest = 0; Rest = 0;
FBDiv += 1; FBDiv += 1;
} else if (Rest > (FREF - 2 * LPF)) } else if (Rest > (FREF - 2 * LPF))
Rest = FREF - 2 * LPF; Rest = FREF - 2 * LPF;
Rest = (Rest * 6528) / (FREF / 10); Rest = (Rest * 6528) / (FREF / 10);
Den = 1; Den = 1;
if (Rest > 0) { if (Rest > 0) {
state->lo4 |= (1 << 14) | (1 << 12); state->lo4 |= (1 << 14) | (1 << 12);
Den = 255; Den = 255;
} }
dib0070_write_reg(state, 0x11, (u16)FBDiv); dib0070_write_reg(state, 0x11, (u16)FBDiv);
dib0070_write_reg(state, 0x12, (Den << 8) | REFDIV); dib0070_write_reg(state, 0x12, (Den << 8) | REFDIV);
dib0070_write_reg(state, 0x13, (u16) Rest); dib0070_write_reg(state, 0x13, (u16) Rest);
if (state->revision == DIB0070S_P1A) { if (state->revision == DIB0070S_P1A) {
if (band == BAND_SBAND) { if (band == BAND_SBAND) {
dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0); dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
dib0070_write_reg(state, 0x1d,0xFFFF); dib0070_write_reg(state, 0x1d, 0xFFFF);
} else } else
dib0070_set_ctrl_lo5(fe, 5, 4, 3, 1); dib0070_set_ctrl_lo5(fe, 5, 4, 3, 1);
} }
dib0070_write_reg(state, 0x20, dib0070_write_reg(state, 0x20,
0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001 | state->current_tune_table_index->tuner_enable); 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001 | state->current_tune_table_index->tuner_enable);
dprintk( "REFDIV: %hd, FREF: %d", REFDIV, FREF); dprintk("REFDIV: %hd, FREF: %d", REFDIV, FREF);
dprintk( "FBDIV: %d, Rest: %d", FBDiv, Rest); dprintk("FBDIV: %d, Rest: %d", FBDiv, Rest);
dprintk( "Num: %hd, Den: %hd, SD: %hd",(u16) Rest, Den, (state->lo4 >> 12) & 0x1); dprintk("Num: %hd, Den: %hd, SD: %hd", (u16) Rest, Den, (state->lo4 >> 12) & 0x1);
dprintk( "HFDIV code: %hd", state->current_tune_table_index->hfdiv); dprintk("HFDIV code: %hd", state->current_tune_table_index->hfdiv);
dprintk( "VCO = %hd", state->current_tune_table_index->vco_band); dprintk("VCO = %hd", state->current_tune_table_index->vco_band);
dprintk( "VCOF: ((%hd*%d) << 1))", state->current_tune_table_index->vco_multi, freq); dprintk("VCOF: ((%hd*%d) << 1))", state->current_tune_table_index->vco_multi, freq);
*tune_state = CT_TUNER_STEP_0; *tune_state = CT_TUNER_STEP_0;
} else { /* we are already tuned to this frequency - the configuration is correct */ } else { /* we are already tuned to this frequency - the configuration is correct */
ret = 50; /* wakeup time */ ret = 50; /* wakeup time */
*tune_state = CT_TUNER_STEP_5; *tune_state = CT_TUNER_STEP_5;
} }
} else if ((*tune_state > CT_TUNER_START) && (*tune_state < CT_TUNER_STEP_4)) { } else if ((*tune_state > CT_TUNER_START) && (*tune_state < CT_TUNER_STEP_4)) {
@ -437,13 +437,13 @@ static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_par
} else if (*tune_state == CT_TUNER_STEP_4) { } else if (*tune_state == CT_TUNER_STEP_4) {
const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain; const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
if (tmp != NULL) { if (tmp != NULL) {
while (freq/1000 > tmp->freq) /* find the right one */ while (freq/1000 > tmp->freq) /* find the right one */
tmp++; tmp++;
dib0070_write_reg(state, 0x0f, dib0070_write_reg(state, 0x0f,
(0 << 15) | (1 << 14) | (3 << 12) | (tmp->wbd_gain_val << 9) | (0 << 8) | (1 << 7) | (state-> (0 << 15) | (1 << 14) | (3 << 12)
current_tune_table_index-> | (tmp->wbd_gain_val << 9) | (0 << 8) | (1 << 7)
wbdmux << 0)); | (state->current_tune_table_index->wbdmux << 0));
state->wbd_gain_current = tmp->wbd_gain_val; state->wbd_gain_current = tmp->wbd_gain_val;
} else { } else {
dib0070_write_reg(state, 0x0f, dib0070_write_reg(state, 0x0f,
(0 << 15) | (1 << 14) | (3 << 12) | (6 << 9) | (0 << 8) | (1 << 7) | (state->current_tune_table_index-> (0 << 15) | (1 << 14) | (3 << 12) | (6 << 9) | (0 << 8) | (1 << 7) | (state->current_tune_table_index->
@ -483,7 +483,7 @@ static int dib0070_tune(struct dvb_frontend *fe, struct dvb_frontend_parameters
do { do {
ret = dib0070_tune_digital(fe, p); ret = dib0070_tune_digital(fe, p);
if (ret != FE_CALLBACK_TIME_NEVER) if (ret != FE_CALLBACK_TIME_NEVER)
msleep(ret/10); msleep(ret/10);
else else
break; break;
} while (state->tune_state != CT_TUNER_STOP); } while (state->tune_state != CT_TUNER_STOP);
@ -512,18 +512,20 @@ u8 dib0070_get_rf_output(struct dvb_frontend *fe)
struct dib0070_state *state = fe->tuner_priv; struct dib0070_state *state = fe->tuner_priv;
return (dib0070_read_reg(state, 0x07) >> 11) & 0x3; return (dib0070_read_reg(state, 0x07) >> 11) & 0x3;
} }
EXPORT_SYMBOL(dib0070_get_rf_output); EXPORT_SYMBOL(dib0070_get_rf_output);
int dib0070_set_rf_output(struct dvb_frontend *fe, u8 no) int dib0070_set_rf_output(struct dvb_frontend *fe, u8 no)
{ {
struct dib0070_state *state = fe->tuner_priv; struct dib0070_state *state = fe->tuner_priv;
u16 rxrf2 = dib0070_read_reg(state, 0x07) & 0xfe7ff; u16 rxrf2 = dib0070_read_reg(state, 0x07) & 0xfe7ff;
if (no > 3) no = 3; if (no > 3)
if (no < 1) no = 1; no = 3;
if (no < 1)
no = 1;
return dib0070_write_reg(state, 0x07, rxrf2 | (no << 11)); return dib0070_write_reg(state, 0x07, rxrf2 | (no << 11));
} }
EXPORT_SYMBOL(dib0070_set_rf_output); EXPORT_SYMBOL(dib0070_set_rf_output);
static const u16 dib0070_p1f_defaults[] = static const u16 dib0070_p1f_defaults[] =
{ {
@ -582,7 +584,7 @@ static void dib0070_wbd_offset_calibration(struct dib0070_state *state)
u8 gain; u8 gain;
for (gain = 6; gain < 8; gain++) { for (gain = 6; gain < 8; gain++) {
state->wbd_offset_3_3[gain - 6] = ((dib0070_read_wbd_offset(state, gain) * 8 * 18 / 33 + 1) / 2); state->wbd_offset_3_3[gain - 6] = ((dib0070_read_wbd_offset(state, gain) * 8 * 18 / 33 + 1) / 2);
dprintk( "Gain: %d, WBDOffset (3.3V) = %hd", gain, state->wbd_offset_3_3[gain-6]); dprintk("Gain: %d, WBDOffset (3.3V) = %hd", gain, state->wbd_offset_3_3[gain-6]);
} }
} }
@ -622,10 +624,10 @@ static int dib0070_reset(struct dvb_frontend *fe)
state->revision = DIB0070S_P1A; state->revision = DIB0070S_P1A;
/* P1F or not */ /* P1F or not */
dprintk( "Revision: %x", state->revision); dprintk("Revision: %x", state->revision);
if (state->revision == DIB0070_P1D) { if (state->revision == DIB0070_P1D) {
dprintk( "Error: this driver is not to be used meant for P1D or earlier"); dprintk("Error: this driver is not to be used meant for P1D or earlier");
return -EINVAL; return -EINVAL;
} }
@ -702,7 +704,7 @@ static const struct dvb_tuner_ops dib0070_ops = {
// .get_bandwidth = dib0070_get_bandwidth // .get_bandwidth = dib0070_get_bandwidth
}; };
struct dvb_frontend * dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg) struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg)
{ {
struct dib0070_state *state = kzalloc(sizeof(struct dib0070_state), GFP_KERNEL); struct dib0070_state *state = kzalloc(sizeof(struct dib0070_state), GFP_KERNEL);
if (state == NULL) if (state == NULL)

29
drivers/media/dvb/frontends/dib0090.c
View file

@ -149,8 +149,8 @@ static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg)
{ {
u8 b[2]; u8 b[2];
struct i2c_msg msg[2] = { struct i2c_msg msg[2] = {
{.addr = state->config->i2c_address,.flags = 0,.buf = &reg,.len = 1}, {.addr = state->config->i2c_address, .flags = 0, .buf = &reg, .len = 1},
{.addr = state->config->i2c_address,.flags = I2C_M_RD,.buf = b,.len = 2}, {.addr = state->config->i2c_address, .flags = I2C_M_RD, .buf = b, .len = 2},
}; };
if (i2c_transfer(state->i2c, msg, 2) != 2) { if (i2c_transfer(state->i2c, msg, 2) != 2) {
printk(KERN_WARNING "DiB0090 I2C read failed\n"); printk(KERN_WARNING "DiB0090 I2C read failed\n");
@ -162,7 +162,7 @@ static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg)
static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val) static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val)
{ {
u8 b[3] = { reg & 0xff, val >> 8, val & 0xff }; u8 b[3] = { reg & 0xff, val >> 8, val & 0xff };
struct i2c_msg msg = {.addr = state->config->i2c_address,.flags = 0,.buf = b,.len = 3 }; struct i2c_msg msg = {.addr = state->config->i2c_address, .flags = 0, .buf = b, .len = 3 };
if (i2c_transfer(state->i2c, &msg, 1) != 1) { if (i2c_transfer(state->i2c, &msg, 1) != 1) {
printk(KERN_WARNING "DiB0090 I2C write failed\n"); printk(KERN_WARNING "DiB0090 I2C write failed\n");
return -EREMOTEIO; return -EREMOTEIO;
@ -287,12 +287,12 @@ extern void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast)
{ {
struct dib0090_state *state = fe->tuner_priv; struct dib0090_state *state = fe->tuner_priv;
if (fast) if (fast)
dib0090_write_reg(state, 0x04, 0); //1kHz dib0090_write_reg(state, 0x04, 0);
else else
dib0090_write_reg(state, 0x04, 1); //almost frozen dib0090_write_reg(state, 0x04, 1);
} }
EXPORT_SYMBOL(dib0090_dcc_freq); EXPORT_SYMBOL(dib0090_dcc_freq);
static const u16 rf_ramp_pwm_cband[] = { static const u16 rf_ramp_pwm_cband[] = {
0, /* max RF gain in 10th of dB */ 0, /* max RF gain in 10th of dB */
0, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */ 0, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */
@ -616,11 +616,11 @@ void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
else else
dib0090_write_reg(state, 0x32, (0 << 11)); dib0090_write_reg(state, 0x32, (0 << 11));
dib0090_write_reg(state, 0x39, (1 << 10)); // 0 gain by default dib0090_write_reg(state, 0x39, (1 << 10));
} }
} }
EXPORT_SYMBOL(dib0090_pwm_gain_reset); EXPORT_SYMBOL(dib0090_pwm_gain_reset);
int dib0090_gain_control(struct dvb_frontend *fe) int dib0090_gain_control(struct dvb_frontend *fe)
{ {
struct dib0090_state *state = fe->tuner_priv; struct dib0090_state *state = fe->tuner_priv;
@ -760,7 +760,7 @@ int dib0090_gain_control(struct dvb_frontend *fe)
#ifdef DEBUG_AGC #ifdef DEBUG_AGC
dprintk dprintk
("FE: %d, tune state %d, ADC = %3ddB (ADC err %3d) WBD %3ddB (WBD err %3d, WBD val SADC: %4d), RFGainLimit (TOP): %3d, signal: %3ddBm", ("FE: %d, tune state %d, ADC = %3ddB (ADC err %3d) WBD %3ddB (WBD err %3d, WBD val SADC: %4d), RFGainLimit (TOP): %3d, signal: %3ddBm",
(u32) fe->id, (u32) * tune_state, (u32) adc, (u32) adc_error, (u32) wbd, (u32) wbd_error, (u32) wbd_val, (u32) fe->id, (u32) *tune_state, (u32) adc, (u32) adc_error, (u32) wbd, (u32) wbd_error, (u32) wbd_val,
(u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA)); (u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA));
#endif #endif
} }
@ -770,8 +770,8 @@ int dib0090_gain_control(struct dvb_frontend *fe)
dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly); dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly);
return ret; return ret;
} }
EXPORT_SYMBOL(dib0090_gain_control); EXPORT_SYMBOL(dib0090_gain_control);
void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt) void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt)
{ {
struct dib0090_state *state = fe->tuner_priv; struct dib0090_state *state = fe->tuner_priv;
@ -784,15 +784,15 @@ void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 *
if (rflt) if (rflt)
*rflt = (state->rf_lt_def >> 10) & 0x7; *rflt = (state->rf_lt_def >> 10) & 0x7;
} }
EXPORT_SYMBOL(dib0090_get_current_gain); EXPORT_SYMBOL(dib0090_get_current_gain);
u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner) u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner)
{ {
struct dib0090_state *st = tuner->tuner_priv; struct dib0090_state *st = tuner->tuner_priv;
return st->wbd_offset; return st->wbd_offset;
} }
EXPORT_SYMBOL(dib0090_get_wbd_offset); EXPORT_SYMBOL(dib0090_get_wbd_offset);
static const u16 dib0090_defaults[] = { static const u16 dib0090_defaults[] = {
25, 0x01, 25, 0x01,
@ -891,7 +891,7 @@ static int dib0090_reset(struct dvb_frontend *fe)
return 0; return 0;
} }
#define steps(u) (((u)>15)?((u)-16):(u)) #define steps(u) (((u) > 15) ? ((u)-16) : (u))
#define INTERN_WAIT 10 #define INTERN_WAIT 10
static int dib0090_get_offset(struct dib0090_state *state, enum frontend_tune_state *tune_state) static int dib0090_get_offset(struct dib0090_state *state, enum frontend_tune_state *tune_state)
{ {
@ -1439,7 +1439,6 @@ enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe)
return state->tune_state; return state->tune_state;
} }
EXPORT_SYMBOL(dib0090_get_tune_state); EXPORT_SYMBOL(dib0090_get_tune_state);
int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state) int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
@ -1449,7 +1448,6 @@ int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tun
state->tune_state = tune_state; state->tune_state = tune_state;
return 0; return 0;
} }
EXPORT_SYMBOL(dib0090_set_tune_state); EXPORT_SYMBOL(dib0090_set_tune_state);
static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency) static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency)
@ -1516,7 +1514,6 @@ struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapte
fe->tuner_priv = NULL; fe->tuner_priv = NULL;
return NULL; return NULL;
} }
EXPORT_SYMBOL(dib0090_register); EXPORT_SYMBOL(dib0090_register);
MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>"); MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");

2
drivers/media/dvb/frontends/dib0090.h
View file

@ -24,7 +24,7 @@ struct dib0090_io_config {
u8 pll_loopdiv:6; u8 pll_loopdiv:6;
u8 adc_clock_ratio; /* valid is 8, 7 ,6 */ u8 adc_clock_ratio; /* valid is 8, 7 ,6 */
u16 pll_int_loop_filt; // internal loop filt value. If not fill in , default is 8165 u16 pll_int_loop_filt;
}; };
struct dib0090_config { struct dib0090_config {

14
drivers/media/dvb/frontends/dib8000.c
View file

@ -937,21 +937,21 @@ static int dib8000_agc_startup(struct dvb_frontend *fe)
static const int32_t lut_1000ln_mant[] = static const int32_t lut_1000ln_mant[] =
{ {
908,7003,7090,7170,7244,7313,7377,7438,7495,7549,7600 908, 7003, 7090, 7170, 7244, 7313, 7377, 7438, 7495, 7549, 7600
}; };
int32_t dib8000_get_adc_power(struct dvb_frontend *fe, uint8_t mode) int32_t dib8000_get_adc_power(struct dvb_frontend *fe, uint8_t mode)
{ {
struct dib8000_state *state = fe->demodulator_priv; struct dib8000_state *state = fe->demodulator_priv;
uint32_t ix =0, tmp_val =0, exp = 0, mant = 0; uint32_t ix = 0, tmp_val = 0, exp = 0, mant = 0;
int32_t val; int32_t val;
val = dib8000_read32(state, 384); val = dib8000_read32(state, 384);
/* mode = 1 : ln_agcpower calc using mant-exp conversion and mantis look up table */ /* mode = 1 : ln_agcpower calc using mant-exp conversion and mantis look up table */
if(mode) { if (mode) {
tmp_val = val; tmp_val = val;
while(tmp_val>>=1) while (tmp_val >>= 1)
exp++; exp++;
mant = (val * 1000 / (1<<exp)); mant = (val * 1000 / (1<<exp));
ix = (uint8_t)((mant-1000)/100); /* index of the LUT */ ix = (uint8_t)((mant-1000)/100); /* index of the LUT */
val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908); /* 1000 * ln(adcpower_real) ; 693 = 1000ln(2) ; 6908 = 1000*ln(1000) ; 20 comes from adc_real = adc_pow_int / 2**20 */ val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908); /* 1000 * ln(adcpower_real) ; 693 = 1000ln(2) ; 6908 = 1000*ln(1000) ; 20 comes from adc_real = adc_pow_int / 2**20 */
@ -1876,14 +1876,14 @@ static int dib8000_sleep(struct dvb_frontend *fe)
} }
} }
enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend* fe) enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe)
{ {
struct dib8000_state *state = fe->demodulator_priv; struct dib8000_state *state = fe->demodulator_priv;
return state->tune_state; return state->tune_state;
} }
EXPORT_SYMBOL(dib8000_get_tune_state); EXPORT_SYMBOL(dib8000_get_tune_state);
int dib8000_set_tune_state(struct dvb_frontend* fe, enum frontend_tune_state tune_state) int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
{ {
struct dib8000_state *state = fe->demodulator_priv; struct dib8000_state *state = fe->demodulator_priv;
state->tune_state = tune_state; state->tune_state = tune_state;

8
drivers/media/dvb/frontends/dib8000.h
View file

@ -46,8 +46,8 @@ extern int dib8000_set_gpio(struct dvb_frontend *, u8 num, u8 dir, u8 val);
extern int dib8000_set_wbd_ref(struct dvb_frontend *, u16 value); extern int dib8000_set_wbd_ref(struct dvb_frontend *, u16 value);
extern int dib8000_pid_filter_ctrl(struct dvb_frontend *, u8 onoff); extern int dib8000_pid_filter_ctrl(struct dvb_frontend *, u8 onoff);
extern int dib8000_pid_filter(struct dvb_frontend *, u8 id, u16 pid, u8 onoff); extern int dib8000_pid_filter(struct dvb_frontend *, u8 id, u16 pid, u8 onoff);
extern int dib8000_set_tune_state(struct dvb_frontend* fe, enum frontend_tune_state tune_state); extern int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state);
extern enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend* fe); extern enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe);
extern void dib8000_pwm_agc_reset(struct dvb_frontend *fe); extern void dib8000_pwm_agc_reset(struct dvb_frontend *fe);
extern s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode); extern s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode);
#else #else
@ -92,12 +92,12 @@ static inline int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return -ENODEV; return -ENODEV;
} }
static inline int dib8000_set_tune_state(struct dvb_frontend* fe, enum frontend_tune_state tune_state) static inline int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
{ {
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return -ENODEV; return -ENODEV;
} }
static inline enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend* fe) static inline enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe)
{ {
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return CT_SHUTDOWN, return CT_SHUTDOWN,

4
drivers/media/dvb/frontends/dibx000_common.h
View file

@ -45,7 +45,7 @@ extern u32 systime(void);
#define BAND_FM 0x10 #define BAND_FM 0x10
#define BAND_CBAND 0x20 #define BAND_CBAND 0x20
#define BAND_OF_FREQUENCY(freq_kHz) ( (freq_kHz) <= 170000 ? BAND_CBAND : \ #define BAND_OF_FREQUENCY(freq_kHz) ((freq_kHz) <= 170000 ? BAND_CBAND : \
(freq_kHz) <= 115000 ? BAND_FM : \ (freq_kHz) <= 115000 ? BAND_FM : \
(freq_kHz) <= 250000 ? BAND_VHF : \ (freq_kHz) <= 250000 ? BAND_VHF : \
(freq_kHz) <= 863000 ? BAND_UHF : \ (freq_kHz) <= 863000 ? BAND_UHF : \
@ -214,6 +214,6 @@ struct dvb_frontend_parametersContext {
#define FE_CALLBACK_TIME_NEVER 0xffffffff #define FE_CALLBACK_TIME_NEVER 0xffffffff
#define ABS(x) ((x<0)?(-x):(x)) #define ABS(x) ((x < 0) ? (-x) : (x))
#endif #endif