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ARM: dts: exynos: Add support ARM architected timers on Exynos5

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All CortexA7/A15 based Exynos5 SoCs have ARM architected timers, so enable
support for them directly in the base dtsi. None of the known firmware
properly configures CNTFRQ arch timer register, so force clock frequency
to 24MHz, which is the only configuration supported by the remaining
clock drivers so far.

Stock firmware for Peach Pit and Pi Chromebooks also doesn't reset
properly other arch timer registers, so add respective properties
indicating that. Other Exynos5-based boards behaves correctly in this area,
what finally allows to enable support for KVM-based virtualization.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Marek Szyprowski 2019-08-28 14:10:04 +02:00 committed by Krzysztof Kozlowski
parent 54ecb8f702
commit 9c8238b85c
3 changed files with 17 additions and 0 deletions
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4
arch/arm/boot/dts/exynos5420-peach-pit.dts
View file

@ -1065,6 +1065,10 @@
status = "okay";
};
&timer {
arm,cpu-registers-not-fw-configured;
};
&tmu_cpu0 {
vtmu-supply = <&ldo10_reg>;
};

9
arch/arm/boot/dts/exynos54xx.dtsi
View file

@ -45,6 +45,15 @@
status = "disabled";
};
timer: timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <24000000>;
};
soc: soc {
sysram@2020000 {
compatible = "mmio-sram";

4
arch/arm/boot/dts/exynos5800-peach-pi.dts
View file

@ -1034,6 +1034,10 @@
status = "okay";
};
&timer {
arm,cpu-registers-not-fw-configured;
};
&tmu_cpu0 {
vtmu-supply = <&ldo10_reg>;
};