gpio-tz1090: add TZ1090 gpio driver
Add a GPIO driver for the main GPIOs found in the TZ1090 (Comet) SoC. This doesn't include low-power GPIOs as they're controlled separately via the Powerdown Controller (PDC) registers. The driver is instantiated by device tree and supports interrupts for all GPIOs. Changes in v4: - fix typos in DT bindings compatible properties - reference Documentation/devicetree/bindings/gpio/gpio.txt in gpio-ranges description in DT bindings - fix gpio-ranges examples in DT bindings (it must now have 3 cells) - gpio-tz1090: use of_property_read_u32 instead of of_get_property Changes in v3: - separated from irq-imgpdc and removed arch/metag changes to allow these patches to go upstream separately via the pinctrl[/gpio] trees (particularly the pinctrl drivers depend on the new pinconf DT bindings). - some s/unsigned/unsigned int/. - some s/unsigned int/bool/ and use of BIT(). - gpio-tz1090*: refer to <dt-bindings/gpio/gpio.h> and <dt-bindings/interrupt-controller/irq.h> flags in bindings. - gpio-tz1090*: move initcall from postcore to subsys. - gpio-tz1090: add REG_ prefix to some constants for consistency. - gpio-tz1090: add comment to explain tz1090_gpio_irq_next_edge cunningness. Changes in v2: - gpio-tz1090: remove references to Linux flags in dt bindings - gpio-tz1090: make use of BIT() from linux/bitops.h - gpio-tz1090: make register accessors inline to match pinctrl - gpio-tz1090: update gpio-ranges to use 3 cells after recent ABI breakage Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Rob Landley <rob@landley.net> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-doc@vger.kernel.org Cc: devicetree-discuss@lists.ozlabs.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>hifive-unleashed-5.1
James Hogan
Linus Walleij
parent
ad81f0545e
commit
9caf1f2202
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@ -0,0 +1,88 @@
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ImgTec TZ1090 GPIO Controller
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Required properties:
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- compatible: Compatible property value should be "img,tz1090-gpio".
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- reg: Physical base address of the controller and length of memory mapped
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region.
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- #address-cells: Should be 1 (for bank subnodes)
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- #size-cells: Should be 0 (for bank subnodes)
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- Each bank of GPIOs should have a subnode to represent it.
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Bank subnode required properties:
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- reg: Index of bank in the range 0 to 2.
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- gpio-controller: Specifies that the node is a gpio controller.
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- #gpio-cells: Should be 2. The syntax of the gpio specifier used by client
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nodes should have the following values.
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<[phandle of the gpio controller node]
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[gpio number within the gpio bank]
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[gpio flags]>
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Values for gpio specifier:
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- GPIO number: a value in the range 0 to 29.
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- GPIO flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
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Only the following flags are supported:
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GPIO_ACTIVE_HIGH
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GPIO_ACTIVE_LOW
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Bank subnode optional properties:
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- gpio-ranges: Mapping to pin controller pins (as described in
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Documentation/devicetree/bindings/gpio/gpio.txt)
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- interrupts: Interrupt for the entire bank
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- interrupt-controller: Specifies that the node is an interrupt controller
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- #interrupt-cells: Should be 2. The syntax of the interrupt specifier used by
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client nodes should have the following values.
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<[phandle of the interurupt controller]
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[gpio number within the gpio bank]
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[irq flags]>
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Values for irq specifier:
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- GPIO number: a value in the range 0 to 29
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- IRQ flags: value to describe edge and level triggering, as defined in
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<dt-bindings/interrupt-controller/irq.h>. Only the following flags are
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supported:
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IRQ_TYPE_EDGE_RISING
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IRQ_TYPE_EDGE_FALLING
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IRQ_TYPE_EDGE_BOTH
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IRQ_TYPE_LEVEL_HIGH
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IRQ_TYPE_LEVEL_LOW
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Example:
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gpios: gpio-controller@02005800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "img,tz1090-gpio";
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reg = <0x02005800 0x90>;
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/* bank 0 with an interrupt */
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gpios0: bank@0 {
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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reg = <0>;
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interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 0 30>;
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interrupt-controller;
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};
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/* bank 2 without interrupt */
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gpios2: bank@2 {
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#gpio-cells = <2>;
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reg = <2>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 60 30>;
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};
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};
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@ -242,6 +242,13 @@ config GPIO_TS5500
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blocks of the TS-5500: DIO1, DIO2 and the LCD port, and the TS-5600
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LCD port.
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config GPIO_TZ1090
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bool "Toumaz Xenif TZ1090 GPIO support"
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depends on SOC_TZ1090
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default y
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help
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Say yes here to support Toumaz Xenif TZ1090 GPIOs.
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config GPIO_XILINX
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bool "Xilinx GPIO support"
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depends on PPC_OF || MICROBLAZE || ARCH_ZYNQ
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@ -79,6 +79,7 @@ obj-$(CONFIG_GPIO_TPS65912) += gpio-tps65912.o
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obj-$(CONFIG_GPIO_TS5500) += gpio-ts5500.o
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obj-$(CONFIG_GPIO_TWL4030) += gpio-twl4030.o
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obj-$(CONFIG_GPIO_TWL6040) += gpio-twl6040.o
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obj-$(CONFIG_GPIO_TZ1090) += gpio-tz1090.o
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obj-$(CONFIG_GPIO_UCB1400) += gpio-ucb1400.o
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obj-$(CONFIG_GPIO_VIPERBOARD) += gpio-viperboard.o
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obj-$(CONFIG_GPIO_VR41XX) += gpio-vr41xx.o
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@ -0,0 +1,633 @@
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/*
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* Toumaz Xenif TZ1090 GPIO handling.
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*
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* Copyright (C) 2008-2013 Imagination Technologies Ltd.
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*
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* Based on ARM PXA code and others.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/bitops.h>
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#include <linux/export.h>
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/of_irq.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/syscore_ops.h>
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#include <asm/global_lock.h>
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/* Register offsets from bank base address */
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#define REG_GPIO_DIR 0x00
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#define REG_GPIO_IRQ_PLRT 0x20
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#define REG_GPIO_IRQ_TYPE 0x30
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#define REG_GPIO_IRQ_EN 0x40
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#define REG_GPIO_IRQ_STS 0x50
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#define REG_GPIO_BIT_EN 0x60
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#define REG_GPIO_DIN 0x70
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#define REG_GPIO_DOUT 0x80
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/* REG_GPIO_IRQ_PLRT */
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#define REG_GPIO_IRQ_PLRT_LOW 0
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#define REG_GPIO_IRQ_PLRT_HIGH 1
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/* REG_GPIO_IRQ_TYPE */
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#define REG_GPIO_IRQ_TYPE_LEVEL 0
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#define REG_GPIO_IRQ_TYPE_EDGE 1
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/**
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* struct tz1090_gpio_bank - GPIO bank private data
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* @chip: Generic GPIO chip for GPIO bank
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* @domain: IRQ domain for GPIO bank (may be NULL)
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* @reg: Base of registers, offset for this GPIO bank
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* @irq: IRQ number for GPIO bank
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* @label: Debug GPIO bank label, used for storage of chip->label
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*
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* This is the main private data for a GPIO bank. It encapsulates a gpio_chip,
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* and the callbacks for the gpio_chip can access the private data with the
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* to_bank() macro below.
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*/
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struct tz1090_gpio_bank {
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struct gpio_chip chip;
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struct irq_domain *domain;
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void __iomem *reg;
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int irq;
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char label[16];
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};
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#define to_bank(c) container_of(c, struct tz1090_gpio_bank, chip)
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/**
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* struct tz1090_gpio - Overall GPIO device private data
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* @dev: Device (from platform device)
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* @reg: Base of GPIO registers
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*
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* Represents the overall GPIO device. This structure is actually only
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* temporary, and used during init.
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*/
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struct tz1090_gpio {
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struct device *dev;
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void __iomem *reg;
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};
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/**
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* struct tz1090_gpio_bank_info - Temporary registration info for GPIO bank
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* @priv: Overall GPIO device private data
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* @node: Device tree node specific to this GPIO bank
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* @index: Index of bank in range 0-2
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*/
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struct tz1090_gpio_bank_info {
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struct tz1090_gpio *priv;
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struct device_node *node;
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unsigned int index;
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};
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/* Convenience register accessors */
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static inline void tz1090_gpio_write(struct tz1090_gpio_bank *bank,
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unsigned int reg_offs, u32 data)
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{
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iowrite32(data, bank->reg + reg_offs);
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}
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static inline u32 tz1090_gpio_read(struct tz1090_gpio_bank *bank,
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unsigned int reg_offs)
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{
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return ioread32(bank->reg + reg_offs);
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}
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/* caller must hold LOCK2 */
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static inline void _tz1090_gpio_clear_bit(struct tz1090_gpio_bank *bank,
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unsigned int reg_offs,
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unsigned int offset)
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{
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u32 value;
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value = tz1090_gpio_read(bank, reg_offs);
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value &= ~BIT(offset);
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tz1090_gpio_write(bank, reg_offs, value);
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}
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static void tz1090_gpio_clear_bit(struct tz1090_gpio_bank *bank,
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unsigned int reg_offs,
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unsigned int offset)
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{
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int lstat;
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__global_lock2(lstat);
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_tz1090_gpio_clear_bit(bank, reg_offs, offset);
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__global_unlock2(lstat);
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}
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/* caller must hold LOCK2 */
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static inline void _tz1090_gpio_set_bit(struct tz1090_gpio_bank *bank,
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unsigned int reg_offs,
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unsigned int offset)
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{
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u32 value;
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value = tz1090_gpio_read(bank, reg_offs);
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value |= BIT(offset);
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tz1090_gpio_write(bank, reg_offs, value);
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}
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static void tz1090_gpio_set_bit(struct tz1090_gpio_bank *bank,
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unsigned int reg_offs,
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unsigned int offset)
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{
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int lstat;
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__global_lock2(lstat);
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_tz1090_gpio_set_bit(bank, reg_offs, offset);
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__global_unlock2(lstat);
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}
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/* caller must hold LOCK2 */
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static inline void _tz1090_gpio_mod_bit(struct tz1090_gpio_bank *bank,
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unsigned int reg_offs,
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unsigned int offset,
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bool val)
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{
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u32 value;
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value = tz1090_gpio_read(bank, reg_offs);
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value &= ~BIT(offset);
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if (val)
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value |= BIT(offset);
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tz1090_gpio_write(bank, reg_offs, value);
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}
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static void tz1090_gpio_mod_bit(struct tz1090_gpio_bank *bank,
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unsigned int reg_offs,
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unsigned int offset,
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bool val)
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{
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int lstat;
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__global_lock2(lstat);
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_tz1090_gpio_mod_bit(bank, reg_offs, offset, val);
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__global_unlock2(lstat);
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}
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static inline int tz1090_gpio_read_bit(struct tz1090_gpio_bank *bank,
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unsigned int reg_offs,
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unsigned int offset)
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{
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return tz1090_gpio_read(bank, reg_offs) & BIT(offset);
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}
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/* GPIO chip callbacks */
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static int tz1090_gpio_direction_input(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct tz1090_gpio_bank *bank = to_bank(chip);
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tz1090_gpio_set_bit(bank, REG_GPIO_DIR, offset);
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return 0;
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}
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static int tz1090_gpio_direction_output(struct gpio_chip *chip,
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unsigned int offset, int output_value)
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{
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struct tz1090_gpio_bank *bank = to_bank(chip);
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int lstat;
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__global_lock2(lstat);
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_tz1090_gpio_mod_bit(bank, REG_GPIO_DOUT, offset, output_value);
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_tz1090_gpio_clear_bit(bank, REG_GPIO_DIR, offset);
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__global_unlock2(lstat);
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return 0;
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}
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/*
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* Return GPIO level
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*/
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static int tz1090_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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struct tz1090_gpio_bank *bank = to_bank(chip);
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return tz1090_gpio_read_bit(bank, REG_GPIO_DIN, offset);
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}
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/*
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* Set output GPIO level
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*/
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static void tz1090_gpio_set(struct gpio_chip *chip, unsigned int offset,
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int output_value)
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{
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struct tz1090_gpio_bank *bank = to_bank(chip);
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tz1090_gpio_mod_bit(bank, REG_GPIO_DOUT, offset, output_value);
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}
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static int tz1090_gpio_request(struct gpio_chip *chip, unsigned int offset)
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{
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struct tz1090_gpio_bank *bank = to_bank(chip);
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int ret;
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ret = pinctrl_request_gpio(chip->base + offset);
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if (ret)
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return ret;
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tz1090_gpio_set_bit(bank, REG_GPIO_DIR, offset);
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tz1090_gpio_set_bit(bank, REG_GPIO_BIT_EN, offset);
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return 0;
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}
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static void tz1090_gpio_free(struct gpio_chip *chip, unsigned int offset)
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{
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struct tz1090_gpio_bank *bank = to_bank(chip);
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pinctrl_free_gpio(chip->base + offset);
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tz1090_gpio_clear_bit(bank, REG_GPIO_BIT_EN, offset);
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}
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static int tz1090_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
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{
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struct tz1090_gpio_bank *bank = to_bank(chip);
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if (!bank->domain)
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return -EINVAL;
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return irq_create_mapping(bank->domain, offset);
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}
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/* IRQ chip handlers */
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/* Get TZ1090 GPIO chip from irq data provided to generic IRQ callbacks */
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static inline struct tz1090_gpio_bank *irqd_to_gpio_bank(struct irq_data *data)
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{
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return (struct tz1090_gpio_bank *)data->domain->host_data;
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}
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static void tz1090_gpio_irq_clear(struct tz1090_gpio_bank *bank,
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unsigned int offset)
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{
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tz1090_gpio_clear_bit(bank, REG_GPIO_IRQ_STS, offset);
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}
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static void tz1090_gpio_irq_enable(struct tz1090_gpio_bank *bank,
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unsigned int offset, bool enable)
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{
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tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_EN, offset, enable);
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}
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static void tz1090_gpio_irq_polarity(struct tz1090_gpio_bank *bank,
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unsigned int offset, unsigned int polarity)
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{
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tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_PLRT, offset, polarity);
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}
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static int tz1090_gpio_valid_handler(struct irq_desc *desc)
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{
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return desc->handle_irq == handle_level_irq ||
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desc->handle_irq == handle_edge_irq;
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}
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static void tz1090_gpio_irq_type(struct tz1090_gpio_bank *bank,
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unsigned int offset, unsigned int type)
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{
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tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_TYPE, offset, type);
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}
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/* set polarity to trigger on next edge, whether rising or falling */
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static void tz1090_gpio_irq_next_edge(struct tz1090_gpio_bank *bank,
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unsigned int offset)
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{
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unsigned int value_p, value_i;
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int lstat;
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/*
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* Set the GPIO's interrupt polarity to the opposite of the current
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* input value so that the next edge triggers an interrupt.
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*/
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__global_lock2(lstat);
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value_i = ~tz1090_gpio_read(bank, REG_GPIO_DIN);
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value_p = tz1090_gpio_read(bank, REG_GPIO_IRQ_PLRT);
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value_p &= ~BIT(offset);
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value_p |= value_i & BIT(offset);
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tz1090_gpio_write(bank, REG_GPIO_IRQ_PLRT, value_p);
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__global_unlock2(lstat);
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}
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static void gpio_ack_irq(struct irq_data *data)
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{
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struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
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tz1090_gpio_irq_clear(bank, data->hwirq);
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}
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static void gpio_mask_irq(struct irq_data *data)
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{
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struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
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tz1090_gpio_irq_enable(bank, data->hwirq, false);
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}
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|
||||
static void gpio_unmask_irq(struct irq_data *data)
|
||||
{
|
||||
struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
|
||||
|
||||
tz1090_gpio_irq_enable(bank, data->hwirq, true);
|
||||
}
|
||||
|
||||
static unsigned int gpio_startup_irq(struct irq_data *data)
|
||||
{
|
||||
struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
|
||||
irq_hw_number_t hw = data->hwirq;
|
||||
struct irq_desc *desc = irq_to_desc(data->irq);
|
||||
|
||||
/*
|
||||
* This warning indicates that the type of the irq hasn't been set
|
||||
* before enabling the irq. This would normally be done by passing some
|
||||
* trigger flags to request_irq().
|
||||
*/
|
||||
WARN(!tz1090_gpio_valid_handler(desc),
|
||||
"irq type not set before enabling gpio irq %d", data->irq);
|
||||
|
||||
tz1090_gpio_irq_clear(bank, hw);
|
||||
tz1090_gpio_irq_enable(bank, hw, true);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gpio_set_irq_type(struct irq_data *data, unsigned int flow_type)
|
||||
{
|
||||
struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
|
||||
unsigned int type;
|
||||
unsigned int polarity;
|
||||
|
||||
switch (flow_type) {
|
||||
case IRQ_TYPE_EDGE_BOTH:
|
||||
type = REG_GPIO_IRQ_TYPE_EDGE;
|
||||
polarity = REG_GPIO_IRQ_PLRT_LOW;
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_RISING:
|
||||
type = REG_GPIO_IRQ_TYPE_EDGE;
|
||||
polarity = REG_GPIO_IRQ_PLRT_HIGH;
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_FALLING:
|
||||
type = REG_GPIO_IRQ_TYPE_EDGE;
|
||||
polarity = REG_GPIO_IRQ_PLRT_LOW;
|
||||
break;
|
||||
case IRQ_TYPE_LEVEL_HIGH:
|
||||
type = REG_GPIO_IRQ_TYPE_LEVEL;
|
||||
polarity = REG_GPIO_IRQ_PLRT_HIGH;
|
||||
break;
|
||||
case IRQ_TYPE_LEVEL_LOW:
|
||||
type = REG_GPIO_IRQ_TYPE_LEVEL;
|
||||
polarity = REG_GPIO_IRQ_PLRT_LOW;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
tz1090_gpio_irq_type(bank, data->hwirq, type);
|
||||
if (type == REG_GPIO_IRQ_TYPE_LEVEL)
|
||||
__irq_set_handler_locked(data->irq, handle_level_irq);
|
||||
else
|
||||
__irq_set_handler_locked(data->irq, handle_edge_irq);
|
||||
|
||||
if (flow_type == IRQ_TYPE_EDGE_BOTH)
|
||||
tz1090_gpio_irq_next_edge(bank, data->hwirq);
|
||||
else
|
||||
tz1090_gpio_irq_polarity(bank, data->hwirq, polarity);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SUSPEND
|
||||
static int gpio_set_irq_wake(struct irq_data *data, unsigned int on)
|
||||
{
|
||||
struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
|
||||
|
||||
#ifdef CONFIG_PM_DEBUG
|
||||
pr_info("irq_wake irq%d state:%d\n", data->irq, on);
|
||||
#endif
|
||||
|
||||
/* wake on gpio block interrupt */
|
||||
return irq_set_irq_wake(bank->irq, on);
|
||||
}
|
||||
#else
|
||||
#define gpio_set_irq_wake NULL
|
||||
#endif
|
||||
|
||||
/* gpio virtual interrupt functions */
|
||||
static struct irq_chip gpio_irq_chip = {
|
||||
.irq_startup = gpio_startup_irq,
|
||||
.irq_ack = gpio_ack_irq,
|
||||
.irq_mask = gpio_mask_irq,
|
||||
.irq_unmask = gpio_unmask_irq,
|
||||
.irq_set_type = gpio_set_irq_type,
|
||||
.irq_set_wake = gpio_set_irq_wake,
|
||||
.flags = IRQCHIP_MASK_ON_SUSPEND,
|
||||
};
|
||||
|
||||
static void tz1090_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
irq_hw_number_t hw;
|
||||
unsigned int irq_stat, irq_no;
|
||||
struct tz1090_gpio_bank *bank;
|
||||
struct irq_desc *child_desc;
|
||||
|
||||
bank = (struct tz1090_gpio_bank *)irq_desc_get_handler_data(desc);
|
||||
irq_stat = tz1090_gpio_read(bank, REG_GPIO_DIR) &
|
||||
tz1090_gpio_read(bank, REG_GPIO_IRQ_STS) &
|
||||
tz1090_gpio_read(bank, REG_GPIO_IRQ_EN) &
|
||||
0x3FFFFFFF; /* 30 bits only */
|
||||
|
||||
for (hw = 0; irq_stat; irq_stat >>= 1, ++hw) {
|
||||
if (!(irq_stat & 1))
|
||||
continue;
|
||||
|
||||
irq_no = irq_linear_revmap(bank->domain, hw);
|
||||
child_desc = irq_to_desc(irq_no);
|
||||
|
||||
/* Toggle edge for pin with both edges triggering enabled */
|
||||
if (irqd_get_trigger_type(&child_desc->irq_data)
|
||||
== IRQ_TYPE_EDGE_BOTH)
|
||||
tz1090_gpio_irq_next_edge(bank, hw);
|
||||
|
||||
BUG_ON(!tz1090_gpio_valid_handler(child_desc));
|
||||
generic_handle_irq_desc(irq_no, child_desc);
|
||||
}
|
||||
}
|
||||
|
||||
static int tz1090_gpio_irq_map(struct irq_domain *d, unsigned int irq,
|
||||
irq_hw_number_t hw)
|
||||
{
|
||||
irq_set_chip(irq, &gpio_irq_chip);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops tz1090_gpio_irq_domain_ops = {
|
||||
.map = tz1090_gpio_irq_map,
|
||||
.xlate = irq_domain_xlate_twocell,
|
||||
};
|
||||
|
||||
static int tz1090_gpio_bank_probe(struct tz1090_gpio_bank_info *info)
|
||||
{
|
||||
struct device_node *np = info->node;
|
||||
struct device *dev = info->priv->dev;
|
||||
struct tz1090_gpio_bank *bank;
|
||||
|
||||
bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
|
||||
if (!bank) {
|
||||
dev_err(dev, "unable to allocate driver data\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* Offset the main registers to the first register in this bank */
|
||||
bank->reg = info->priv->reg + info->index * 4;
|
||||
|
||||
/* Set up GPIO chip */
|
||||
snprintf(bank->label, sizeof(bank->label), "tz1090-gpio-%u",
|
||||
info->index);
|
||||
bank->chip.label = bank->label;
|
||||
bank->chip.dev = dev;
|
||||
bank->chip.direction_input = tz1090_gpio_direction_input;
|
||||
bank->chip.direction_output = tz1090_gpio_direction_output;
|
||||
bank->chip.get = tz1090_gpio_get;
|
||||
bank->chip.set = tz1090_gpio_set;
|
||||
bank->chip.free = tz1090_gpio_free;
|
||||
bank->chip.request = tz1090_gpio_request;
|
||||
bank->chip.to_irq = tz1090_gpio_to_irq;
|
||||
bank->chip.of_node = np;
|
||||
|
||||
/* GPIO numbering from 0 */
|
||||
bank->chip.base = info->index * 30;
|
||||
bank->chip.ngpio = 30;
|
||||
|
||||
/* Add the GPIO bank */
|
||||
gpiochip_add(&bank->chip);
|
||||
|
||||
/* Get the GPIO bank IRQ if provided */
|
||||
bank->irq = irq_of_parse_and_map(np, 0);
|
||||
|
||||
/* The interrupt is optional (it may be used by another core on chip) */
|
||||
if (bank->irq < 0) {
|
||||
dev_info(dev, "IRQ not provided for bank %u, IRQs disabled\n",
|
||||
info->index);
|
||||
return 0;
|
||||
}
|
||||
|
||||
dev_info(dev, "Setting up IRQs for GPIO bank %u\n",
|
||||
info->index);
|
||||
|
||||
/*
|
||||
* Initialise all interrupts to disabled so we don't get
|
||||
* spurious ones on a dirty boot and hit the BUG_ON in the
|
||||
* handler.
|
||||
*/
|
||||
tz1090_gpio_write(bank, REG_GPIO_IRQ_EN, 0);
|
||||
|
||||
/* Add a virtual IRQ for each GPIO */
|
||||
bank->domain = irq_domain_add_linear(np,
|
||||
bank->chip.ngpio,
|
||||
&tz1090_gpio_irq_domain_ops,
|
||||
bank);
|
||||
|
||||
/* Setup chained handler for this GPIO bank */
|
||||
irq_set_handler_data(bank->irq, bank);
|
||||
irq_set_chained_handler(bank->irq, tz1090_gpio_irq_handler);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tz1090_gpio_register_banks(struct tz1090_gpio *priv)
|
||||
{
|
||||
struct device_node *np = priv->dev->of_node;
|
||||
struct device_node *node;
|
||||
|
||||
for_each_available_child_of_node(np, node) {
|
||||
struct tz1090_gpio_bank_info info;
|
||||
u32 addr;
|
||||
int ret;
|
||||
|
||||
ret = of_property_read_u32(node, "reg", &addr);
|
||||
if (ret) {
|
||||
dev_err(priv->dev, "invalid reg on %s\n",
|
||||
node->full_name);
|
||||
continue;
|
||||
}
|
||||
if (addr >= 3) {
|
||||
dev_err(priv->dev, "index %u in %s out of range\n",
|
||||
addr, node->full_name);
|
||||
continue;
|
||||
}
|
||||
|
||||
info.index = addr;
|
||||
info.node = of_node_get(node);
|
||||
info.priv = priv;
|
||||
|
||||
ret = tz1090_gpio_bank_probe(&info);
|
||||
if (ret) {
|
||||
dev_err(priv->dev, "failure registering %s\n",
|
||||
node->full_name);
|
||||
of_node_put(node);
|
||||
continue;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int tz1090_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct resource *res_regs;
|
||||
struct tz1090_gpio priv;
|
||||
|
||||
if (!np) {
|
||||
dev_err(&pdev->dev, "must be instantiated via devicetree\n");
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res_regs) {
|
||||
dev_err(&pdev->dev, "cannot find registers resource\n");
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
priv.dev = &pdev->dev;
|
||||
|
||||
/* Ioremap the registers */
|
||||
priv.reg = devm_ioremap(&pdev->dev, res_regs->start,
|
||||
res_regs->end - res_regs->start);
|
||||
if (!priv.reg) {
|
||||
dev_err(&pdev->dev, "unable to ioremap registers\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* Look for banks */
|
||||
tz1090_gpio_register_banks(&priv);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct of_device_id tz1090_gpio_of_match[] = {
|
||||
{ .compatible = "img,tz1090-gpio" },
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct platform_driver tz1090_gpio_driver = {
|
||||
.driver = {
|
||||
.name = "tz1090-gpio",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = tz1090_gpio_of_match,
|
||||
},
|
||||
.probe = tz1090_gpio_probe,
|
||||
};
|
||||
|
||||
static int __init tz1090_gpio_init(void)
|
||||
{
|
||||
return platform_driver_register(&tz1090_gpio_driver);
|
||||
}
|
||||
subsys_initcall(tz1090_gpio_init);
|
||||
Loading…
Reference in New Issue