Samsung fixes for 3.16
- use WFI macro in platform_do_lowpower because exynos cpuhotplug includes a hardcoded WFI instruction and it causes compile error in Thumb-2 mode. - fix GIC reg sizes for exynos4 SoCs - remove reset timer counter value during boot and resume for mct to fix a big jump in printk timestamps - fix pm code to check cortex-A9 for another exynos SoCs - don't rely on firmware's secondary_cpu_start for mcpm -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJTpWI3AAoJEA0Cl+kVi2xqqj0P+wflKy3jmJu/T5qzasm2hSjE ywPjiecTeAHVurrY/pO0sFVAhNfi8KhxqJgzXcoJXJhTbboLQg3r0qwER5LizEOh Sl+HRTYcNQDPK4NKPCOpJFBn9pBQskNQYyg/wRqiuBhnPRyU09fJTgMjJi632l07 pqpCsdjHCFlP99QcNbTteHluzlEjr87XB4t1RNkdjPUsIqfBDhRLRFYwR/PT565O 6Vcl4aVkz14w02gw/+NW4rSCCI+8BWFP9iiCuptExNAAFDaSmDzQJcwBEBaX+DIY oadAc/ySsR0vdrQnX50L79+tuZvPzQq/3wwXTS3Xzv1LvHIscISpKpXIoKGTyyLI /GKP5itg9wq1upp+6k5Ubf1L+rIW3s/geqwoYsIgHgmXC0tiOFWaqn/u6vYT2rVF 0XylWLK/hC7tr0OjyAZFNiGeU3jLgoD5ZESfBhDCDko2EXETAMk7parXfLOKHHNP 1S3p9KKWjG0ePyXUbXQ00ubzkK+Tddp7e84RmSU/xu7zi2IqTX+3fJ1IbAeEI5e0 ibiI3gORT0ruSXaxW3gC0zDhAzpwy6dqbbkQK0EeYZ0dNu488W9XwlPbHTjBJFPm yGatGiKi0xGC3IH8dhd28i2IEQzQIETCQ+uf0txTKtSCNsQ0p2gFXAbI2qfpanqy Zn0UpR154+Ug0FYt+B0J =3Mlm -----END PGP SIGNATURE----- Merge tag 'samsung-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes Merge Samsung fixes for 3.16 from Kukjin Kim: - use WFI macro in platform_do_lowpower because exynos cpuhotplug includes a hardcoded WFI instruction and it causes compile error in Thumb-2 mode. - fix GIC reg sizes for exynos4 SoCs - remove reset timer counter value during boot and resume for mct to fix a big jump in printk timestamps - fix pm code to check cortex-A9 for another exynos SoCs - don't rely on firmware's secondary_cpu_start for mcpm * tag 'samsung-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: Don't rely on firmware's secondary_cpu_start for mcpm ARM: EXYNOS: fix pm code to check for cortex A9 rather than the SoC clocksource: exynos_mct: Don't reset the counter during boot and resume ARM: dts: fix reg sizes of GIC for exynos4 ARM: EXYNOS: Use wfi macro in platform_do_lowpower Signed-off-by: Arnd Bergmann <arnd@arndb.de>hifive-unleashed-5.1
Arnd Bergmann
commit
9cbf3d2b7e
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@ -113,7 +113,7 @@
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x10490000 0x1000>, <0x10480000 0x100>;
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reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
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};
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combiner: interrupt-controller@10440000 {
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@ -46,13 +46,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
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if (cpu == 1)
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exynos_cpu_power_down(cpu);
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/*
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* here's the WFI
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*/
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asm(".word 0xe320f003\n"
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:
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:
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: "memory", "cc");
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wfi();
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if (pen_release == cpu_logical_map(cpu)) {
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/*
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@ -25,7 +25,6 @@
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#define EXYNOS5420_CPUS_PER_CLUSTER 4
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#define EXYNOS5420_NR_CLUSTERS 2
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#define MCPM_BOOT_ADDR_OFFSET 0x1c
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/*
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* The common v7_exit_coherency_flush API could not be used because of the
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@ -343,11 +342,13 @@ static int __init exynos_mcpm_init(void)
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pr_info("Exynos MCPM support installed\n");
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/*
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* Future entries into the kernel can now go
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* through the cluster entry vectors.
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* U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
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* as part of secondary_cpu_start(). Let's redirect it to the
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* mcpm_entry_point().
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*/
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__raw_writel(virt_to_phys(mcpm_entry_point),
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ns_sram_base_addr + MCPM_BOOT_ADDR_OFFSET);
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__raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */
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__raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */
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__raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
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iounmap(ns_sram_base_addr);
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@ -300,7 +300,7 @@ static int exynos_pm_suspend(void)
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tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
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__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
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if (!soc_is_exynos5250())
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if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
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exynos_cpu_save_register();
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return 0;
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@ -334,7 +334,7 @@ static void exynos_pm_resume(void)
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if (exynos_pm_central_resume())
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goto early_wakeup;
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if (!soc_is_exynos5250())
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if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
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exynos_cpu_restore_register();
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/* For release retention */
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@ -353,7 +353,7 @@ static void exynos_pm_resume(void)
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s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
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if (!soc_is_exynos5250())
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if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
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scu_enable(S5P_VA_SCU);
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early_wakeup:
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@ -440,15 +440,18 @@ static int exynos_cpu_pm_notifier(struct notifier_block *self,
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case CPU_PM_ENTER:
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if (cpu == 0) {
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exynos_pm_central_suspend();
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exynos_cpu_save_register();
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if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
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exynos_cpu_save_register();
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}
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break;
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case CPU_PM_EXIT:
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if (cpu == 0) {
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if (!soc_is_exynos5250())
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if (read_cpuid_part_number() ==
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ARM_CPU_PART_CORTEX_A9) {
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scu_enable(S5P_VA_SCU);
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exynos_cpu_restore_register();
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exynos_cpu_restore_register();
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}
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exynos_pm_central_resume();
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}
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break;
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@ -153,13 +153,10 @@ static void exynos4_mct_write(unsigned int value, unsigned long offset)
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}
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/* Clocksource handling */
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static void exynos4_mct_frc_start(u32 hi, u32 lo)
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static void exynos4_mct_frc_start(void)
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{
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u32 reg;
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exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
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exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
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reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
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reg |= MCT_G_TCON_START;
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exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
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@ -181,7 +178,7 @@ static cycle_t exynos4_frc_read(struct clocksource *cs)
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static void exynos4_frc_resume(struct clocksource *cs)
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{
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exynos4_mct_frc_start(0, 0);
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exynos4_mct_frc_start();
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}
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struct clocksource mct_frc = {
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@ -200,7 +197,7 @@ static u64 notrace exynos4_read_sched_clock(void)
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static void __init exynos4_clocksource_init(void)
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{
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exynos4_mct_frc_start(0, 0);
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exynos4_mct_frc_start();
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if (clocksource_register_hz(&mct_frc, clk_rate))
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panic("%s: can't register clocksource\n", mct_frc.name);
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Reference in New Issue