drm/nouveau/secboot/gm200: add secure-boot support
Add secure-boot for the dGPU set of GM20X chips, using the PMU as the high-secure falcon. This work is based on Deepak Goyal's initial port of Secure Boot to Nouveau. v2. use proper memory target function Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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@ -53,4 +53,6 @@ bool nvkm_secboot_is_managed(struct nvkm_secboot *, enum nvkm_secboot_falcon);
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int nvkm_secboot_reset(struct nvkm_secboot *, u32 falcon);
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int nvkm_secboot_start(struct nvkm_secboot *, u32 falcon);
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int gm200_secboot_new(struct nvkm_device *, int, struct nvkm_secboot **);
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#endif
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@ -1981,6 +1981,7 @@ nv120_chipset = {
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.mxm = nv50_mxm_new,
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.pci = gk104_pci_new,
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.pmu = gm107_pmu_new,
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.secboot = gm200_secboot_new,
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.timer = gk20a_timer_new,
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.volt = gk104_volt_new,
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.ce[0] = gm200_ce_new,
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@ -2012,6 +2013,7 @@ nv124_chipset = {
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.mxm = nv50_mxm_new,
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.pci = gk104_pci_new,
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.pmu = gm107_pmu_new,
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.secboot = gm200_secboot_new,
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.timer = gk20a_timer_new,
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.volt = gk104_volt_new,
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.ce[0] = gm200_ce_new,
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@ -2043,6 +2045,7 @@ nv126_chipset = {
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.mxm = nv50_mxm_new,
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.pci = gk104_pci_new,
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.pmu = gm107_pmu_new,
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.secboot = gm200_secboot_new,
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.timer = gk20a_timer_new,
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.volt = gk104_volt_new,
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.ce[0] = gm200_ce_new,
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@ -231,12 +231,6 @@ gm200_gr_data[] = {
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* PGRAPH engine/subdev functions
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******************************************************************************/
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static int
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gm200_gr_init_ctxctl(struct gf100_gr *gr)
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{
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return 0;
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}
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int
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gm200_gr_init(struct gf100_gr *gr)
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{
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@ -350,7 +344,7 @@ gm200_gr_init(struct gf100_gr *gr)
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gf100_gr_zbc_init(gr);
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return gm200_gr_init_ctxctl(gr);
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return gf100_gr_init_ctxctl(gr);
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}
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int
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@ -1 +1,2 @@
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nvkm-y += nvkm/subdev/secboot/base.o
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nvkm-y += nvkm/subdev/secboot/gm200.o
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1489
drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c
Normal file
1489
drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c
Normal file
File diff suppressed because it is too large
Load diff
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@ -45,4 +45,182 @@ int nvkm_secboot_ctor(const struct nvkm_secboot_func *, struct nvkm_device *,
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int nvkm_secboot_falcon_reset(struct nvkm_secboot *);
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int nvkm_secboot_falcon_run(struct nvkm_secboot *);
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struct flcn_u64 {
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u32 lo;
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u32 hi;
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};
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static inline u64 flcn64_to_u64(const struct flcn_u64 f)
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{
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return ((u64)f.hi) << 32 | f.lo;
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}
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/**
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* struct gm200_flcn_bl_desc - DMEM bootloader descriptor
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* @signature: 16B signature for secure code. 0s if no secure code
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* @ctx_dma: DMA context to be used by BL while loading code/data
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* @code_dma_base: 256B-aligned Physical FB Address where code is located
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* (falcon's $xcbase register)
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* @non_sec_code_off: offset from code_dma_base where the non-secure code is
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* located. The offset must be multiple of 256 to help perf
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* @non_sec_code_size: the size of the nonSecure code part.
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* @sec_code_off: offset from code_dma_base where the secure code is
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* located. The offset must be multiple of 256 to help perf
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* @sec_code_size: offset from code_dma_base where the secure code is
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* located. The offset must be multiple of 256 to help perf
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* @code_entry_point: code entry point which will be invoked by BL after
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* code is loaded.
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* @data_dma_base: 256B aligned Physical FB Address where data is located.
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* (falcon's $xdbase register)
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* @data_size: size of data block. Should be multiple of 256B
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*
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* Structure used by the bootloader to load the rest of the code. This has
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* to be filled by host and copied into DMEM at offset provided in the
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* hsflcn_bl_desc.bl_desc_dmem_load_off.
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*/
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struct gm200_flcn_bl_desc {
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u32 reserved[4];
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u32 signature[4];
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u32 ctx_dma;
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struct flcn_u64 code_dma_base;
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u32 non_sec_code_off;
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u32 non_sec_code_size;
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u32 sec_code_off;
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u32 sec_code_size;
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u32 code_entry_point;
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struct flcn_u64 data_dma_base;
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u32 data_size;
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};
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/**
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* struct hsflcn_acr_desc - data section of the HS firmware
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*
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* This header is to be copied at the beginning of DMEM by the HS bootloader.
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*
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* @signature: signature of ACR ucode
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* @wpr_region_id: region ID holding the WPR header and its details
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* @wpr_offset: offset from the WPR region holding the wpr header
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* @regions: region descriptors
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* @nonwpr_ucode_blob_size: size of LS blob
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* @nonwpr_ucode_blob_start: FB location of LS blob is
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*/
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struct hsflcn_acr_desc {
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union {
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u8 reserved_dmem[0x200];
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u32 signatures[4];
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} ucode_reserved_space;
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u32 wpr_region_id;
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u32 wpr_offset;
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u32 mmu_mem_range;
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#define FLCN_ACR_MAX_REGIONS 2
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struct {
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u32 no_regions;
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struct {
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u32 start_addr;
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u32 end_addr;
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u32 region_id;
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u32 read_mask;
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u32 write_mask;
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u32 client_mask;
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} region_props[FLCN_ACR_MAX_REGIONS];
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} regions;
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u32 ucode_blob_size;
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u64 ucode_blob_base __aligned(8);
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struct {
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u32 vpr_enabled;
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u32 vpr_start;
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u32 vpr_end;
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u32 hdcp_policies;
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} vpr_desc;
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};
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/**
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* Contains the whole secure boot state, allowing it to be performed as needed
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* @wpr_addr: physical address of the WPR region
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* @wpr_size: size in bytes of the WPR region
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* @ls_blob: LS blob of all the LS firmwares, signatures, bootloaders
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* @ls_blob_size: size of the LS blob
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* @ls_blob_nb_regions: number of LS firmwares that will be loaded
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* @acr_blob: HS blob
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* @acr_blob_vma: mapping of the HS blob into the secure falcon's VM
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* @acr_bl_desc: bootloader descriptor of the HS blob
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* @hsbl_blob: HS blob bootloader
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* @inst: instance block for HS falcon
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* @pgd: page directory for the HS falcon
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* @vm: address space used by the HS falcon
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* @bl_desc_size: size of the BL descriptor used by this chip.
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* @fixup_bl_desc: hook that generates the proper BL descriptor format from
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* the generic GM200 format into a data array of size
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* bl_desc_size
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*/
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struct gm200_secboot {
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struct nvkm_secboot base;
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const struct gm200_secboot_func *func;
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/*
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* Address and size of the WPR region. On dGPU this will be the
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* address of the LS blob. On Tegra this is a fixed region set by the
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* bootloader
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*/
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u64 wpr_addr;
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u32 wpr_size;
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/*
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* HS FW - lock WPR region (dGPU only) and load LS FWs
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* on Tegra the HS FW copies the LS blob into the fixed WPR instead
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*/
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struct nvkm_gpuobj *acr_load_blob;
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struct gm200_flcn_bl_desc acr_load_bl_desc;
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/* HS FW - unlock WPR region (dGPU only) */
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struct nvkm_gpuobj *acr_unload_blob;
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struct gm200_flcn_bl_desc acr_unload_bl_desc;
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/* HS bootloader */
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void *hsbl_blob;
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/* LS FWs, to be loaded by the HS ACR */
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struct nvkm_gpuobj *ls_blob;
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/* Instance block & address space used for HS FW execution */
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struct nvkm_gpuobj *inst;
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struct nvkm_gpuobj *pgd;
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struct nvkm_vm *vm;
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/* To keep track of the state of all managed falcons */
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enum {
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/* In non-secure state, no firmware loaded, no privileges*/
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NON_SECURE = 0,
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/* In low-secure mode and ready to be started */
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RESET,
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/* In low-secure mode and running */
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RUNNING,
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} falcon_state[NVKM_SECBOOT_FALCON_END];
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};
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#define gm200_secboot(sb) container_of(sb, struct gm200_secboot, base)
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struct gm200_secboot_func {
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/*
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* Size of the bootloader descriptor for this chip. A block of this
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* size is allocated before booting a falcon and the fixup_bl_desc
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* callback is called on it
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*/
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u32 bl_desc_size;
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void (*fixup_bl_desc)(const struct gm200_flcn_bl_desc *, void *);
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/*
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* Chip-specific modifications of the HS descriptor can be done here.
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* On dGPU this is used to fill the information about the WPR region
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* we want the HS FW to set up.
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*/
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void (*fixup_hs_desc)(struct gm200_secboot *, struct hsflcn_acr_desc *);
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};
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int gm200_secboot_init(struct nvkm_secboot *);
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void *gm200_secboot_dtor(struct nvkm_secboot *);
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int gm200_secboot_reset(struct nvkm_secboot *, u32);
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int gm200_secboot_start(struct nvkm_secboot *, u32);
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int gm20x_secboot_prepare_blobs(struct gm200_secboot *);
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#endif
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