spi: docs: convert to ReST and add it to the kABI bookset
While there's one file there with briefily describes the uAPI, the documentation was written just like most subsystems: focused on kernel developers. So, add it together with driver-api books. Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # for iio Signed-off-by: Jonathan Corbet <corbet@lwn.net>alistair/sunxi64-5.4-dsi
Mauro Carvalho Chehab
Jonathan Corbet
parent
d2fd3732e4
commit
9cdd273e29
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@ -116,6 +116,7 @@ needed).
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power/index
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target/index
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timers/index
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spi/index
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watchdog/index
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virtual/index
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input/index
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@ -1,3 +1,4 @@
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===================================================
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spi_butterfly - parport-to-butterfly adapter driver
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===================================================
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@ -27,25 +28,29 @@ need to reflash the firmware, and the pins are the standard Atmel "ISP"
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connector pins (used also on non-Butterfly AVR boards). On the parport
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side this is like "sp12" programming cables.
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====== ============= ===================
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Signal Butterfly Parport (DB-25)
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------ --------- ---------------
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SCK = J403.PB1/SCK = pin 2/D0
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RESET = J403.nRST = pin 3/D1
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VCC = J403.VCC_EXT = pin 8/D6
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MOSI = J403.PB2/MOSI = pin 9/D7
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MISO = J403.PB3/MISO = pin 11/S7,nBUSY
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GND = J403.GND = pin 23/GND
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====== ============= ===================
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SCK J403.PB1/SCK pin 2/D0
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RESET J403.nRST pin 3/D1
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VCC J403.VCC_EXT pin 8/D6
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MOSI J403.PB2/MOSI pin 9/D7
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MISO J403.PB3/MISO pin 11/S7,nBUSY
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GND J403.GND pin 23/GND
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====== ============= ===================
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Then to let Linux master that bus to talk to the DataFlash chip, you must
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(a) flash new firmware that disables SPI (set PRR.2, and disable pullups
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by clearing PORTB.[0-3]); (b) configure the mtd_dataflash driver; and
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(c) cable in the chipselect.
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====== ============ ===================
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Signal Butterfly Parport (DB-25)
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------ --------- ---------------
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VCC = J400.VCC_EXT = pin 7/D5
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SELECT = J400.PB0/nSS = pin 17/C3,nSELECT
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GND = J400.GND = pin 24/GND
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====== ============ ===================
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VCC J400.VCC_EXT pin 7/D5
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SELECT J400.PB0/nSS pin 17/C3,nSELECT
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GND J400.GND pin 24/GND
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====== ============ ===================
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Or you could flash firmware making the AVR into an SPI slave (keeping the
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DataFlash in reset) and tweak the spi_butterfly driver to make it bind to
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@ -56,13 +61,14 @@ That would let you talk to the AVR using custom SPI-with-USI firmware,
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while letting either Linux or the AVR use the DataFlash. There are plenty
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of spare parport pins to wire this one up, such as:
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====== ============= ===================
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Signal Butterfly Parport (DB-25)
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------ --------- ---------------
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SCK = J403.PE4/USCK = pin 5/D3
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MOSI = J403.PE5/DI = pin 6/D4
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MISO = J403.PE6/DO = pin 12/S5,nPAPEROUT
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GND = J403.GND = pin 22/GND
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IRQ = J402.PF4 = pin 10/S6,ACK
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GND = J402.GND(P2) = pin 25/GND
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====== ============= ===================
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SCK J403.PE4/USCK pin 5/D3
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MOSI J403.PE5/DI pin 6/D4
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MISO J403.PE6/DO pin 12/S5,nPAPEROUT
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GND J403.GND pin 22/GND
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IRQ J402.PF4 pin 10/S6,ACK
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GND J402.GND(P2) pin 25/GND
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====== ============= ===================
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@ -0,0 +1,22 @@
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.. SPDX-License-Identifier: GPL-2.0
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=================================
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Serial Peripheral Interface (SPI)
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=================================
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.. toctree::
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:maxdepth: 1
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spi-summary
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spidev
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butterfly
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pxa2xx
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spi-lm70llp
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spi-sc18is602
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.. only:: subproject and html
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Indices
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=======
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* :ref:`genindex`
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@ -1,8 +1,10 @@
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==============================
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PXA2xx SPI on SSP driver HOWTO
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===================================================
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==============================
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This a mini howto on the pxa2xx_spi driver. The driver turns a PXA2xx
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synchronous serial port into a SPI master controller
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(see Documentation/spi/spi-summary). The driver has the following features
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(see Documentation/spi/spi-summary.rst). The driver has the following features
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- Support for any PXA2xx SSP
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- SSP PIO and SSP DMA data transfers.
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@ -19,12 +21,12 @@ Declaring PXA2xx Master Controllers
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-----------------------------------
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Typically a SPI master is defined in the arch/.../mach-*/board-*.c as a
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"platform device". The master configuration is passed to the driver via a table
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found in include/linux/spi/pxa2xx_spi.h:
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found in include/linux/spi/pxa2xx_spi.h::
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struct pxa2xx_spi_controller {
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struct pxa2xx_spi_controller {
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u16 num_chipselect;
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u8 enable_dma;
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};
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};
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The "pxa2xx_spi_controller.num_chipselect" field is used to determine the number of
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slave device (chips) attached to this SPI master.
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@ -36,9 +38,9 @@ See the "PXA2xx Developer Manual" section "DMA Controller".
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NSSP MASTER SAMPLE
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------------------
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Below is a sample configuration using the PXA255 NSSP.
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Below is a sample configuration using the PXA255 NSSP::
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static struct resource pxa_spi_nssp_resources[] = {
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static struct resource pxa_spi_nssp_resources[] = {
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[0] = {
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.start = __PREG(SSCR0_P(2)), /* Start address of NSSP */
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.end = __PREG(SSCR0_P(2)) + 0x2c, /* Range of registers */
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@ -49,14 +51,14 @@ static struct resource pxa_spi_nssp_resources[] = {
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.end = IRQ_NSSP,
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.flags = IORESOURCE_IRQ,
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},
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};
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};
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static struct pxa2xx_spi_controller pxa_nssp_master_info = {
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static struct pxa2xx_spi_controller pxa_nssp_master_info = {
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.num_chipselect = 1, /* Matches the number of chips attached to NSSP */
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.enable_dma = 1, /* Enables NSSP DMA */
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};
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};
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static struct platform_device pxa_spi_nssp = {
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static struct platform_device pxa_spi_nssp = {
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.name = "pxa2xx-spi", /* MUST BE THIS VALUE, so device match driver */
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.id = 2, /* Bus number, MUST MATCH SSP number 1..n */
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.resource = pxa_spi_nssp_resources,
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@ -64,22 +66,22 @@ static struct platform_device pxa_spi_nssp = {
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.dev = {
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.platform_data = &pxa_nssp_master_info, /* Passed to driver */
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},
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};
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};
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static struct platform_device *devices[] __initdata = {
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static struct platform_device *devices[] __initdata = {
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&pxa_spi_nssp,
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};
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};
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static void __init board_init(void)
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{
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static void __init board_init(void)
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{
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(void)platform_add_device(devices, ARRAY_SIZE(devices));
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}
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}
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Declaring Slave Devices
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-----------------------
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Typically each SPI slave (chip) is defined in the arch/.../mach-*/board-*.c
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using the "spi_board_info" structure found in "linux/spi/spi.h". See
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"Documentation/spi/spi-summary" for additional information.
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"Documentation/spi/spi-summary.rst" for additional information.
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Each slave device attached to the PXA must provide slave specific configuration
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information via the structure "pxa2xx_spi_chip" found in
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@ -87,19 +89,21 @@ information via the structure "pxa2xx_spi_chip" found in
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will uses the configuration whenever the driver communicates with the slave
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device. All fields are optional.
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struct pxa2xx_spi_chip {
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::
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struct pxa2xx_spi_chip {
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u8 tx_threshold;
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u8 rx_threshold;
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u8 dma_burst_size;
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u32 timeout;
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u8 enable_loopback;
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void (*cs_control)(u32 command);
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};
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};
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The "pxa2xx_spi_chip.tx_threshold" and "pxa2xx_spi_chip.rx_threshold" fields are
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used to configure the SSP hardware fifo. These fields are critical to the
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performance of pxa2xx_spi driver and misconfiguration will result in rx
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fifo overruns (especially in PIO mode transfers). Good default values are
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fifo overruns (especially in PIO mode transfers). Good default values are::
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.tx_threshold = 8,
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.rx_threshold = 8,
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@ -141,41 +145,43 @@ The pxa2xx_spi_chip structure is passed to the pxa2xx_spi driver in the
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"spi_board_info.controller_data" field. Below is a sample configuration using
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the PXA255 NSSP.
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/* Chip Select control for the CS8415A SPI slave device */
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static void cs8415a_cs_control(u32 command)
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{
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::
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/* Chip Select control for the CS8415A SPI slave device */
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static void cs8415a_cs_control(u32 command)
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{
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if (command & PXA2XX_CS_ASSERT)
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GPCR(2) = GPIO_bit(2);
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else
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GPSR(2) = GPIO_bit(2);
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}
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}
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/* Chip Select control for the CS8405A SPI slave device */
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static void cs8405a_cs_control(u32 command)
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{
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/* Chip Select control for the CS8405A SPI slave device */
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static void cs8405a_cs_control(u32 command)
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{
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if (command & PXA2XX_CS_ASSERT)
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GPCR(3) = GPIO_bit(3);
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else
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GPSR(3) = GPIO_bit(3);
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}
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}
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static struct pxa2xx_spi_chip cs8415a_chip_info = {
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static struct pxa2xx_spi_chip cs8415a_chip_info = {
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.tx_threshold = 8, /* SSP hardward FIFO threshold */
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.rx_threshold = 8, /* SSP hardward FIFO threshold */
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.dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
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.timeout = 235, /* See Intel documentation */
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.cs_control = cs8415a_cs_control, /* Use external chip select */
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};
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};
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static struct pxa2xx_spi_chip cs8405a_chip_info = {
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static struct pxa2xx_spi_chip cs8405a_chip_info = {
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.tx_threshold = 8, /* SSP hardward FIFO threshold */
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.rx_threshold = 8, /* SSP hardward FIFO threshold */
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.dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
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.timeout = 235, /* See Intel documentation */
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.cs_control = cs8405a_cs_control, /* Use external chip select */
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};
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};
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static struct spi_board_info streetracer_spi_board_info[] __initdata = {
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static struct spi_board_info streetracer_spi_board_info[] __initdata = {
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{
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.modalias = "cs8415a", /* Name of spi_driver for this device */
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.max_speed_hz = 3686400, /* Run SSP as fast a possbile */
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@ -193,13 +199,13 @@ static struct spi_board_info streetracer_spi_board_info[] __initdata = {
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.controller_data = &cs8405a_chip_info, /* Master chip config */
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.irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */
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},
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};
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};
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static void __init streetracer_init(void)
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{
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static void __init streetracer_init(void)
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{
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spi_register_board_info(streetracer_spi_board_info,
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ARRAY_SIZE(streetracer_spi_board_info));
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}
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}
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DMA and PIO I/O Support
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@ -210,26 +216,25 @@ by setting the "enable_dma" flag in the "pxa2xx_spi_controller" structure. The
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mode supports both coherent and stream based DMA mappings.
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The following logic is used to determine the type of I/O to be used on
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a per "spi_transfer" basis:
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a per "spi_transfer" basis::
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if !enable_dma then
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if !enable_dma then
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always use PIO transfers
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if spi_message.len > 8191 then
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if spi_message.len > 8191 then
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print "rate limited" warning
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use PIO transfers
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if spi_message.is_dma_mapped and rx_dma_buf != 0 and tx_dma_buf != 0 then
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if spi_message.is_dma_mapped and rx_dma_buf != 0 and tx_dma_buf != 0 then
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use coherent DMA mode
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if rx_buf and tx_buf are aligned on 8 byte boundary then
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if rx_buf and tx_buf are aligned on 8 byte boundary then
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use streaming DMA mode
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otherwise
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otherwise
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use PIO transfer
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THANKS TO
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---------
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David Brownell and others for mentoring the development of this driver.
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@ -1,8 +1,11 @@
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==============================================
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spi_lm70llp : LM70-LLP parport-to-SPI adapter
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==============================================
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Supported board/chip:
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* National Semiconductor LM70 LLP evaluation board
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Datasheet: http://www.national.com/pf/LM/LM70.html
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Author:
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@ -29,9 +32,10 @@ available (on page 4) here:
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The hardware interfacing on the LM70 LLP eval board is as follows:
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======== == ========= ==========
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Parallel LM70 LLP
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Port Direction JP2 Header
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----------- --------- ----------------
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Port . Direction JP2 Header
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======== == ========= ==========
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D0 2 - -
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D1 3 --> V+ 5
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D2 4 --> V+ 5
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@ -42,7 +46,7 @@ The hardware interfacing on the LM70 LLP eval board is as follows:
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D7 9 --> SI/O 5
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GND 25 - GND 7
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Select 13 <-- SI/O 1
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----------- --------- ----------------
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======== == ========= ==========
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Note that since the LM70 uses a "3-wire" variant of SPI, the SI/SO pin
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is connected to both pin D7 (as Master Out) and Select (as Master In)
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@ -74,6 +78,7 @@ inverting the value read at pin 13.
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Thanks to
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---------
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o David Brownell for mentoring the SPI-side driver development.
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o Dr.Craig Hollabaugh for the (early) "manual" bitbanging driver version.
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o Nadir Billimoria for help interpreting the circuit schematic.
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- David Brownell for mentoring the SPI-side driver development.
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- Dr.Craig Hollabaugh for the (early) "manual" bitbanging driver version.
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- Nadir Billimoria for help interpreting the circuit schematic.
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@ -1,8 +1,11 @@
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===========================
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Kernel driver spi-sc18is602
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===========================
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Supported chips:
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* NXP SI18IS602/602B/603
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Datasheet: http://www.nxp.com/documents/data_sheet/SC18IS602_602B_603.pdf
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Author:
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@ -1,3 +1,4 @@
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====================================
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Overview of Linux kernel SPI support
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====================================
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@ -139,12 +140,14 @@ a command and then reading its response.
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There are two types of SPI driver, here called:
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Controller drivers ... controllers may be built into System-On-Chip
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Controller drivers ...
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controllers may be built into System-On-Chip
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processors, and often support both Master and Slave roles.
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These drivers touch hardware registers and may use DMA.
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Or they can be PIO bitbangers, needing just GPIO pins.
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Protocol drivers ... these pass messages through the controller
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Protocol drivers ...
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these pass messages through the controller
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driver to communicate with a Slave or Master device on the
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other side of an SPI link.
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@ -160,7 +163,7 @@ those two types of drivers.
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There is a minimal core of SPI programming interfaces, focussing on
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using the driver model to connect controller and protocol drivers using
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device tables provided by board specific initialization code. SPI
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shows up in sysfs in several locations:
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shows up in sysfs in several locations::
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/sys/devices/.../CTLR ... physical node for a given SPI controller
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@ -168,7 +171,7 @@ shows up in sysfs in several locations:
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chipselect C, accessed through CTLR.
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/sys/bus/spi/devices/spiB.C ... symlink to that physical
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.../CTLR/spiB.C device
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.../CTLR/spiB.C device
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/sys/devices/.../CTLR/spiB.C/modalias ... identifies the driver
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that should be used with this device (for hotplug/coldplug)
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@ -206,7 +209,8 @@ Linux needs several kinds of information to properly configure SPI devices.
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That information is normally provided by board-specific code, even for
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chips that do support some of automated discovery/enumeration.
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DECLARE CONTROLLERS
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Declare Controllers
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^^^^^^^^^^^^^^^^^^^
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The first kind of information is a list of what SPI controllers exist.
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For System-on-Chip (SOC) based boards, these will usually be platform
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@ -221,7 +225,7 @@ same basic controller setup code. This is because most SOCs have several
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SPI-capable controllers, and only the ones actually usable on a given
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board should normally be set up and registered.
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So for example arch/.../mach-*/board-*.c files might have code like:
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So for example arch/.../mach-*/board-*.c files might have code like::
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#include <mach/spi.h> /* for mysoc_spi_data */
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|
|
@ -238,7 +242,7 @@ So for example arch/.../mach-*/board-*.c files might have code like:
|
|||
...
|
||||
}
|
||||
|
||||
And SOC-specific utility code might look something like:
|
||||
And SOC-specific utility code might look something like::
|
||||
|
||||
#include <mach/spi.h>
|
||||
|
||||
|
|
@ -269,8 +273,8 @@ same SOC controller is used. For example, on one board SPI might use
|
|||
an external clock, where another derives the SPI clock from current
|
||||
settings of some master clock.
|
||||
|
||||
|
||||
DECLARE SLAVE DEVICES
|
||||
Declare Slave Devices
|
||||
^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The second kind of information is a list of what SPI slave devices exist
|
||||
on the target board, often with some board-specific data needed for the
|
||||
|
|
@ -278,7 +282,7 @@ driver to work correctly.
|
|||
|
||||
Normally your arch/.../mach-*/board-*.c files would provide a small table
|
||||
listing the SPI devices on each board. (This would typically be only a
|
||||
small handful.) That might look like:
|
||||
small handful.) That might look like::
|
||||
|
||||
static struct ads7846_platform_data ads_info = {
|
||||
.vref_delay_usecs = 100,
|
||||
|
|
@ -316,7 +320,7 @@ not possible until the infrastructure knows how to deselect it.
|
|||
|
||||
Then your board initialization code would register that table with the SPI
|
||||
infrastructure, so that it's available later when the SPI master controller
|
||||
driver is registered:
|
||||
driver is registered::
|
||||
|
||||
spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
|
||||
|
||||
|
|
@ -324,12 +328,13 @@ Like with other static board-specific setup, you won't unregister those.
|
|||
|
||||
The widely used "card" style computers bundle memory, cpu, and little else
|
||||
onto a card that's maybe just thirty square centimeters. On such systems,
|
||||
your arch/.../mach-.../board-*.c file would primarily provide information
|
||||
your ``arch/.../mach-.../board-*.c`` file would primarily provide information
|
||||
about the devices on the mainboard into which such a card is plugged. That
|
||||
certainly includes SPI devices hooked up through the card connectors!
|
||||
|
||||
|
||||
NON-STATIC CONFIGURATIONS
|
||||
Non-static Configurations
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Developer boards often play by different rules than product boards, and one
|
||||
example is the potential need to hotplug SPI devices and/or controllers.
|
||||
|
|
@ -349,7 +354,7 @@ How do I write an "SPI Protocol Driver"?
|
|||
Most SPI drivers are currently kernel drivers, but there's also support
|
||||
for userspace drivers. Here we talk only about kernel drivers.
|
||||
|
||||
SPI protocol drivers somewhat resemble platform device drivers:
|
||||
SPI protocol drivers somewhat resemble platform device drivers::
|
||||
|
||||
static struct spi_driver CHIP_driver = {
|
||||
.driver = {
|
||||
|
|
@ -367,6 +372,8 @@ device whose board_info gave a modalias of "CHIP". Your probe() code
|
|||
might look like this unless you're creating a device which is managing
|
||||
a bus (appearing under /sys/class/spi_master).
|
||||
|
||||
::
|
||||
|
||||
static int CHIP_probe(struct spi_device *spi)
|
||||
{
|
||||
struct CHIP *chip;
|
||||
|
|
@ -479,6 +486,8 @@ The main task of this type of driver is to provide an "spi_master".
|
|||
Use spi_alloc_master() to allocate the master, and spi_master_get_devdata()
|
||||
to get the driver-private data allocated for that device.
|
||||
|
||||
::
|
||||
|
||||
struct spi_master *master;
|
||||
struct CONTROLLER *c;
|
||||
|
||||
|
|
@ -503,7 +512,8 @@ If you need to remove your SPI controller driver, spi_unregister_master()
|
|||
will reverse the effect of spi_register_master().
|
||||
|
||||
|
||||
BUS NUMBERING
|
||||
Bus Numbering
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
Bus numbering is important, since that's how Linux identifies a given
|
||||
SPI bus (shared SCK, MOSI, MISO). Valid bus numbers start at zero. On
|
||||
|
|
@ -517,9 +527,10 @@ then be replaced by a dynamically assigned number. You'd then need to treat
|
|||
this as a non-static configuration (see above).
|
||||
|
||||
|
||||
SPI MASTER METHODS
|
||||
SPI Master Methods
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
|
||||
master->setup(struct spi_device *spi)
|
||||
``master->setup(struct spi_device *spi)``
|
||||
This sets up the device clock rate, SPI mode, and word sizes.
|
||||
Drivers may change the defaults provided by board_info, and then
|
||||
call spi_setup(spi) to invoke this routine. It may sleep.
|
||||
|
|
@ -528,37 +539,37 @@ SPI MASTER METHODS
|
|||
change them right away ... otherwise drivers could corrupt I/O
|
||||
that's in progress for other SPI devices.
|
||||
|
||||
** BUG ALERT: for some reason the first version of
|
||||
** many spi_master drivers seems to get this wrong.
|
||||
** When you code setup(), ASSUME that the controller
|
||||
** is actively processing transfers for another device.
|
||||
.. note::
|
||||
|
||||
master->cleanup(struct spi_device *spi)
|
||||
BUG ALERT: for some reason the first version of
|
||||
many spi_master drivers seems to get this wrong.
|
||||
When you code setup(), ASSUME that the controller
|
||||
is actively processing transfers for another device.
|
||||
|
||||
``master->cleanup(struct spi_device *spi)``
|
||||
Your controller driver may use spi_device.controller_state to hold
|
||||
state it dynamically associates with that device. If you do that,
|
||||
be sure to provide the cleanup() method to free that state.
|
||||
|
||||
master->prepare_transfer_hardware(struct spi_master *master)
|
||||
``master->prepare_transfer_hardware(struct spi_master *master)``
|
||||
This will be called by the queue mechanism to signal to the driver
|
||||
that a message is coming in soon, so the subsystem requests the
|
||||
driver to prepare the transfer hardware by issuing this call.
|
||||
This may sleep.
|
||||
|
||||
master->unprepare_transfer_hardware(struct spi_master *master)
|
||||
``master->unprepare_transfer_hardware(struct spi_master *master)``
|
||||
This will be called by the queue mechanism to signal to the driver
|
||||
that there are no more messages pending in the queue and it may
|
||||
relax the hardware (e.g. by power management calls). This may sleep.
|
||||
|
||||
master->transfer_one_message(struct spi_master *master,
|
||||
struct spi_message *mesg)
|
||||
``master->transfer_one_message(struct spi_master *master, struct spi_message *mesg)``
|
||||
The subsystem calls the driver to transfer a single message while
|
||||
queuing transfers that arrive in the meantime. When the driver is
|
||||
finished with this message, it must call
|
||||
spi_finalize_current_message() so the subsystem can issue the next
|
||||
message. This may sleep.
|
||||
|
||||
master->transfer_one(struct spi_master *master, struct spi_device *spi,
|
||||
struct spi_transfer *transfer)
|
||||
``master->transfer_one(struct spi_master *master, struct spi_device *spi, struct spi_transfer *transfer)``
|
||||
The subsystem calls the driver to transfer a single transfer while
|
||||
queuing transfers that arrive in the meantime. When the driver is
|
||||
finished with this transfer, it must call
|
||||
|
|
@ -568,19 +579,20 @@ SPI MASTER METHODS
|
|||
not call your transfer_one callback.
|
||||
|
||||
Return values:
|
||||
negative errno: error
|
||||
0: transfer is finished
|
||||
1: transfer is still in progress
|
||||
|
||||
master->set_cs_timing(struct spi_device *spi, u8 setup_clk_cycles,
|
||||
u8 hold_clk_cycles, u8 inactive_clk_cycles)
|
||||
* negative errno: error
|
||||
* 0: transfer is finished
|
||||
* 1: transfer is still in progress
|
||||
|
||||
``master->set_cs_timing(struct spi_device *spi, u8 setup_clk_cycles, u8 hold_clk_cycles, u8 inactive_clk_cycles)``
|
||||
This method allows SPI client drivers to request SPI master controller
|
||||
for configuring device specific CS setup, hold and inactive timing
|
||||
requirements.
|
||||
|
||||
DEPRECATED METHODS
|
||||
Deprecated Methods
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
|
||||
master->transfer(struct spi_device *spi, struct spi_message *message)
|
||||
``master->transfer(struct spi_device *spi, struct spi_message *message)``
|
||||
This must not sleep. Its responsibility is to arrange that the
|
||||
transfer happens and its complete() callback is issued. The two
|
||||
will normally happen later, after other transfers complete, and
|
||||
|
|
@ -590,7 +602,8 @@ SPI MASTER METHODS
|
|||
implemented.
|
||||
|
||||
|
||||
SPI MESSAGE QUEUE
|
||||
SPI Message Queue
|
||||
^^^^^^^^^^^^^^^^^
|
||||
|
||||
If you are happy with the standard queueing mechanism provided by the
|
||||
SPI subsystem, just implement the queued methods specified above. Using
|
||||
|
|
@ -619,13 +632,13 @@ THANKS TO
|
|||
Contributors to Linux-SPI discussions include (in alphabetical order,
|
||||
by last name):
|
||||
|
||||
Mark Brown
|
||||
David Brownell
|
||||
Russell King
|
||||
Grant Likely
|
||||
Dmitry Pervushin
|
||||
Stephen Street
|
||||
Mark Underwood
|
||||
Andrew Victor
|
||||
Linus Walleij
|
||||
Vitaly Wool
|
||||
- Mark Brown
|
||||
- David Brownell
|
||||
- Russell King
|
||||
- Grant Likely
|
||||
- Dmitry Pervushin
|
||||
- Stephen Street
|
||||
- Mark Underwood
|
||||
- Andrew Victor
|
||||
- Linus Walleij
|
||||
- Vitaly Wool
|
||||
|
|
@ -1,7 +1,13 @@
|
|||
=================
|
||||
SPI userspace API
|
||||
=================
|
||||
|
||||
SPI devices have a limited userspace API, supporting basic half-duplex
|
||||
read() and write() access to SPI slave devices. Using ioctl() requests,
|
||||
full duplex transfers and device I/O configuration are also available.
|
||||
|
||||
::
|
||||
|
||||
#include <fcntl.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/ioctl.h>
|
||||
|
|
@ -39,14 +45,17 @@ device node with a "dev" attribute that will be understood by udev or mdev.
|
|||
busybox; it's less featureful, but often enough.) For a SPI device with
|
||||
chipselect C on bus B, you should see:
|
||||
|
||||
/dev/spidevB.C ... character special device, major number 153 with
|
||||
/dev/spidevB.C ...
|
||||
character special device, major number 153 with
|
||||
a dynamically chosen minor device number. This is the node
|
||||
that userspace programs will open, created by "udev" or "mdev".
|
||||
|
||||
/sys/devices/.../spiB.C ... as usual, the SPI device node will
|
||||
/sys/devices/.../spiB.C ...
|
||||
as usual, the SPI device node will
|
||||
be a child of its SPI master controller.
|
||||
|
||||
/sys/class/spidev/spidevB.C ... created when the "spidev" driver
|
||||
/sys/class/spidev/spidevB.C ...
|
||||
created when the "spidev" driver
|
||||
binds to that device. (Directory or symlink, based on whether
|
||||
or not you enabled the "deprecated sysfs files" Kconfig option.)
|
||||
|
||||
|
|
@ -80,7 +89,8 @@ the SPI_IOC_MESSAGE(N) request.
|
|||
Several ioctl() requests let your driver read or override the device's current
|
||||
settings for data transfer parameters:
|
||||
|
||||
SPI_IOC_RD_MODE, SPI_IOC_WR_MODE ... pass a pointer to a byte which will
|
||||
SPI_IOC_RD_MODE, SPI_IOC_WR_MODE ...
|
||||
pass a pointer to a byte which will
|
||||
return (RD) or assign (WR) the SPI transfer mode. Use the constants
|
||||
SPI_MODE_0..SPI_MODE_3; or if you prefer you can combine SPI_CPOL
|
||||
(clock polarity, idle high iff this is set) or SPI_CPHA (clock phase,
|
||||
|
|
@ -88,22 +98,26 @@ settings for data transfer parameters:
|
|||
Note that this request is limited to SPI mode flags that fit in a
|
||||
single byte.
|
||||
|
||||
SPI_IOC_RD_MODE32, SPI_IOC_WR_MODE32 ... pass a pointer to a uin32_t
|
||||
SPI_IOC_RD_MODE32, SPI_IOC_WR_MODE32 ...
|
||||
pass a pointer to a uin32_t
|
||||
which will return (RD) or assign (WR) the full SPI transfer mode,
|
||||
not limited to the bits that fit in one byte.
|
||||
|
||||
SPI_IOC_RD_LSB_FIRST, SPI_IOC_WR_LSB_FIRST ... pass a pointer to a byte
|
||||
SPI_IOC_RD_LSB_FIRST, SPI_IOC_WR_LSB_FIRST ...
|
||||
pass a pointer to a byte
|
||||
which will return (RD) or assign (WR) the bit justification used to
|
||||
transfer SPI words. Zero indicates MSB-first; other values indicate
|
||||
the less common LSB-first encoding. In both cases the specified value
|
||||
is right-justified in each word, so that unused (TX) or undefined (RX)
|
||||
bits are in the MSBs.
|
||||
|
||||
SPI_IOC_RD_BITS_PER_WORD, SPI_IOC_WR_BITS_PER_WORD ... pass a pointer to
|
||||
SPI_IOC_RD_BITS_PER_WORD, SPI_IOC_WR_BITS_PER_WORD ...
|
||||
pass a pointer to
|
||||
a byte which will return (RD) or assign (WR) the number of bits in
|
||||
each SPI transfer word. The value zero signifies eight bits.
|
||||
|
||||
SPI_IOC_RD_MAX_SPEED_HZ, SPI_IOC_WR_MAX_SPEED_HZ ... pass a pointer to a
|
||||
SPI_IOC_RD_MAX_SPEED_HZ, SPI_IOC_WR_MAX_SPEED_HZ ...
|
||||
pass a pointer to a
|
||||
u32 which will return (RD) or assign (WR) the maximum SPI transfer
|
||||
speed, in Hz. The controller can't necessarily assign that specific
|
||||
clock speed.
|
||||
|
|
@ -695,7 +695,7 @@ static int iio_dummy_remove(struct iio_sw_device *swd)
|
|||
* i2c:
|
||||
* Documentation/i2c/writing-clients.rst
|
||||
* spi:
|
||||
* Documentation/spi/spi-summary
|
||||
* Documentation/spi/spi-summary.rst
|
||||
*/
|
||||
static const struct iio_sw_device_ops iio_dummy_device_ops = {
|
||||
.probe = iio_dummy_probe,
|
||||
|
|
|
|||
|
|
@ -543,7 +543,7 @@ config SPI_PXA2XX
|
|||
help
|
||||
This enables using a PXA2xx or Sodaville SSP port as a SPI master
|
||||
controller. The driver can be configured to use any SSP port and
|
||||
additional documentation can be found a Documentation/spi/pxa2xx.
|
||||
additional documentation can be found a Documentation/spi/pxa2xx.rst.
|
||||
|
||||
config SPI_PXA2XX_PCI
|
||||
def_tristate SPI_PXA2XX && PCI && COMMON_CLK
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
* with a battery powered AVR microcontroller and lots of goodies. You
|
||||
* can use GCC to develop firmware for this.
|
||||
*
|
||||
* See Documentation/spi/butterfly for information about how to build
|
||||
* See Documentation/spi/butterfly.rst for information about how to build
|
||||
* and use this custom parallel port cable.
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@
|
|||
* available (on page 4) here:
|
||||
* http://www.national.com/appinfo/tempsensors/files/LM70LLPEVALmanual.pdf
|
||||
*
|
||||
* Also see Documentation/spi/spi-lm70llp. The SPI<->parport code here is
|
||||
* Also see Documentation/spi/spi-lm70llp.rst. The SPI<->parport code here is
|
||||
* (heavily) based on spi-butterfly by David Brownell.
|
||||
*
|
||||
* The LM70 LLP connects to the PC parallel port in the following manner:
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
*
|
||||
* Copyright (C) 2012 Guenter Roeck <linux@roeck-us.net>
|
||||
*
|
||||
* For further information, see the Documentation/spi/spi-sc18is602 file.
|
||||
* For further information, see the Documentation/spi/spi-sc18is602.rst file.
|
||||
*/
|
||||
|
||||
/**
|
||||
|
|
|
|||
Loading…
Reference in New Issue