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drm/i915: Give names to the CCK_DISPLAY_CLOCK_CONTROL bits

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Avoid using magic values for CCK frequency bits. Also the mask we were
using for the requested frequency was one bit too short. Fix it up.

Note: This also fixes the #define for a mask (spotted by Jesse in his
review).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Add note about mask change.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2014-06-13 13:37:48 +03:00 committed by Daniel Vetter
parent dfcab17e57
commit 9cf33db5eb
2 changed files with 7 additions and 2 deletions
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5
drivers/gpu/drm/i915/i915_reg.h
View file

@ -584,6 +584,11 @@ enum punit_power_well {
#define DSI_PLL_M1_DIV_SHIFT 0
#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
#define DISPLAY_TRUNK_FORCE_ON (1 << 17)
#define DISPLAY_TRUNK_FORCE_OFF (1 << 16)
#define DISPLAY_FREQUENCY_STATUS (0x1f << 8)
#define DISPLAY_FREQUENCY_STATUS_SHIFT 8
#define DISPLAY_FREQUENCY_VALUES (0x1f << 0)
/**
* DOC: DPIO

4
drivers/gpu/drm/i915/intel_display.c
View file

@ -4516,7 +4516,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
mutex_lock(&dev_priv->dpio_lock);
/* adjust cdclk divider */
val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
val &= ~0xf;
val &= ~DISPLAY_FREQUENCY_VALUES;
val |= divider;
vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
mutex_unlock(&dev_priv->dpio_lock);
@ -4553,7 +4553,7 @@ int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
mutex_unlock(&dev_priv->dpio_lock);
divider &= 0xf;
divider &= DISPLAY_FREQUENCY_VALUES;
cur_cdclk = DIV_ROUND_CLOSEST(vco << 1, divider + 1);