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drm/amd/display: clean up header file includes 

Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
hifive-unleashed-5.1
Yue Hin Lau 2017-08-25 16:13:55 -04:00 committed by Alex Deucher
parent d1423e6faf
commit 9cffc57319
4 changed files with 0 additions and 89 deletions
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20
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
View File

@ -27,10 +27,6 @@
#include "core_types.h"
#include "include/grph_object_id.h"
#include "include/fixed31_32.h"
#include "include/logger_interface.h"
#include "reg_helper.h"
#include "dcn10_dpp.h"
#include "basics/conversion.h"
@ -68,22 +64,6 @@ enum dcn10_coef_filter_type_sel {
SCL_COEF_ALPHA_HORZ_FILTER = 5
};
enum lb_memory_config {
/* Enable all 3 pieces of memory */
LB_MEMORY_CONFIG_0 = 0,
/* Enable only the first piece of memory */
LB_MEMORY_CONFIG_1 = 1,
/* Enable only the second piece of memory */
LB_MEMORY_CONFIG_2 = 2,
/* Only applicable in 4:2:0 mode, enable all 3 pieces of memory and the
* last piece of chroma memory used for the luma storage
*/
LB_MEMORY_CONFIG_3 = 3
};
enum dscl_autocal_mode {
AUTOCAL_MODE_OFF = 0,

20
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
View File

@ -27,10 +27,6 @@
#include "core_types.h"
#include "include/grph_object_id.h"
#include "include/fixed31_32.h"
#include "include/logger_interface.h"
#include "reg_helper.h"
#include "dcn10_dpp.h"
#include "basics/conversion.h"
@ -66,22 +62,6 @@ enum dcn10_coef_filter_type_sel {
SCL_COEF_ALPHA_HORZ_FILTER = 5
};
enum lb_memory_config {
/* Enable all 3 pieces of memory */
LB_MEMORY_CONFIG_0 = 0,
/* Enable only the first piece of memory */
LB_MEMORY_CONFIG_1 = 1,
/* Enable only the second piece of memory */
LB_MEMORY_CONFIG_2 = 2,
/* Only applicable in 4:2:0 mode, enable all 3 pieces of memory and the
* last piece of chroma memory used for the luma storage
*/
LB_MEMORY_CONFIG_3 = 3
};
enum dscl_autocal_mode {
AUTOCAL_MODE_OFF = 0,

8
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
View File

@ -100,14 +100,6 @@ enum dscl_mode_sel {
DSCL_MODE_DSCL_BYPASS = 6
};
enum gamut_remap_select {
GAMUT_REMAP_BYPASS = 0,
GAMUT_REMAP_COEFF,
GAMUT_REMAP_COMA_COEFF,
GAMUT_REMAP_COMB_COEFF
};
static void dpp_set_overscan(
struct dcn10_dpp *xfm,
const struct scaler_data *data)

41
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
View File

@ -37,40 +37,6 @@
#define CTX \
ippn10->base.ctx
struct dcn10_input_csc_matrix {
enum dc_color_space color_space;
uint32_t regval[12];
};
static const struct dcn10_input_csc_matrix dcn10_input_csc_matrix[] = {
{COLOR_SPACE_SRGB,
{0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
{COLOR_SPACE_SRGB_LIMITED,
{0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
{COLOR_SPACE_YCBCR601,
{0x2cdd, 0x2000, 0, 0xe991, 0xe926, 0x2000, 0xf4fd, 0x10ef,
0, 0x2000, 0x38b4, 0xe3a6} },
{COLOR_SPACE_YCBCR601_LIMITED,
{0x3353, 0x2568, 0, 0xe400, 0xe5dc, 0x2568, 0xf367, 0x1108,
0, 0x2568, 0x40de, 0xdd3a} },
{COLOR_SPACE_YCBCR709,
{0x3265, 0x2000, 0, 0xe6ce, 0xf105, 0x2000, 0xfa01, 0xa7d, 0,
0x2000, 0x3b61, 0xe24f} },
{COLOR_SPACE_YCBCR709_LIMITED,
{0x39a6, 0x2568, 0, 0xe0d6, 0xeedd, 0x2568, 0xf925, 0x9a8, 0,
0x2568, 0x43ee, 0xdbb2} }
};
enum dcn10_input_csc_select {
INPUT_CSC_SELECT_BYPASS = 0,
INPUT_CSC_SELECT_ICSC,
INPUT_CSC_SELECT_COMA
};
static bool ippn10_cursor_program_control(
struct dcn10_ipp *ippn10,
bool pixel_data_invert,
@ -255,13 +221,6 @@ static void ippn10_cursor_set_position(
/* TODO Handle surface pixel formats other than 4:4:4 */
}
enum pixel_format_description {
PIXEL_FORMAT_FIXED = 0,
PIXEL_FORMAT_FIXED16,
PIXEL_FORMAT_FLOAT
};
/*****************************************/
/* Constructor, Destructor */
/*****************************************/