x86: order functions in cpu/common.c and cpu/common_64.c v2
v2: make 64 bit get c->x86_cache_alignment = c->x86_clfush_size Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>hifive-unleashed-5.1
Yinghai Lu
Ingo Molnar
parent
3da99c9776
commit
9d31d35b5f
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@ -60,6 +60,18 @@ EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
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__u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
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/* Current gdt points %fs at the "master" per-cpu area: after this,
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* it's on the real one. */
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void switch_to_new_gdt(void)
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{
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struct desc_ptr gdt_descr;
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gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
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gdt_descr.size = GDT_SIZE - 1;
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load_gdt(&gdt_descr);
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asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
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}
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static int cachesize_override __cpuinitdata = -1;
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static int disable_x86_serial_nr __cpuinitdata = 1;
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@ -123,15 +135,15 @@ int __cpuinit get_model_name(struct cpuinfo_x86 *c)
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void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
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{
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unsigned int n, dummy, ecx, edx, l2size;
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unsigned int n, dummy, ebx, ecx, edx, l2size;
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n = c->extended_cpuid_level;
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if (n >= 0x80000005) {
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cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
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cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
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printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
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edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
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c->x86_cache_size = (ecx>>24)+(edx>>24);
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edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
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c->x86_cache_size = (ecx>>24) + (edx>>24);
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}
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if (n < 0x80000006) /* Some chips just has a large L1. */
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@ -185,6 +197,51 @@ static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
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return NULL; /* Not found */
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}
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#ifdef CONFIG_X86_HT
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void __cpuinit detect_ht(struct cpuinfo_x86 *c)
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{
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u32 eax, ebx, ecx, edx;
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int index_msb, core_bits;
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cpuid(1, &eax, &ebx, &ecx, &edx);
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if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
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return;
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smp_num_siblings = (ebx & 0xff0000) >> 16;
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if (smp_num_siblings == 1) {
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printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
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} else if (smp_num_siblings > 1) {
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if (smp_num_siblings > NR_CPUS) {
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printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
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smp_num_siblings);
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smp_num_siblings = 1;
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return;
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}
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index_msb = get_count_order(smp_num_siblings);
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c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
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printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
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c->phys_proc_id);
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smp_num_siblings = smp_num_siblings / c->x86_max_cores;
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index_msb = get_count_order(smp_num_siblings);
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core_bits = get_count_order(c->x86_max_cores);
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c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
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((1 << core_bits) - 1);
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if (c->x86_max_cores > 1)
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printk(KERN_INFO "CPU: Processor Core ID: %d\n",
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c->cpu_core_id);
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}
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}
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#endif
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static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
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{
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@ -258,7 +315,26 @@ static int __cpuinit have_cpuid_p(void)
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return flag_is_changeable_p(X86_EFLAGS_ID);
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}
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void __init cpu_detect(struct cpuinfo_x86 *c)
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static void __init early_cpu_support_print(void)
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{
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int i,j;
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struct cpu_dev *cpu_devx;
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printk("KERNEL supported cpus:\n");
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for (i = 0; i < X86_VENDOR_NUM; i++) {
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cpu_devx = cpu_devs[i];
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if (!cpu_devx)
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continue;
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for (j = 0; j < 2; j++) {
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if (!cpu_devx->c_ident[j])
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continue;
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printk(" %s %s\n", cpu_devx->c_vendor,
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cpu_devx->c_ident[j]);
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}
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}
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}
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void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
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{
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/* Get vendor name */
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cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
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@ -267,19 +343,20 @@ void __init cpu_detect(struct cpuinfo_x86 *c)
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(unsigned int *)&c->x86_vendor_id[4]);
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c->x86 = 4;
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/* Intel-defined flags: level 0x00000001 */
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if (c->cpuid_level >= 0x00000001) {
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u32 junk, tfms, cap0, misc;
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cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
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c->x86 = (tfms >> 8) & 15;
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c->x86_model = (tfms >> 4) & 15;
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c->x86 = (tfms >> 8) & 0xf;
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c->x86_model = (tfms >> 4) & 0xf;
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c->x86_mask = tfms & 0xf;
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if (c->x86 == 0xf)
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c->x86 += (tfms >> 20) & 0xff;
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if (c->x86 >= 0x6)
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c->x86_model += ((tfms >> 16) & 0xF) << 4;
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c->x86_mask = tfms & 15;
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c->x86_model += ((tfms >> 16) & 0xf) << 4;
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if (cap0 & (1<<19)) {
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c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
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c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
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c->x86_cache_alignment = c->x86_clflush_size;
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}
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}
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}
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@ -341,6 +418,17 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
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validate_pat_support(c);
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}
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void __init early_cpu_init(void)
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{
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struct cpu_vendor_dev *cvdev;
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for (cvdev = __x86cpuvendor_start; cvdev < __x86cpuvendor_end; cvdev++)
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cpu_devs[cvdev->vendor] = cvdev->cpu_dev;
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early_cpu_support_print();
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early_identify_cpu(&boot_cpu_data);
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}
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/*
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* The NOPL instruction is supposed to exist on all CPUs with
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* family >= 6, unfortunately, that's not true in practice because
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@ -500,7 +588,7 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
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*/
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if (c != &boot_cpu_data) {
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/* AND the already accumulated flags with these */
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for (i = 0 ; i < NCAPINTS ; i++)
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for (i = 0; i < NCAPINTS; i++)
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boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
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}
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@ -529,52 +617,6 @@ void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
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mtrr_ap_init();
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}
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#ifdef CONFIG_X86_HT
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void __cpuinit detect_ht(struct cpuinfo_x86 *c)
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{
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u32 eax, ebx, ecx, edx;
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int index_msb, core_bits;
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cpuid(1, &eax, &ebx, &ecx, &edx);
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if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
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return;
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smp_num_siblings = (ebx & 0xff0000) >> 16;
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if (smp_num_siblings == 1) {
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printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
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} else if (smp_num_siblings > 1) {
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if (smp_num_siblings > NR_CPUS) {
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printk(KERN_WARNING "CPU: Unsupported number of the "
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"siblings %d", smp_num_siblings);
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smp_num_siblings = 1;
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return;
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}
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index_msb = get_count_order(smp_num_siblings);
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c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
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printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
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c->phys_proc_id);
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smp_num_siblings = smp_num_siblings / c->x86_max_cores;
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index_msb = get_count_order(smp_num_siblings) ;
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core_bits = get_count_order(c->x86_max_cores);
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c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
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((1 << core_bits) - 1);
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if (c->x86_max_cores > 1)
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printk(KERN_INFO "CPU: Processor Core ID: %d\n",
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c->cpu_core_id);
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}
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}
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#endif
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static __init int setup_noclflush(char *arg)
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{
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setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
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@ -592,17 +634,17 @@ void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
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vendor = c->x86_vendor_id;
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if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
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printk("%s ", vendor);
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printk(KERN_CONT "%s ", vendor);
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if (!c->x86_model_id[0])
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printk("%d86", c->x86);
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if (c->x86_model_id[0])
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printk(KERN_CONT "%s", c->x86_model_id);
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else
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printk("%s", c->x86_model_id);
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printk(KERN_CONT "%d86", c->x86);
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if (c->x86_mask || c->cpuid_level >= 0)
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printk(" stepping %02x\n", c->x86_mask);
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printk(KERN_CONT " stepping %02x\n", c->x86_mask);
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else
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printk("\n");
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printk(KERN_CONT "\n");
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}
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static __init int setup_disablecpuid(char *arg)
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@ -618,16 +660,6 @@ __setup("clearcpuid=", setup_disablecpuid);
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cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
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void __init early_cpu_init(void)
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{
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struct cpu_vendor_dev *cvdev;
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for (cvdev = __x86cpuvendor_start; cvdev < __x86cpuvendor_end; cvdev++)
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cpu_devs[cvdev->vendor] = cvdev->cpu_dev;
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early_identify_cpu(&boot_cpu_data);
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}
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/* Make sure %fs is initialized properly in idle threads */
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struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
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{
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@ -636,18 +668,6 @@ struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
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return regs;
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}
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/* Current gdt points %fs at the "master" per-cpu area: after this,
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* it's on the real one. */
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void switch_to_new_gdt(void)
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{
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struct desc_ptr gdt_descr;
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gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
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gdt_descr.size = GDT_SIZE - 1;
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load_gdt(&gdt_descr);
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asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
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}
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/*
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* cpu_init() initializes state that is per-CPU. Some data is already
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* initialized (naturally) in the bootstrap process, such as the GDT
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@ -103,9 +103,8 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
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if (n >= 0x80000005) {
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cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
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printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
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"D cache %dK (%d bytes/line)\n",
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edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
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printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
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edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
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c->x86_cache_size = (ecx>>24) + (edx>>24);
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/* On K8 L1 TLB is inclusive, so don't count it */
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c->x86_tlbsize = 0;
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@ -143,8 +142,8 @@ void __cpuinit detect_ht(struct cpuinfo_x86 *c)
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} else if (smp_num_siblings > 1) {
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if (smp_num_siblings > NR_CPUS) {
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printk(KERN_WARNING "CPU: Unsupported number of "
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"siblings %d", smp_num_siblings);
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printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
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smp_num_siblings);
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smp_num_siblings = 1;
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return;
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}
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@ -182,7 +181,7 @@ static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
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if (cpu_devs[i]) {
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if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
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(cpu_devs[i]->c_ident[1] &&
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!strcmp(v, cpu_devs[i]->c_ident[1]))) {
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!strcmp(v, cpu_devs[i]->c_ident[1]))) {
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c->x86_vendor = i;
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this_cpu = cpu_devs[i];
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return;
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@ -217,39 +216,6 @@ static void __init early_cpu_support_print(void)
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}
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}
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/*
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* The NOPL instruction is supposed to exist on all CPUs with
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* family >= 6, unfortunately, that's not true in practice because
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* of early VIA chips and (more importantly) broken virtualizers that
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* are not easy to detect. Hence, probe for it based on first
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* principles.
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*
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* Note: no 64-bit chip is known to lack these, but put the code here
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* for consistency with 32 bits, and to make it utterly trivial to
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* diagnose the problem should it ever surface.
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*/
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static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
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{
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const u32 nopl_signature = 0x888c53b1; /* Random number */
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u32 has_nopl = nopl_signature;
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clear_cpu_cap(c, X86_FEATURE_NOPL);
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if (c->x86 >= 6) {
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asm volatile("\n"
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"1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
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"2:\n"
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" .section .fixup,\"ax\"\n"
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"3: xor %0,%0\n"
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" jmp 2b\n"
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" .previous\n"
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_ASM_EXTABLE(1b,3b)
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: "+a" (has_nopl));
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if (has_nopl == nopl_signature)
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set_cpu_cap(c, X86_FEATURE_NOPL);
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}
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}
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void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
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{
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/* Get vendor name */
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@ -258,6 +224,7 @@ void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
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(unsigned int *)&c->x86_vendor_id[8],
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(unsigned int *)&c->x86_vendor_id[4]);
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c->x86 = 4;
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/* Intel-defined flags: level 0x00000001 */
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if (c->cpuid_level >= 0x00000001) {
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u32 junk, tfms, cap0, misc;
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@ -268,12 +235,11 @@ void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
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if (c->x86 == 0xf)
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c->x86 += (tfms >> 20) & 0xff;
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if (c->x86 >= 0x6)
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c->x86_model += ((tfms >> 16) & 0xF) << 4;
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if (cap0 & (1<<19))
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c->x86_model += ((tfms >> 16) & 0xf) << 4;
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if (cap0 & (1<<19)) {
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c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
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} else {
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/* Have CPUID level 0 only - unheard of */
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c->x86 = 4;
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c->x86_cache_alignment = c->x86_clflush_size;
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}
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}
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}
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@ -283,9 +249,6 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
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u32 tfms, xlvl;
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u32 ebx;
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/* Initialize the standard set of capabilities */
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/* Note that the vendor-specific code below might override */
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/* Intel-defined flags: level 0x00000001 */
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if (c->cpuid_level >= 0x00000001) {
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u32 capability, excap;
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@ -361,6 +324,39 @@ void __init early_cpu_init(void)
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early_identify_cpu(&boot_cpu_data);
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}
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/*
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* The NOPL instruction is supposed to exist on all CPUs with
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* family >= 6, unfortunately, that's not true in practice because
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* of early VIA chips and (more importantly) broken virtualizers that
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* are not easy to detect. Hence, probe for it based on first
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* principles.
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*
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* Note: no 64-bit chip is known to lack these, but put the code here
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* for consistency with 32 bits, and to make it utterly trivial to
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* diagnose the problem should it ever surface.
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*/
|
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static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
|
||||
{
|
||||
const u32 nopl_signature = 0x888c53b1; /* Random number */
|
||||
u32 has_nopl = nopl_signature;
|
||||
|
||||
clear_cpu_cap(c, X86_FEATURE_NOPL);
|
||||
if (c->x86 >= 6) {
|
||||
asm volatile("\n"
|
||||
"1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
|
||||
"2:\n"
|
||||
" .section .fixup,\"ax\"\n"
|
||||
"3: xor %0,%0\n"
|
||||
" jmp 2b\n"
|
||||
" .previous\n"
|
||||
_ASM_EXTABLE(1b,3b)
|
||||
: "+a" (has_nopl));
|
||||
|
||||
if (has_nopl == nopl_signature)
|
||||
set_cpu_cap(c, X86_FEATURE_NOPL);
|
||||
}
|
||||
}
|
||||
|
||||
static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
|
||||
{
|
||||
c->extended_cpuid_level = 0;
|
||||
|
|
@ -448,7 +444,7 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
|
|||
|
||||
}
|
||||
|
||||
void __cpuinit identify_boot_cpu(void)
|
||||
void __init identify_boot_cpu(void)
|
||||
{
|
||||
identify_cpu(&boot_cpu_data);
|
||||
}
|
||||
|
|
@ -460,13 +456,6 @@ void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
|
|||
mtrr_ap_init();
|
||||
}
|
||||
|
||||
static __init int setup_noclflush(char *arg)
|
||||
{
|
||||
setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
|
||||
return 1;
|
||||
}
|
||||
__setup("noclflush", setup_noclflush);
|
||||
|
||||
struct msr_range {
|
||||
unsigned min;
|
||||
unsigned max;
|
||||
|
|
@ -510,6 +499,13 @@ static __init int setup_show_msr(char *arg)
|
|||
}
|
||||
__setup("show_msr=", setup_show_msr);
|
||||
|
||||
static __init int setup_noclflush(char *arg)
|
||||
{
|
||||
setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
|
||||
return 1;
|
||||
}
|
||||
__setup("noclflush", setup_noclflush);
|
||||
|
||||
void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
|
||||
{
|
||||
if (c->x86_model_id[0])
|
||||
|
|
|
|||
Loading…
Reference in New Issue