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DT: MIPS: ralink: add MT7620A dts files

Add a dtsi file for MT7620A SoC and a sample dts file.

Signed-off-by: John Crispin <blogic@openwrt.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Patchwork: http://patchwork.linux-mips.org/patch/5190/
hifive-unleashed-5.1
John Crispin 2013-04-12 06:27:41 +00:00 committed by Ralf Baechle
parent 6fbfe90e58
commit 9d50094dfe
4 changed files with 79 additions and 0 deletions

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@ -46,6 +46,10 @@ choice
bool "RT3883 eval kit"
depends on SOC_RT3883
config DTB_MT7620A_EVAL
bool "MT7620A eval kit"
depends on SOC_MT7620
endchoice
endif

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@ -1,3 +1,4 @@
obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
obj-$(CONFIG_DTB_MT7620A_EVAL) := mt7620a_eval.dtb.o

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@ -0,0 +1,58 @@
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ralink,mtk7620a-soc";
cpus {
cpu@0 {
compatible = "mips,mips24KEc";
};
};
cpuintc: cpuintc@0 {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
palmbus@10000000 {
compatible = "palmbus";
reg = <0x10000000 0x200000>;
ranges = <0x0 0x10000000 0x1FFFFF>;
#address-cells = <1>;
#size-cells = <1>;
sysc@0 {
compatible = "ralink,mt7620a-sysc";
reg = <0x0 0x100>;
};
intc: intc@200 {
compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
reg = <0x200 0x100>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
};
memc@300 {
compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
reg = <0x300 0x100>;
};
uartlite@c00 {
compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
interrupt-parent = <&intc>;
interrupts = <12>;
reg-shift = <2>;
};
};
};

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@ -0,0 +1,16 @@
/dts-v1/;
/include/ "mt7620a.dtsi"
/ {
compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
model = "Ralink MT7620A evaluation board";
memory@0 {
reg = <0x0 0x2000000>;
};
chosen {
bootargs = "console=ttyS0,57600";
};
};