i40e: split some code in i40e_reset_vf into helpers
A future patch is going to want to re-use some of the code in i40e_reset_vf, so lets break up the beginning and ending parts into their own helper functions. The first function will be used to initialize the reset on a VF, while the second function will be used to finalize the reset and restore functionality. Change-ID: I48df808b8bf09de3c2ed8c521f57b3f0ab9e5907 Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>hifive-unleashed-5.1
parent
1de81c2d07
commit
9dc2e41738
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@ -923,22 +923,19 @@ static int i40e_quiesce_vf_pci(struct i40e_vf *vf)
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}
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}
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/**
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/**
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* i40e_reset_vf
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* i40e_trigger_vf_reset
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* @vf: pointer to the VF structure
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* @vf: pointer to the VF structure
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* @flr: VFLR was issued or not
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* @flr: VFLR was issued or not
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*
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*
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* reset the VF
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* Trigger hardware to start a reset for a particular VF. Expects the caller
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* to wait the proper amount of time to allow hardware to reset the VF before
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* it cleans up and restores VF functionality.
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**/
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**/
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void i40e_reset_vf(struct i40e_vf *vf, bool flr)
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static void i40e_trigger_vf_reset(struct i40e_vf *vf, bool flr)
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{
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{
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struct i40e_pf *pf = vf->pf;
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struct i40e_pf *pf = vf->pf;
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struct i40e_hw *hw = &pf->hw;
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struct i40e_hw *hw = &pf->hw;
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u32 reg, reg_idx, bit_idx;
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u32 reg, reg_idx, bit_idx;
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bool rsd = false;
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int i;
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if (test_and_set_bit(__I40E_VF_DISABLE, &pf->state))
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return;
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/* warn the VF */
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/* warn the VF */
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clear_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states);
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clear_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states);
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@ -970,37 +967,22 @@ void i40e_reset_vf(struct i40e_vf *vf, bool flr)
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if (i40e_quiesce_vf_pci(vf))
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if (i40e_quiesce_vf_pci(vf))
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dev_err(&pf->pdev->dev, "VF %d PCI transactions stuck\n",
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dev_err(&pf->pdev->dev, "VF %d PCI transactions stuck\n",
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vf->vf_id);
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vf->vf_id);
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}
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/* poll VPGEN_VFRSTAT reg to make sure
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/**
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* that reset is complete
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* i40e_cleanup_reset_vf
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*/
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* @vf: pointer to the VF structure
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for (i = 0; i < 10; i++) {
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*
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/* VF reset requires driver to first reset the VF and then
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* Cleanup a VF after the hardware reset is finished. Expects the caller to
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* poll the status register to make sure that the reset
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* have verified whether the reset is finished properly, and ensure the
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* completed successfully. Due to internal HW FIFO flushes,
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* minimum amount of wait time has passed.
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* we must wait 10ms before the register will be valid.
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**/
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*/
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static void i40e_cleanup_reset_vf(struct i40e_vf *vf)
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usleep_range(10000, 20000);
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{
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reg = rd32(hw, I40E_VPGEN_VFRSTAT(vf->vf_id));
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struct i40e_pf *pf = vf->pf;
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if (reg & I40E_VPGEN_VFRSTAT_VFRD_MASK) {
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struct i40e_hw *hw = &pf->hw;
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rsd = true;
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u32 reg;
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break;
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}
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}
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if (flr)
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usleep_range(10000, 20000);
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if (!rsd)
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dev_err(&pf->pdev->dev, "VF reset check timeout on VF %d\n",
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vf->vf_id);
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/* On initial reset, we won't have any queues */
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if (vf->lan_vsi_idx == 0)
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goto complete_reset;
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i40e_vsi_stop_rings(pf->vsi[vf->lan_vsi_idx]);
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complete_reset:
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/* free VF resources to begin resetting the VSI state */
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/* free VF resources to begin resetting the VSI state */
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i40e_free_vf_res(vf);
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i40e_free_vf_res(vf);
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@ -1035,6 +1017,59 @@ complete_reset:
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* request resources immediately after setting this flag.
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* request resources immediately after setting this flag.
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*/
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*/
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wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_id), I40E_VFR_VFACTIVE);
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wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_id), I40E_VFR_VFACTIVE);
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}
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/**
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* i40e_reset_vf
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* @vf: pointer to the VF structure
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* @flr: VFLR was issued or not
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*
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* reset the VF
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**/
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void i40e_reset_vf(struct i40e_vf *vf, bool flr)
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{
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struct i40e_pf *pf = vf->pf;
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struct i40e_hw *hw = &pf->hw;
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bool rsd = false;
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u32 reg;
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int i;
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/* If VFs have been disabled, there is no need to reset */
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if (test_and_set_bit(__I40E_VF_DISABLE, &pf->state))
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return;
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i40e_trigger_vf_reset(vf, flr);
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/* poll VPGEN_VFRSTAT reg to make sure
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* that reset is complete
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*/
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for (i = 0; i < 10; i++) {
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/* VF reset requires driver to first reset the VF and then
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* poll the status register to make sure that the reset
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* completed successfully. Due to internal HW FIFO flushes,
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* we must wait 10ms before the register will be valid.
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*/
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usleep_range(10000, 20000);
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reg = rd32(hw, I40E_VPGEN_VFRSTAT(vf->vf_id));
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if (reg & I40E_VPGEN_VFRSTAT_VFRD_MASK) {
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rsd = true;
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break;
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}
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}
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if (flr)
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usleep_range(10000, 20000);
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if (!rsd)
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dev_err(&pf->pdev->dev, "VF reset check timeout on VF %d\n",
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vf->vf_id);
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usleep_range(10000, 20000);
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/* On initial reset, we don't have any queues to disable */
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if (vf->lan_vsi_idx != 0)
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i40e_vsi_stop_rings(pf->vsi[vf->lan_vsi_idx]);
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i40e_cleanup_reset_vf(vf);
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i40e_flush(hw);
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i40e_flush(hw);
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clear_bit(__I40E_VF_DISABLE, &pf->state);
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clear_bit(__I40E_VF_DISABLE, &pf->state);
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