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MIPS: Remove execution hazard barriers for Octeon. 

The Octeon has no execution hazards, so we can remove them and save an
instruction per TLB handler invocation.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Reviewed by: David VomLehn <dvomlehn@cisco.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
hifive-unleashed-5.1
David Daney 2009-05-12 12:41:54 -07:00 committed by Ralf Baechle
parent 41f0e4d041
commit 9e290a19f2
1 changed files with 1 additions and 0 deletions
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arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
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@ -47,6 +47,7 @@
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 1
#define cpu_has_mips_r2_exec_hazard 0
#define cpu_has_dsp 0
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0