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ARC updates for 5.8-rc5

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- User build systems to pass -mcpu
 
  - Fix potential EFA clobber in syscall handler
 
  - Fix ARCompact 2 levels of interrupts build
 
  - Detect newer HS CPU releases
 
  - miscll other fixes
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Merge tag 'arc-5.8-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc

Pull ARC fixes from Vineet Gupta:

 - User build systems to pass -mcpu

 - Fix potential EFA clobber in syscall handler

 - Fix ARCompact 2 levels of interrupts build

 - Detect newer HS CPU releases

 - misc other fixes

* tag 'arc-5.8-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  ARCv2: support loop buffer (LPB) disabling
  ARC: build: remove deprecated toggle for arc700 builds
  ARC: build: allow users to specify -mcpu
  ARCv2: boot log: detect newer/upconing HS3x/HS4x releases
  ARC: elf: use right ELF_ARCH
  ARC: [arcompact] fix bitrot with 2 levels of interrupt
  ARC: entry: fix potential EFA clobber when TIF_SYSCALL_TRACE
This commit is contained in:
Linus Torvalds 2020-07-07 13:43:43 -07:00
parent a6bc851ffe 10011f7d95
commit 9e4d769621
7 changed files with 59 additions and 27 deletions
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15
arch/arc/Kconfig
View file

@ -170,6 +170,15 @@ config ARC_CPU_HS
endchoice
config ARC_TUNE_MCPU
string "Override default -mcpu compiler flag"
default ""
help
Override default -mcpu=xxx compiler flag (which is set depending on
the ISA version) with the specified value.
NOTE: If specified flag isn't supported by current compiler the
ISA default value will be used as a fallback.
config CPU_BIG_ENDIAN
bool "Enable Big Endian Mode"
help
@ -465,6 +474,12 @@ config ARC_IRQ_NO_AUTOSAVE
This is programmable and can be optionally disabled in which case
software INTERRUPT_PROLOGUE/EPILGUE do the needed work
config ARC_LPB_DISABLE
bool "Disable loop buffer (LPB)"
help
On HS cores, loop buffer (LPB) is programmable in runtime and can
be optionally disabled.
endif # ISA_ARCV2
endmenu # "ARC CPU Configuration"

21
arch/arc/Makefile
View file

@ -10,8 +10,25 @@ CROSS_COMPILE := $(call cc-cross-prefix, arc-linux- arceb-linux-)
endif
cflags-y += -fno-common -pipe -fno-builtin -mmedium-calls -D__linux__
cflags-$(CONFIG_ISA_ARCOMPACT) += -mA7
cflags-$(CONFIG_ISA_ARCV2) += -mcpu=hs38
tune-mcpu-def-$(CONFIG_ISA_ARCOMPACT) := -mcpu=arc700
tune-mcpu-def-$(CONFIG_ISA_ARCV2) := -mcpu=hs38
ifeq ($(CONFIG_ARC_TUNE_MCPU),"")
cflags-y += $(tune-mcpu-def-y)
else
tune-mcpu := $(shell echo $(CONFIG_ARC_TUNE_MCPU))
tune-mcpu-ok := $(call cc-option-yn, $(tune-mcpu))
ifeq ($(tune-mcpu-ok),y)
cflags-y += $(tune-mcpu)
else
# The flag provided by 'CONFIG_ARC_TUNE_MCPU' option isn't known by this compiler
# (probably the compiler is too old). Use ISA default mcpu flag instead as a safe option.
$(warning ** WARNING ** CONFIG_ARC_TUNE_MCPU flag '$(tune-mcpu)' is unknown, fallback to '$(tune-mcpu-def-y)')
cflags-y += $(tune-mcpu-def-y)
endif
endif
ifdef CONFIG_ARC_CURR_IN_REG
# For a global register defintion, make sure it gets passed to every file

2
arch/arc/include/asm/elf.h
View file

@ -19,7 +19,7 @@
#define R_ARC_32_PCREL 0x31
/*to set parameters in the core dumps */
#define ELF_ARCH EM_ARCOMPACT
#define ELF_ARCH EM_ARC_INUSE
#define ELF_CLASS ELFCLASS32
#ifdef CONFIG_CPU_BIG_ENDIAN

5
arch/arc/include/asm/irqflags-compact.h
View file

@ -90,6 +90,9 @@ static inline void arch_local_irq_restore(unsigned long flags)
/*
* Unconditionally Enable IRQs
*/
#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
extern void arch_local_irq_enable(void);
#else
static inline void arch_local_irq_enable(void)
{
unsigned long temp;
@ -102,7 +105,7 @@ static inline void arch_local_irq_enable(void)
: "n"((STATUS_E1_MASK | STATUS_E2_MASK))
: "cc", "memory");
}
#endif
/*
* Unconditionally Disable IRQs

16
arch/arc/kernel/entry.S
View file

@ -165,7 +165,6 @@ END(EV_Extension)
tracesys:
; save EFA in case tracer wants the PC of traced task
; using ERET won't work since next-PC has already committed
lr r12, [efa]
GET_CURR_TASK_FIELD_PTR TASK_THREAD, r11
st r12, [r11, THREAD_FAULT_ADDR] ; thread.fault_address
@ -208,15 +207,9 @@ tracesys_exit:
; Breakpoint TRAP
; ---------------------------------------------
trap_with_param:
; stop_pc info by gdb needs this info
lr r0, [efa]
mov r0, r12 ; EFA in case ptracer/gdb wants stop_pc
mov r1, sp
; Now that we have read EFA, it is safe to do "fake" rtie
; and get out of CPU exception mode
FAKE_RET_FROM_EXCPN
; Save callee regs in case gdb wants to have a look
; SP will grow up by size of CALLEE Reg-File
; NOTE: clobbers r12
@ -243,6 +236,10 @@ ENTRY(EV_Trap)
EXCEPTION_PROLOGUE
lr r12, [efa]
FAKE_RET_FROM_EXCPN
;============ TRAP 1 :breakpoints
; Check ECR for trap with arg (PROLOGUE ensures r10 has ECR)
bmsk.f 0, r10, 7
@ -250,9 +247,6 @@ ENTRY(EV_Trap)
;============ TRAP (no param): syscall top level
; First return from Exception to pure K mode (Exception/IRQs renabled)
FAKE_RET_FROM_EXCPN
; If syscall tracing ongoing, invoke pre-post-hooks
GET_CURR_THR_INFO_FLAGS r10
btst r10, TIF_SYSCALL_TRACE

8
arch/arc/kernel/head.S
View file

@ -59,6 +59,14 @@
bclr r5, r5, STATUS_AD_BIT
#endif
kflag r5
#ifdef CONFIG_ARC_LPB_DISABLE
lr r5, [ARC_REG_LPB_BUILD]
breq r5, 0, 1f ; LPB doesn't exist
mov r5, 1
sr r5, [ARC_REG_LPB_CTRL]
1:
#endif /* CONFIG_ARC_LPB_DISABLE */
#endif
; Config DSP_CTRL properly, so kernel may use integer multiply,
; multiply-accumulate, and divide operations

19
arch/arc/kernel/setup.c
View file

@ -58,10 +58,12 @@ static const struct id_to_str arc_legacy_rel[] = {
{ 0x00, NULL }
};
static const struct id_to_str arc_cpu_rel[] = {
static const struct id_to_str arc_hs_ver54_rel[] = {
/* UARCH.MAJOR, Release */
{ 0, "R3.10a"},
{ 1, "R3.50a"},
{ 2, "R3.60a"},
{ 3, "R4.00a"},
{ 0xFF, NULL }
};
@ -117,12 +119,6 @@ static void decode_arc_core(struct cpuinfo_arc *cpu)
struct bcr_uarch_build_arcv2 uarch;
const struct id_to_str *tbl;
/*
* Up until (including) the first core4 release (0x54) things were
* simple: AUX IDENTITY.ARCVER was sufficient to identify arc family
* and release: 0x50 to 0x53 was HS38, 0x54 was HS48 (dual issue)
*/
if (cpu->core.family < 0x54) { /* includes arc700 */
for (tbl = &arc_legacy_rel[0]; tbl->id != 0; tbl++) {
@ -143,11 +139,10 @@ static void decode_arc_core(struct cpuinfo_arc *cpu)
}
/*
* However the subsequent HS release (same 0x54) allow HS38 or HS48
* configurations and encode this info in a different BCR.
* The BCR was introduced in 0x54 so can't be read unconditionally.
* Initial HS cores bumped AUX IDENTITY.ARCVER for each release until
* ARCVER 0x54 which introduced AUX MICRO_ARCH_BUILD and subsequent
* releases only update it.
*/
READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch);
if (uarch.prod == 4) {
@ -158,7 +153,7 @@ static void decode_arc_core(struct cpuinfo_arc *cpu)
cpu->name = "HS38";
}
for (tbl = &arc_cpu_rel[0]; tbl->id != 0xFF; tbl++) {
for (tbl = &arc_hs_ver54_rel[0]; tbl->id != 0xFF; tbl++) {
if (uarch.maj == tbl->id) {
cpu->release = tbl->str;
break;