drm/nouveau/fifo/gk104: add nvenc plumbing
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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@ -11,6 +11,8 @@ struct kepler_channel_gpfifo_a_v0 {
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#define NVA06F_V0_ENGINE_MSPDEC 0x00000020
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#define NVA06F_V0_ENGINE_MSPPP 0x00000040
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#define NVA06F_V0_ENGINE_MSENC 0x00000080
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#define NVA06F_V0_ENGINE_NVENC0 0x00000400
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#define NVA06F_V0_ENGINE_NVENC1 0x00000800
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#define NVA06F_V0_ENGINE_CE0 0x00010000
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#define NVA06F_V0_ENGINE_CE1 0x00020000
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#define NVA06F_V0_ENGINE_CE2 0x00040000
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@ -735,6 +735,8 @@ gk104_fifo_oneinit(struct nvkm_fifo *base)
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case 0x0000000b: engidx = NVKM_ENGINE_MSENC; break;
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case 0x0000000c: engidx = NVKM_ENGINE_VIC; break;
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case 0x0000000d: engidx = NVKM_ENGINE_SEC; break;
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case 0x0000000e: engidx = NVKM_ENGINE_NVENC0; break;
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case 0x0000000f: engidx = NVKM_ENGINE_NVENC1; break;
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break;
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default:
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break;
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@ -67,6 +67,8 @@ gk104_fifo_gpfifo_engine_addr(struct nvkm_engine *engine)
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case NVKM_ENGINE_MSPPP : return 0x0260;
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case NVKM_ENGINE_MSVLD : return 0x0270;
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case NVKM_ENGINE_MSENC : return 0x0290;
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case NVKM_ENGINE_NVENC0: return 0x02100290;
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case NVKM_ENGINE_NVENC1: return 0x0210;
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default:
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WARN_ON(1);
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return 0;
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@ -77,9 +79,9 @@ static int
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gk104_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base,
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struct nvkm_engine *engine, bool suspend)
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{
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const u32 offset = gk104_fifo_gpfifo_engine_addr(engine);
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struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
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struct nvkm_gpuobj *inst = chan->base.inst;
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u32 offset = gk104_fifo_gpfifo_engine_addr(engine);
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int ret;
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ret = gk104_fifo_gpfifo_kick(chan);
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@ -88,8 +90,12 @@ gk104_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base,
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if (offset) {
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nvkm_kmap(inst);
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nvkm_wo32(inst, offset + 0x00, 0x00000000);
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nvkm_wo32(inst, offset + 0x04, 0x00000000);
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nvkm_wo32(inst, (offset & 0xffff) + 0x00, 0x00000000);
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nvkm_wo32(inst, (offset & 0xffff) + 0x04, 0x00000000);
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if ((offset >>= 16)) {
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nvkm_wo32(inst, offset + 0x00, 0x00000000);
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nvkm_wo32(inst, offset + 0x04, 0x00000000);
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}
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nvkm_done(inst);
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}
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@ -100,15 +106,21 @@ static int
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gk104_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base,
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struct nvkm_engine *engine)
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{
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const u32 offset = gk104_fifo_gpfifo_engine_addr(engine);
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struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
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struct nvkm_gpuobj *inst = chan->base.inst;
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u32 offset = gk104_fifo_gpfifo_engine_addr(engine);
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if (offset) {
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u64 addr = chan->engn[engine->subdev.index].vma.offset;
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u64 addr = chan->engn[engine->subdev.index].vma.offset;
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u32 datalo = lower_32_bits(addr) | 0x00000004;
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u32 datahi = upper_32_bits(addr);
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nvkm_kmap(inst);
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nvkm_wo32(inst, offset + 0x00, lower_32_bits(addr) | 4);
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nvkm_wo32(inst, offset + 0x04, upper_32_bits(addr));
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nvkm_wo32(inst, (offset & 0xffff) + 0x00, datalo);
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nvkm_wo32(inst, (offset & 0xffff) + 0x04, datahi);
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if ((offset >>= 16)) {
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nvkm_wo32(inst, offset + 0x00, datalo);
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nvkm_wo32(inst, offset + 0x04, datahi);
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}
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nvkm_done(inst);
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}
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@ -331,6 +343,8 @@ gk104_fifo_gpfifo[] = {
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{ NVA06F_V0_ENGINE_MSPDEC, BIT_ULL(NVKM_ENGINE_MSPDEC) },
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{ NVA06F_V0_ENGINE_MSPPP , BIT_ULL(NVKM_ENGINE_MSPPP ) },
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{ NVA06F_V0_ENGINE_MSENC , BIT_ULL(NVKM_ENGINE_MSENC ) },
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{ NVA06F_V0_ENGINE_NVENC0, BIT_ULL(NVKM_ENGINE_NVENC0) },
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{ NVA06F_V0_ENGINE_NVENC1, BIT_ULL(NVKM_ENGINE_NVENC1) },
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{ NVA06F_V0_ENGINE_CE0 , BIT_ULL(NVKM_ENGINE_CE0 ) },
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{ NVA06F_V0_ENGINE_CE1 , BIT_ULL(NVKM_ENGINE_CE1 ) },
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{ NVA06F_V0_ENGINE_CE2 , BIT_ULL(NVKM_ENGINE_CE2 ) },
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