drm/r100/kms: Emit cache flush to the end of command buffer. (v2)
Cache flush is required in case CPU is accessing rendered data. This fixes glean/readPixSanity test case and random rendering errors in sauerbraten and warzone2100. v2 Fix comment ordering in r100_fence_ring_emit and remove extra defines added in first version. Signed-off-by: Pauli Nieminen <suokkos@gmail.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -354,11 +354,17 @@ u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
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return RREG32(RADEON_CRTC2_CRNT_FRAME);
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}
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/* Who ever call radeon_fence_emit should call ring_lock and ask
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* for enough space (today caller are ib schedule and buffer move) */
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void r100_fence_ring_emit(struct radeon_device *rdev,
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struct radeon_fence *fence)
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{
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/* Who ever call radeon_fence_emit should call ring_lock and ask
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* for enough space (today caller are ib schedule and buffer move) */
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/* We have to make sure that caches are flushed before
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* CPU might read something from VRAM. */
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radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
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radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
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radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
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radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
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/* Wait until IDLE & CLEAN */
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radeon_ring_write(rdev, PACKET0(0x1720, 0));
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radeon_ring_write(rdev, (1 << 16) | (1 << 17));
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