parisc: Use ldcw instruction for SMP spinlock release barrier
There are only a couple of instructions that can function as a memory barrier on parisc. Currently, we use the sync instruction as a memory barrier when releasing a spinlock. However, the ldcw instruction is a better barrier when we have a handy memory location since it operates in the cache on coherent machines. This patch updates the spinlock release code to use ldcw. I also changed the "stw,ma" instructions to "stw" instructions as it is not an adequate barrier. Signed-off-by: John David Anglin <dave.anglin@bell.net> Signed-off-by: Helge Deller <deller@gmx.de>hifive-unleashed-5.2
John David Anglin
Helge Deller
parent
6c63ef8001
commit
9e5c602186
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@ -37,7 +37,11 @@ static inline void arch_spin_unlock(arch_spinlock_t *x)
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volatile unsigned int *a;
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a = __ldcw_align(x);
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#ifdef CONFIG_SMP
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(void) __ldcw(a);
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#else
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mb();
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#endif
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*a = 1;
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}
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@ -471,8 +471,9 @@
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nop
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LDREG 0(\ptp),\pte
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bb,<,n \pte,_PAGE_PRESENT_BIT,3f
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LDCW 0(\tmp),\tmp1
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b \fault
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stw,ma \spc,0(\tmp)
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stw \spc,0(\tmp)
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99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
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#endif
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2: LDREG 0(\ptp),\pte
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@ -481,20 +482,22 @@
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.endm
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/* Release pa_tlb_lock lock without reloading lock address. */
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.macro tlb_unlock0 spc,tmp
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.macro tlb_unlock0 spc,tmp,tmp1
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#ifdef CONFIG_SMP
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98: or,COND(=) %r0,\spc,%r0
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stw,ma \spc,0(\tmp)
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LDCW 0(\tmp),\tmp1
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or,COND(=) %r0,\spc,%r0
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stw \spc,0(\tmp)
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99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
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#endif
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.endm
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/* Release pa_tlb_lock lock. */
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.macro tlb_unlock1 spc,tmp
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.macro tlb_unlock1 spc,tmp,tmp1
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#ifdef CONFIG_SMP
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98: load_pa_tlb_lock \tmp
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99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
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tlb_unlock0 \spc,\tmp
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tlb_unlock0 \spc,\tmp,\tmp1
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#endif
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.endm
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@ -1177,7 +1180,7 @@ dtlb_miss_20w:
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idtlbt pte,prot
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tlb_unlock1 spc,t0
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tlb_unlock1 spc,t0,t1
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rfir
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nop
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@ -1203,7 +1206,7 @@ nadtlb_miss_20w:
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idtlbt pte,prot
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tlb_unlock1 spc,t0
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tlb_unlock1 spc,t0,t1
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rfir
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nop
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@ -1237,7 +1240,7 @@ dtlb_miss_11:
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mtsp t1, %sr1 /* Restore sr1 */
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tlb_unlock1 spc,t0
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tlb_unlock1 spc,t0,t1
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rfir
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nop
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@ -1270,7 +1273,7 @@ nadtlb_miss_11:
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mtsp t1, %sr1 /* Restore sr1 */
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tlb_unlock1 spc,t0
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tlb_unlock1 spc,t0,t1
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rfir
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nop
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@ -1299,7 +1302,7 @@ dtlb_miss_20:
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idtlbt pte,prot
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tlb_unlock1 spc,t0
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tlb_unlock1 spc,t0,t1
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rfir
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nop
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@ -1327,7 +1330,7 @@ nadtlb_miss_20:
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idtlbt pte,prot
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tlb_unlock1 spc,t0
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tlb_unlock1 spc,t0,t1
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rfir
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nop
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@ -1434,7 +1437,7 @@ itlb_miss_20w:
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iitlbt pte,prot
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tlb_unlock1 spc,t0
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tlb_unlock1 spc,t0,t1
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rfir
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nop
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@ -1458,7 +1461,7 @@ naitlb_miss_20w:
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iitlbt pte,prot
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tlb_unlock1 spc,t0
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tlb_unlock1 spc,t0,t1
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rfir
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nop
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@ -1492,7 +1495,7 @@ itlb_miss_11:
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mtsp t1, %sr1 /* Restore sr1 */
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tlb_unlock1 spc,t0
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tlb_unlock1 spc,t0,t1
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rfir
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nop
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@ -1516,7 +1519,7 @@ naitlb_miss_11:
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mtsp t1, %sr1 /* Restore sr1 */
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tlb_unlock1 spc,t0
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tlb_unlock1 spc,t0,t1
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rfir
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nop
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@ -1546,7 +1549,7 @@ itlb_miss_20:
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iitlbt pte,prot
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tlb_unlock1 spc,t0
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tlb_unlock1 spc,t0,t1
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rfir
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nop
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@ -1566,7 +1569,7 @@ naitlb_miss_20:
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iitlbt pte,prot
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tlb_unlock1 spc,t0
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tlb_unlock1 spc,t0,t1
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rfir
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nop
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@ -1596,7 +1599,7 @@ dbit_trap_20w:
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idtlbt pte,prot
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tlb_unlock0 spc,t0
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tlb_unlock0 spc,t0,t1
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rfir
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nop
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#else
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@ -1622,7 +1625,7 @@ dbit_trap_11:
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mtsp t1, %sr1 /* Restore sr1 */
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tlb_unlock0 spc,t0
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tlb_unlock0 spc,t0,t1
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rfir
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nop
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@ -1642,7 +1645,7 @@ dbit_trap_20:
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idtlbt pte,prot
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tlb_unlock0 spc,t0
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tlb_unlock0 spc,t0,t1
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rfir
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nop
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#endif
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@ -640,7 +640,9 @@ cas_action:
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sub,<> %r28, %r25, %r0
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2: stw %r24, 0(%r26)
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/* Free lock */
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sync
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#ifdef CONFIG_SMP
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LDCW 0(%sr2,%r20), %r1 /* Barrier */
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#endif
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stw %r20, 0(%sr2,%r20)
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#if ENABLE_LWS_DEBUG
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/* Clear thread register indicator */
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@ -655,7 +657,9 @@ cas_action:
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3:
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/* Error occurred on load or store */
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/* Free lock */
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sync
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#ifdef CONFIG_SMP
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LDCW 0(%sr2,%r20), %r1 /* Barrier */
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#endif
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stw %r20, 0(%sr2,%r20)
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#if ENABLE_LWS_DEBUG
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stw %r0, 4(%sr2,%r20)
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@ -857,7 +861,9 @@ cas2_action:
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cas2_end:
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/* Free lock */
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sync
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#ifdef CONFIG_SMP
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LDCW 0(%sr2,%r20), %r1 /* Barrier */
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#endif
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stw %r20, 0(%sr2,%r20)
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/* Enable interrupts */
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ssm PSW_SM_I, %r0
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@ -868,7 +874,9 @@ cas2_end:
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22:
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/* Error occurred on load or store */
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/* Free lock */
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sync
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#ifdef CONFIG_SMP
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LDCW 0(%sr2,%r20), %r1 /* Barrier */
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#endif
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stw %r20, 0(%sr2,%r20)
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ssm PSW_SM_I, %r0
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ldo 1(%r0),%r28
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