IOMMU fixes for v3.5-rc1
Two patches are in here which fix AMD IOMMU specific issues. One patch fixes a long-standing warning on resume because the amd_iommu_resume function enabled interrupts. The other patch fixes a deadlock in an error-path of the page-fault request handling code of the IOMMU driver. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJPz1wQAAoJECvwRC2XARrj6FkQAJsF4LuzKXQcAybUnzMZq3E8 g2ii0uknErrNgsAjnooH1aTzq0vo5Ps/ZLj84XJER+V0vYkD574vhKs9dzu8Y8at xv20AH+Uei+0tUVy2WCPglVwZaSrQB+eVm0oqWIqNKnp28q3pVsns8iccp+Anqxz VV8IqJchfAUXdB8EGJCbZkT+YGfNcFGXx2bfYyiNBUvXOfE6fzzXZly0AXWcm9GB XLYxLdtZ5RYG874IMKnQvAUCXAfN21snK61i1hcx1aoZynzVAFvbf1SnzcINuX4M SqXdies6Ui8S2Ndvl4wZXfEkFYRL48v2+tpjp9bxEvvfX40WCbUHJ3M7Z+LoayvP Xgpshp5JaoXcgp3Rgyhyd22HzKMP291NyjObrKBgf6QxFaQSz16OIsFN9aKxEiyc QCMJyLgfKeBDWM64Zw2u526RIIMENPIim+YH5R2jN08kZUYd+5r611E5BcxE0I6Z uuuDi+eY+UCiBVyofckuJz4yVnNIZroRSFoldfsbv7BvHCE4QNOCyG5JrdVzL0e3 81dgmMDaPCr2ga2NjJ2hebYJLNYNc4IIf/zwK8OoT/S5sD53zU42WIQ2Ug91hXmw ep04oobprN764te1VOaSbm9FNUCD3ykf6xLtqX9gKp254mZ/w46YaMR0GSphrUbS YBNnrSbIq+1z5MtruD/V =qLIK -----END PGP SIGNATURE----- Merge tag 'iommu-fixes-3.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull IOMMU fixes from Joerg Roedel: "Two patches are in here which fix AMD IOMMU specific issues. One patch fixes a long-standing warning on resume because the amd_iommu_resume function enabled interrupts. The other patch fixes a deadlock in an error-path of the page-fault request handling code of the IOMMU driver. * tag 'iommu-fixes-3.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: iommu/amd: Fix deadlock in ppr-handling error path iommu/amd: Cache pdev pointer to root-bridge
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9e68447f5b
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@ -547,26 +547,12 @@ static void iommu_poll_events(struct amd_iommu *iommu)
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u32 head)
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static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
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{
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struct amd_iommu_fault fault;
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volatile u64 *raw;
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int i;
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INC_STATS_COUNTER(pri_requests);
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raw = (u64 *)(iommu->ppr_log + head);
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/*
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* Hardware bug: Interrupt may arrive before the entry is written to
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* memory. If this happens we need to wait for the entry to arrive.
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*/
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for (i = 0; i < LOOP_TIMEOUT; ++i) {
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if (PPR_REQ_TYPE(raw[0]) != 0)
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break;
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udelay(1);
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}
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if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
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pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
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return;
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@ -578,12 +564,6 @@ static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u32 head)
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fault.tag = PPR_TAG(raw[0]);
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fault.flags = PPR_FLAGS(raw[0]);
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/*
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* To detect the hardware bug we need to clear the entry
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* to back to zero.
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*/
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raw[0] = raw[1] = 0;
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atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
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}
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@ -595,25 +575,62 @@ static void iommu_poll_ppr_log(struct amd_iommu *iommu)
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if (iommu->ppr_log == NULL)
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return;
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/* enable ppr interrupts again */
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writel(MMIO_STATUS_PPR_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET);
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spin_lock_irqsave(&iommu->lock, flags);
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head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
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tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
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while (head != tail) {
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volatile u64 *raw;
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u64 entry[2];
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int i;
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/* Handle PPR entry */
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iommu_handle_ppr_entry(iommu, head);
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raw = (u64 *)(iommu->ppr_log + head);
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/* Update and refresh ring-buffer state*/
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/*
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* Hardware bug: Interrupt may arrive before the entry is
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* written to memory. If this happens we need to wait for the
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* entry to arrive.
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*/
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for (i = 0; i < LOOP_TIMEOUT; ++i) {
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if (PPR_REQ_TYPE(raw[0]) != 0)
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break;
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udelay(1);
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}
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/* Avoid memcpy function-call overhead */
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entry[0] = raw[0];
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entry[1] = raw[1];
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/*
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* To detect the hardware bug we need to clear the entry
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* back to zero.
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*/
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raw[0] = raw[1] = 0UL;
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/* Update head pointer of hardware ring-buffer */
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head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
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writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
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/*
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* Release iommu->lock because ppr-handling might need to
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* re-aquire it
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*/
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spin_unlock_irqrestore(&iommu->lock, flags);
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/* Handle PPR entry */
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iommu_handle_ppr_entry(iommu, entry);
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spin_lock_irqsave(&iommu->lock, flags);
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/* Refresh ring-buffer information */
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head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
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tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
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}
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/* enable ppr interrupts again */
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writel(MMIO_STATUS_PPR_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET);
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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@ -1029,6 +1029,9 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
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if (!iommu->dev)
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return 1;
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iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
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PCI_DEVFN(0, 0));
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iommu->cap_ptr = h->cap_ptr;
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iommu->pci_seg = h->pci_seg;
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iommu->mmio_phys = h->mmio_phys;
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@ -1323,20 +1326,16 @@ static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
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{
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int i, j;
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u32 ioc_feature_control;
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struct pci_dev *pdev = NULL;
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struct pci_dev *pdev = iommu->root_pdev;
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/* RD890 BIOSes may not have completely reconfigured the iommu */
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if (!is_rd890_iommu(iommu->dev))
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if (!is_rd890_iommu(iommu->dev) || !pdev)
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return;
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/*
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* First, we need to ensure that the iommu is enabled. This is
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* controlled by a register in the northbridge
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*/
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pdev = pci_get_bus_and_slot(iommu->dev->bus->number, PCI_DEVFN(0, 0));
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if (!pdev)
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return;
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/* Select Northbridge indirect register 0x75 and enable writing */
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pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
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@ -1346,8 +1345,6 @@ static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
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if (!(ioc_feature_control & 0x1))
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pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
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pci_dev_put(pdev);
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/* Restore the iommu BAR */
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pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
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iommu->stored_addr_lo);
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@ -481,6 +481,9 @@ struct amd_iommu {
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/* Pointer to PCI device of this IOMMU */
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struct pci_dev *dev;
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/* Cache pdev to root device for resume quirks */
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struct pci_dev *root_pdev;
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/* physical address of MMIO space */
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u64 mmio_phys;
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/* virtual address of MMIO space */
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