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MIPS: EMMA2RH: Remove EMMA2RH_CPU_CASCADE 

Although all EMMAxxx SoCs can support IP2 and IP3 hardware interrupts,
current EMMA2RH plat_irq_dispatch() supports IP2 only.  We can make it
configurable in the future, but for the time being, would like to make
things explicitly allcated to IP2 in accordance with plat_irq_dispatch().

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1388/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
hifive-unleashed-5.1
Shinya Kuribayashi 2010-06-17 20:36:13 +09:00 committed by Ralf Baechle
parent eebacda40f
commit 9e6f39698a
2 changed files with 1 additions and 2 deletions
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2
arch/mips/emma/markeins/irq.c
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@ -301,7 +301,7 @@ void __init arch_init_irq(void)
/* setup cascade interrupts */
setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
setup_irq(MIPS_CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
setup_irq(MIPS_CPU_IRQ_BASE + 2, &irq_cascade);
}
asmlinkage void plat_irq_dispatch(void)

1
arch/mips/include/asm/emma/emma2rh.h
View File

@ -101,7 +101,6 @@
#define NUM_EMMA2RH_IRQ 96
#define CPU_EMMA2RH_CASCADE 2
#define EMMA2RH_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
/*