Merge 5.9-rc5 into driver-core-next
We need the driver core changes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>zero-sugar-mainline-defconfig
Greg Kroah-Hartman
commit
9ef8638bd8
|
|
@ -111,6 +111,7 @@ ForEachMacros:
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|||
- 'css_for_each_descendant_pre'
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||||
- 'device_for_each_child_node'
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||||
- 'dma_fence_chain_for_each'
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||||
- 'do_for_each_ftrace_op'
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||||
- 'drm_atomic_crtc_for_each_plane'
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||||
- 'drm_atomic_crtc_state_for_each_plane'
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||||
- 'drm_atomic_crtc_state_for_each_plane_state'
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||||
|
|
@ -136,6 +137,7 @@ ForEachMacros:
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|||
- 'for_each_active_dev_scope'
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- 'for_each_active_drhd_unit'
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- 'for_each_active_iommu'
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- 'for_each_aggr_pgid'
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- 'for_each_available_child_of_node'
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- 'for_each_bio'
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- 'for_each_board_func_rsrc'
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@ -234,6 +236,7 @@ ForEachMacros:
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- 'for_each_node_state'
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- 'for_each_node_with_cpus'
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- 'for_each_node_with_property'
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- 'for_each_nonreserved_multicast_dest_pgid'
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- 'for_each_of_allnodes'
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- 'for_each_of_allnodes_from'
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- 'for_each_of_cpu_node'
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@ -256,6 +259,7 @@ ForEachMacros:
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- 'for_each_pci_dev'
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- 'for_each_pci_msi_entry'
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- 'for_each_pcm_streams'
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- 'for_each_physmem_range'
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- 'for_each_populated_zone'
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- 'for_each_possible_cpu'
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- 'for_each_present_cpu'
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|
@ -265,6 +269,8 @@ ForEachMacros:
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- 'for_each_process_thread'
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- 'for_each_property_of_node'
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- 'for_each_registered_fb'
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- 'for_each_requested_gpio'
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- 'for_each_requested_gpio_in_range'
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- 'for_each_reserved_mem_region'
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- 'for_each_rtd_codec_dais'
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- 'for_each_rtd_codec_dais_rollback'
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@ -278,12 +284,17 @@ ForEachMacros:
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- 'for_each_sg'
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- 'for_each_sg_dma_page'
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- 'for_each_sg_page'
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- 'for_each_sgtable_dma_page'
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- 'for_each_sgtable_dma_sg'
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- 'for_each_sgtable_page'
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- 'for_each_sgtable_sg'
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- 'for_each_sibling_event'
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- 'for_each_subelement'
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- 'for_each_subelement_extid'
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- 'for_each_subelement_id'
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- '__for_each_thread'
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- 'for_each_thread'
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- 'for_each_unicast_dest_pgid'
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- 'for_each_wakeup_source'
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- 'for_each_zone'
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- 'for_each_zone_zonelist'
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@ -464,6 +475,7 @@ ForEachMacros:
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|||
- 'v4l2_m2m_for_each_src_buf'
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- 'v4l2_m2m_for_each_src_buf_safe'
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||||
- 'virtio_device_for_each_vq'
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- 'while_for_each_ftrace_op'
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- 'xa_for_each'
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- 'xa_for_each_marked'
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- 'xa_for_each_range'
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|
|
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|||
1
.mailmap
1
.mailmap
|
|
@ -308,6 +308,7 @@ Tony Luck <tony.luck@intel.com>
|
|||
TripleX Chung <xxx.phy@gmail.com> <triplex@zh-kernel.org>
|
||||
TripleX Chung <xxx.phy@gmail.com> <zhongyu@18mail.cn>
|
||||
Tsuneo Yoshioka <Tsuneo.Yoshioka@f-secure.com>
|
||||
Tycho Andersen <tycho@tycho.pizza> <tycho@tycho.ws>
|
||||
Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de>
|
||||
Uwe Kleine-König <ukl@pengutronix.de>
|
||||
Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com>
|
||||
|
|
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|
|
@ -49,7 +49,7 @@ checking of rcu_dereference() primitives:
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|||
is invoked by both RCU-sched readers and updaters.
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||||
srcu_dereference_check(p, c):
|
||||
Use explicit check expression "c" along with
|
||||
srcu_read_lock_held()(). This is useful in code that
|
||||
srcu_read_lock_held(). This is useful in code that
|
||||
is invoked by both SRCU readers and updaters.
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||||
rcu_dereference_raw(p):
|
||||
Don't check. (Use sparingly, if at all.)
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||||
|
|
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|||
|
|
@ -1662,7 +1662,7 @@
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|||
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||||
98 block User-mode virtual block device
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||||
0 = /dev/ubda First user-mode block device
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||||
16 = /dev/udbb Second user-mode block device
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||||
16 = /dev/ubdb Second user-mode block device
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||||
...
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||||
|
||||
Partitions are handled in the same way as for IDE
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||||
|
|
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|||
|
|
@ -156,7 +156,6 @@ against. Possible keywords are:::
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|||
``line-range`` cannot contain space, e.g.
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||||
"1-30" is valid range but "1 - 30" is not.
|
||||
|
||||
``module=foo`` combined keyword=value form is interchangably accepted
|
||||
|
||||
The meanings of each keyword are:
|
||||
|
||||
|
|
|
|||
|
|
@ -1434,7 +1434,7 @@ on the feature, restricting the viewing angles.
|
|||
|
||||
|
||||
DYTC Lapmode sensor
|
||||
------------------
|
||||
-------------------
|
||||
|
||||
sysfs: dytc_lapmode
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||||
|
||||
|
|
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|||
|
|
@ -123,7 +123,9 @@ Energy-Performance Bias (EPB) knob (otherwise), which means that the processor's
|
|||
internal P-state selection logic is expected to focus entirely on performance.
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||||
|
||||
This will override the EPP/EPB setting coming from the ``sysfs`` interface
|
||||
(see `Energy vs Performance Hints`_ below).
|
||||
(see `Energy vs Performance Hints`_ below). Moreover, any attempts to change
|
||||
the EPP/EPB to a value different from 0 ("performance") via ``sysfs`` in this
|
||||
configuration will be rejected.
|
||||
|
||||
Also, in this configuration the range of P-states available to the processor's
|
||||
internal P-state selection logic is always restricted to the upper boundary
|
||||
|
|
@ -564,8 +566,8 @@ Energy-Performance Preference (EPP) knob (if supported) or its
|
|||
Energy-Performance Bias (EPB) knob. It is also possible to write a positive
|
||||
integer value between 0 to 255, if the EPP feature is present. If the EPP
|
||||
feature is not present, writing integer value to this attribute is not
|
||||
supported. In this case, user can use
|
||||
"/sys/devices/system/cpu/cpu*/power/energy_perf_bias" interface.
|
||||
supported. In this case, user can use the
|
||||
"/sys/devices/system/cpu/cpu*/power/energy_perf_bias" interface.
|
||||
|
||||
[Note that tasks may by migrated from one CPU to another by the scheduler's
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||||
load-balancing algorithm and if different energy vs performance hints are
|
||||
|
|
|
|||
|
|
@ -1,66 +0,0 @@
|
|||
Texas Instruments K3 Interrupt Aggregator
|
||||
=========================================
|
||||
|
||||
The Interrupt Aggregator (INTA) provides a centralized machine
|
||||
which handles the termination of system events to that they can
|
||||
be coherently processed by the host(s) in the system. A maximum
|
||||
of 64 events can be mapped to a single interrupt.
|
||||
|
||||
|
||||
Interrupt Aggregator
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||||
+-----------------------------------------+
|
||||
| Intmap VINT |
|
||||
| +--------------+ +------------+ |
|
||||
m ------>| | vint | bit | | 0 |.....|63| vint0 |
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||||
. | +--------------+ +------------+ | +------+
|
||||
. | . . | | HOST |
|
||||
Globalevents ------>| . . |------>| IRQ |
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||||
. | . . | | CTRL |
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||||
. | . . | +------+
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||||
n ------>| +--------------+ +------------+ |
|
||||
| | vint | bit | | 0 |.....|63| vintx |
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||||
| +--------------+ +------------+ |
|
||||
| |
|
||||
+-----------------------------------------+
|
||||
|
||||
Configuration of these Intmap registers that maps global events to vint is done
|
||||
by a system controller (like the Device Memory and Security Controller on K3
|
||||
AM654 SoC). Driver should request the system controller to get the range
|
||||
of global events and vints assigned to the requesting host. Management
|
||||
of these requested resources should be handled by driver and requests
|
||||
system controller to map specific global event to vint, bit pair.
|
||||
|
||||
Communication between the host processor running an OS and the system
|
||||
controller happens through a protocol called TI System Control Interface
|
||||
(TISCI protocol). For more details refer:
|
||||
Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
|
||||
|
||||
TISCI Interrupt Aggregator Node:
|
||||
-------------------------------
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||||
- compatible: Must be "ti,sci-inta".
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||||
- reg: Should contain registers location and length.
|
||||
- interrupt-controller: Identifies the node as an interrupt controller
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||||
- msi-controller: Identifies the node as an MSI controller.
|
||||
- interrupt-parent: phandle of irq parent.
|
||||
- ti,sci: Phandle to TI-SCI compatible System controller node.
|
||||
- ti,sci-dev-id: TISCI device ID of the Interrupt Aggregator.
|
||||
- ti,sci-rm-range-vint: Array of TISCI subtype ids representing vints(inta
|
||||
outputs) range within this INTA, assigned to the
|
||||
requesting host context.
|
||||
- ti,sci-rm-range-global-event: Array of TISCI subtype ids representing the
|
||||
global events range reaching this IA and are assigned
|
||||
to the requesting host context.
|
||||
|
||||
Example:
|
||||
--------
|
||||
main_udmass_inta: interrupt-controller@33d00000 {
|
||||
compatible = "ti,sci-inta";
|
||||
reg = <0x0 0x33d00000 0x0 0x100000>;
|
||||
interrupt-controller;
|
||||
msi-controller;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <179>;
|
||||
ti,sci-rm-range-vint = <0x0>;
|
||||
ti,sci-rm-range-global-event = <0x1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-inta.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments K3 Interrupt Aggregator
|
||||
|
||||
maintainers:
|
||||
- Lokesh Vutla <lokeshvutla@ti.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
|
||||
|
||||
description: |
|
||||
The Interrupt Aggregator (INTA) provides a centralized machine
|
||||
which handles the termination of system events to that they can
|
||||
be coherently processed by the host(s) in the system. A maximum
|
||||
of 64 events can be mapped to a single interrupt.
|
||||
|
||||
Interrupt Aggregator
|
||||
+-----------------------------------------+
|
||||
| Intmap VINT |
|
||||
| +--------------+ +------------+ |
|
||||
m ------>| | vint | bit | | 0 |.....|63| vint0 |
|
||||
. | +--------------+ +------------+ | +------+
|
||||
. | . . | | HOST |
|
||||
Globalevents ------>| . . |----->| IRQ |
|
||||
. | . . | | CTRL |
|
||||
. | . . | +------+
|
||||
n ------>| +--------------+ +------------+ |
|
||||
| | vint | bit | | 0 |.....|63| vintx |
|
||||
| +--------------+ +------------+ |
|
||||
| |
|
||||
+-----------------------------------------+
|
||||
|
||||
Configuration of these Intmap registers that maps global events to vint is
|
||||
done by a system controller (like the Device Memory and Security Controller
|
||||
on AM654 SoC). Driver should request the system controller to get the range
|
||||
of global events and vints assigned to the requesting host. Management
|
||||
of these requested resources should be handled by driver and requests
|
||||
system controller to map specific global event to vint, bit pair.
|
||||
|
||||
Communication between the host processor running an OS and the system
|
||||
controller happens through a protocol called TI System Control Interface
|
||||
(TISCI protocol).
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: ti,sci-inta
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
msi-controller: true
|
||||
|
||||
ti,interrupt-ranges:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
description: |
|
||||
Interrupt ranges that converts the INTA output hw irq numbers
|
||||
to parents's input interrupt numbers.
|
||||
items:
|
||||
items:
|
||||
- description: |
|
||||
"output_irq" specifies the base for inta output irq
|
||||
- description: |
|
||||
"parent's input irq" specifies the base for parent irq
|
||||
- description: |
|
||||
"limit" specifies the limit for translation
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupt-controller
|
||||
- msi-controller
|
||||
- ti,sci
|
||||
- ti,sci-dev-id
|
||||
- ti,interrupt-ranges
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
main_udmass_inta: msi-controller@33d00000 {
|
||||
compatible = "ti,sci-inta";
|
||||
reg = <0x0 0x33d00000 0x0 0x100000>;
|
||||
interrupt-controller;
|
||||
msi-controller;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <179>;
|
||||
ti,interrupt-ranges = <0 0 256>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,82 +0,0 @@
|
|||
Texas Instruments K3 Interrupt Router
|
||||
=====================================
|
||||
|
||||
The Interrupt Router (INTR) module provides a mechanism to mux M
|
||||
interrupt inputs to N interrupt outputs, where all M inputs are selectable
|
||||
to be driven per N output. An Interrupt Router can either handle edge triggered
|
||||
or level triggered interrupts and that is fixed in hardware.
|
||||
|
||||
Interrupt Router
|
||||
+----------------------+
|
||||
| Inputs Outputs |
|
||||
+-------+ | +------+ +-----+ |
|
||||
| GPIO |----------->| | irq0 | | 0 | | Host IRQ
|
||||
+-------+ | +------+ +-----+ | controller
|
||||
| . . | +-------+
|
||||
+-------+ | . . |----->| IRQ |
|
||||
| INTA |----------->| . . | +-------+
|
||||
+-------+ | . +-----+ |
|
||||
| +------+ | N | |
|
||||
| | irqM | +-----+ |
|
||||
| +------+ |
|
||||
| |
|
||||
+----------------------+
|
||||
|
||||
There is one register per output (MUXCNTL_N) that controls the selection.
|
||||
Configuration of these MUXCNTL_N registers is done by a system controller
|
||||
(like the Device Memory and Security Controller on K3 AM654 SoC). System
|
||||
controller will keep track of the used and unused registers within the Router.
|
||||
Driver should request the system controller to get the range of GIC IRQs
|
||||
assigned to the requesting hosts. It is the drivers responsibility to keep
|
||||
track of Host IRQs.
|
||||
|
||||
Communication between the host processor running an OS and the system
|
||||
controller happens through a protocol called TI System Control Interface
|
||||
(TISCI protocol). For more details refer:
|
||||
Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
|
||||
|
||||
TISCI Interrupt Router Node:
|
||||
----------------------------
|
||||
Required Properties:
|
||||
- compatible: Must be "ti,sci-intr".
|
||||
- ti,intr-trigger-type: Should be one of the following:
|
||||
1: If intr supports edge triggered interrupts.
|
||||
4: If intr supports level triggered interrupts.
|
||||
- interrupt-controller: Identifies the node as an interrupt controller
|
||||
- #interrupt-cells: Specifies the number of cells needed to encode an
|
||||
interrupt source. The value should be 2.
|
||||
First cell should contain the TISCI device ID of source
|
||||
Second cell should contain the interrupt source offset
|
||||
within the device.
|
||||
- ti,sci: Phandle to TI-SCI compatible System controller node.
|
||||
- ti,sci-dst-id: TISCI device ID of the destination IRQ controller.
|
||||
- ti,sci-rm-range-girq: Array of TISCI subtype ids representing the host irqs
|
||||
assigned to this interrupt router. Each subtype id
|
||||
corresponds to a range of host irqs.
|
||||
|
||||
For more details on TISCI IRQ resource management refer:
|
||||
https://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/rm/rm_irq.html
|
||||
|
||||
Example:
|
||||
--------
|
||||
The following example demonstrates both interrupt router node and the consumer
|
||||
node(main gpio) on the AM654 SoC:
|
||||
|
||||
main_intr: interrupt-controller0 {
|
||||
compatible = "ti,sci-intr";
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <2>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dst-id = <56>;
|
||||
ti,sci-rm-range-girq = <0x1>;
|
||||
};
|
||||
|
||||
main_gpio0: gpio@600000 {
|
||||
...
|
||||
interrupt-parent = <&main_intr>;
|
||||
interrupts = <57 256>, <57 257>, <57 258>,
|
||||
<57 259>, <57 260>, <57 261>;
|
||||
...
|
||||
};
|
||||
|
|
@ -0,0 +1,102 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments K3 Interrupt Router
|
||||
|
||||
maintainers:
|
||||
- Lokesh Vutla <lokeshvutla@ti.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
|
||||
|
||||
description: |
|
||||
The Interrupt Router (INTR) module provides a mechanism to mux M
|
||||
interrupt inputs to N interrupt outputs, where all M inputs are selectable
|
||||
to be driven per N output. An Interrupt Router can either handle edge
|
||||
triggered or level triggered interrupts and that is fixed in hardware.
|
||||
|
||||
Interrupt Router
|
||||
+----------------------+
|
||||
| Inputs Outputs |
|
||||
+-------+ | +------+ +-----+ |
|
||||
| GPIO |----------->| | irq0 | | 0 | | Host IRQ
|
||||
+-------+ | +------+ +-----+ | controller
|
||||
| . . | +-------+
|
||||
+-------+ | . . |----->| IRQ |
|
||||
| INTA |----------->| . . | +-------+
|
||||
+-------+ | . +-----+ |
|
||||
| +------+ | N | |
|
||||
| | irqM | +-----+ |
|
||||
| +------+ |
|
||||
| |
|
||||
+----------------------+
|
||||
|
||||
There is one register per output (MUXCNTL_N) that controls the selection.
|
||||
Configuration of these MUXCNTL_N registers is done by a system controller
|
||||
(like the Device Memory and Security Controller on K3 AM654 SoC). System
|
||||
controller will keep track of the used and unused registers within the Router.
|
||||
Driver should request the system controller to get the range of GIC IRQs
|
||||
assigned to the requesting hosts. It is the drivers responsibility to keep
|
||||
track of Host IRQs.
|
||||
|
||||
Communication between the host processor running an OS and the system
|
||||
controller happens through a protocol called TI System Control Interface
|
||||
(TISCI protocol).
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: ti,sci-intr
|
||||
|
||||
ti,intr-trigger-type:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [1, 4]
|
||||
description: |
|
||||
Should be one of the following.
|
||||
1 = If intr supports edge triggered interrupts.
|
||||
4 = If intr supports level triggered interrupts.
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 1
|
||||
description: |
|
||||
The 1st cell should contain interrupt router input hw number.
|
||||
|
||||
ti,interrupt-ranges:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
description: |
|
||||
Interrupt ranges that converts the INTR output hw irq numbers
|
||||
to parents's input interrupt numbers.
|
||||
items:
|
||||
items:
|
||||
- description: |
|
||||
"output_irq" specifies the base for intr output irq
|
||||
- description: |
|
||||
"parent's input irq" specifies the base for parent irq
|
||||
- description: |
|
||||
"limit" specifies the limit for translation
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- ti,intr-trigger-type
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
- ti,sci
|
||||
- ti,sci-dev-id
|
||||
- ti,interrupt-ranges
|
||||
|
||||
examples:
|
||||
- |
|
||||
main_gpio_intr: interrupt-controller0 {
|
||||
compatible = "ti,sci-intr";
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <131>;
|
||||
ti,interrupt-ranges = <0 360 32>;
|
||||
};
|
||||
|
|
@ -30,9 +30,13 @@ allOf:
|
|||
then:
|
||||
properties:
|
||||
clock-output-names:
|
||||
items:
|
||||
- const: clk_out_sd0
|
||||
- const: clk_in_sd0
|
||||
oneOf:
|
||||
- items:
|
||||
- const: clk_out_sd0
|
||||
- const: clk_in_sd0
|
||||
- items:
|
||||
- const: clk_out_sd1
|
||||
- const: clk_in_sd1
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -50,6 +50,8 @@ Optional properties:
|
|||
error caused by stop clock(fifo full)
|
||||
Valid range = [0:0x7]. if not present, default value is 0.
|
||||
applied to compatible "mediatek,mt2701-mmc".
|
||||
- resets: Phandle and reset specifier pair to softreset line of MSDC IP.
|
||||
- reset-names: Should be "hrst".
|
||||
|
||||
Examples:
|
||||
mmc0: mmc@11230000 {
|
||||
|
|
|
|||
|
|
@ -15,8 +15,15 @@ Required properties:
|
|||
- "nvidia,tegra210-sdhci": for Tegra210
|
||||
- "nvidia,tegra186-sdhci": for Tegra186
|
||||
- "nvidia,tegra194-sdhci": for Tegra194
|
||||
- clocks : Must contain one entry, for the module clock.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clocks: For Tegra210, Tegra186 and Tegra194 must contain two entries.
|
||||
One for the module clock and one for the timeout clock.
|
||||
For all other Tegra devices, must contain a single entry for
|
||||
the module clock. See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: For Tegra210, Tegra186 and Tegra194 must contain the
|
||||
strings 'sdhci' and 'tmclk' to represent the module and
|
||||
the timeout clocks, respectively.
|
||||
For all other Tegra devices must contain the string 'sdhci'
|
||||
to represent the module clock.
|
||||
- resets : Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names : Must include the following entries:
|
||||
|
|
@ -99,7 +106,7 @@ Optional properties for Tegra210, Tegra186 and Tegra194:
|
|||
|
||||
Example:
|
||||
sdhci@700b0000 {
|
||||
compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
|
||||
compatible = "nvidia,tegra124-sdhci";
|
||||
reg = <0x0 0x700b0000 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
|
||||
|
|
@ -115,3 +122,22 @@ sdhci@700b0000 {
|
|||
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@700b0000 {
|
||||
compatible = "nvidia,tegra210-sdhci";
|
||||
reg = <0x0 0x700b0000 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
|
||||
<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
|
||||
clock-names = "sdhci", "tmclk";
|
||||
resets = <&tegra_car 14>;
|
||||
reset-names = "sdhci";
|
||||
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
|
||||
pinctrl-0 = <&sdmmc1_3v3>;
|
||||
pinctrl-1 = <&sdmmc1_1v8>;
|
||||
nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
|
||||
nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
|
||||
nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
|
||||
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Distributed Switch Architecture Device Tree Bindings
|
||||
----------------------------------------------------
|
||||
|
||||
See Documentation/devicetree/bindings/net/dsa/dsa.yaml for the documenation.
|
||||
See Documentation/devicetree/bindings/net/dsa/dsa.yaml for the documentation.
|
||||
|
|
|
|||
|
|
@ -23,8 +23,8 @@ Required properties:
|
|||
|
||||
- compatible:
|
||||
Must be one of :
|
||||
"brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs
|
||||
"brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
|
||||
"brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on BRCMSTB SoCs
|
||||
"brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi" : Second Instance of MSPI
|
||||
BRCMSTB SoCs
|
||||
"brcm,spi-bcm7425-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
|
||||
BRCMSTB SoCs
|
||||
|
|
@ -36,8 +36,8 @@ Required properties:
|
|||
BRCMSTB SoCs
|
||||
"brcm,spi-bcm7278-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
|
||||
BRCMSTB SoCs
|
||||
"brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi" : MSPI+BSPI on Cygnus, NSP
|
||||
"brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi" : NS2 SoCs
|
||||
"brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on Cygnus, NSP
|
||||
"brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi" : NS2 SoCs
|
||||
|
||||
- reg:
|
||||
Define the bases and ranges of the associated I/O address spaces.
|
||||
|
|
@ -86,7 +86,7 @@ BRCMSTB SoC Example:
|
|||
spi@f03e3400 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-brcmstb-qspi";
|
||||
compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi";
|
||||
reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>;
|
||||
reg-names = "cs_reg", "mspi", "bspi";
|
||||
interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>;
|
||||
|
|
@ -149,7 +149,7 @@ BRCMSTB SoC Example:
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&upg_fixed>;
|
||||
compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-brcmstb-mspi";
|
||||
compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi";
|
||||
reg = <0xf0416000 0x180>;
|
||||
reg-names = "mspi";
|
||||
interrupts = <0x14>;
|
||||
|
|
@ -160,7 +160,7 @@ BRCMSTB SoC Example:
|
|||
iProc SoC Example:
|
||||
|
||||
qspi: spi@18027200 {
|
||||
compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
|
||||
compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
|
||||
reg = <0x18027200 0x184>,
|
||||
<0x18027000 0x124>,
|
||||
<0x1811c408 0x004>,
|
||||
|
|
@ -191,7 +191,7 @@ iProc SoC Example:
|
|||
NS2 SoC Example:
|
||||
|
||||
qspi: spi@66470200 {
|
||||
compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi";
|
||||
compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";
|
||||
reg = <0x66470200 0x184>,
|
||||
<0x66470000 0x124>,
|
||||
<0x67017408 0x004>,
|
||||
|
|
|
|||
|
|
@ -179,7 +179,7 @@ DMA Fence uABI/Sync File
|
|||
:internal:
|
||||
|
||||
Indefinite DMA Fences
|
||||
~~~~~~~~~~~~~~~~~~~~
|
||||
~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
At various times &dma_fence with an indefinite time until dma_fence_wait()
|
||||
finishes have been proposed. Examples include:
|
||||
|
|
|
|||
|
|
@ -6,9 +6,9 @@ API to implement a new FPGA bridge
|
|||
|
||||
* struct :c:type:`fpga_bridge` — The FPGA Bridge structure
|
||||
* struct :c:type:`fpga_bridge_ops` — Low level Bridge driver ops
|
||||
* :c:func:`devm_fpga_bridge_create()` — Allocate and init a bridge struct
|
||||
* :c:func:`fpga_bridge_register()` — Register a bridge
|
||||
* :c:func:`fpga_bridge_unregister()` — Unregister a bridge
|
||||
* devm_fpga_bridge_create() — Allocate and init a bridge struct
|
||||
* fpga_bridge_register() — Register a bridge
|
||||
* fpga_bridge_unregister() — Unregister a bridge
|
||||
|
||||
.. kernel-doc:: include/linux/fpga/fpga-bridge.h
|
||||
:functions: fpga_bridge
|
||||
|
|
|
|||
|
|
@ -104,9 +104,9 @@ API for implementing a new FPGA Manager driver
|
|||
* ``fpga_mgr_states`` — Values for :c:member:`fpga_manager->state`.
|
||||
* struct :c:type:`fpga_manager` — the FPGA manager struct
|
||||
* struct :c:type:`fpga_manager_ops` — Low level FPGA manager driver ops
|
||||
* :c:func:`devm_fpga_mgr_create` — Allocate and init a manager struct
|
||||
* :c:func:`fpga_mgr_register` — Register an FPGA manager
|
||||
* :c:func:`fpga_mgr_unregister` — Unregister an FPGA manager
|
||||
* devm_fpga_mgr_create() — Allocate and init a manager struct
|
||||
* fpga_mgr_register() — Register an FPGA manager
|
||||
* fpga_mgr_unregister() — Unregister an FPGA manager
|
||||
|
||||
.. kernel-doc:: include/linux/fpga/fpga-mgr.h
|
||||
:functions: fpga_mgr_states
|
||||
|
|
|
|||
|
|
@ -6,9 +6,9 @@ Overview
|
|||
|
||||
The in-kernel API for FPGA programming is a combination of APIs from
|
||||
FPGA manager, bridge, and regions. The actual function used to
|
||||
trigger FPGA programming is :c:func:`fpga_region_program_fpga()`.
|
||||
trigger FPGA programming is fpga_region_program_fpga().
|
||||
|
||||
:c:func:`fpga_region_program_fpga()` uses functionality supplied by
|
||||
fpga_region_program_fpga() uses functionality supplied by
|
||||
the FPGA manager and bridges. It will:
|
||||
|
||||
* lock the region's mutex
|
||||
|
|
@ -20,8 +20,8 @@ the FPGA manager and bridges. It will:
|
|||
* release the locks
|
||||
|
||||
The struct fpga_image_info specifies what FPGA image to program. It is
|
||||
allocated/freed by :c:func:`fpga_image_info_alloc()` and freed with
|
||||
:c:func:`fpga_image_info_free()`
|
||||
allocated/freed by fpga_image_info_alloc() and freed with
|
||||
fpga_image_info_free()
|
||||
|
||||
How to program an FPGA using a region
|
||||
-------------------------------------
|
||||
|
|
@ -84,10 +84,10 @@ will generate that list. Here's some sample code of what to do next::
|
|||
API for programming an FPGA
|
||||
---------------------------
|
||||
|
||||
* :c:func:`fpga_region_program_fpga` — Program an FPGA
|
||||
* :c:type:`fpga_image_info` — Specifies what FPGA image to program
|
||||
* :c:func:`fpga_image_info_alloc()` — Allocate an FPGA image info struct
|
||||
* :c:func:`fpga_image_info_free()` — Free an FPGA image info struct
|
||||
* fpga_region_program_fpga() — Program an FPGA
|
||||
* fpga_image_info() — Specifies what FPGA image to program
|
||||
* fpga_image_info_alloc() — Allocate an FPGA image info struct
|
||||
* fpga_image_info_free() — Free an FPGA image info struct
|
||||
|
||||
.. kernel-doc:: drivers/fpga/fpga-region.c
|
||||
:functions: fpga_region_program_fpga
|
||||
|
|
|
|||
|
|
@ -46,18 +46,18 @@ API to add a new FPGA region
|
|||
----------------------------
|
||||
|
||||
* struct :c:type:`fpga_region` — The FPGA region struct
|
||||
* :c:func:`devm_fpga_region_create` — Allocate and init a region struct
|
||||
* :c:func:`fpga_region_register` — Register an FPGA region
|
||||
* :c:func:`fpga_region_unregister` — Unregister an FPGA region
|
||||
* devm_fpga_region_create() — Allocate and init a region struct
|
||||
* fpga_region_register() — Register an FPGA region
|
||||
* fpga_region_unregister() — Unregister an FPGA region
|
||||
|
||||
The FPGA region's probe function will need to get a reference to the FPGA
|
||||
Manager it will be using to do the programming. This usually would happen
|
||||
during the region's probe function.
|
||||
|
||||
* :c:func:`fpga_mgr_get` — Get a reference to an FPGA manager, raise ref count
|
||||
* :c:func:`of_fpga_mgr_get` — Get a reference to an FPGA manager, raise ref count,
|
||||
* fpga_mgr_get() — Get a reference to an FPGA manager, raise ref count
|
||||
* of_fpga_mgr_get() — Get a reference to an FPGA manager, raise ref count,
|
||||
given a device node.
|
||||
* :c:func:`fpga_mgr_put` — Put an FPGA manager
|
||||
* fpga_mgr_put() — Put an FPGA manager
|
||||
|
||||
The FPGA region will need to specify which bridges to control while programming
|
||||
the FPGA. The region driver can build a list of bridges during probe time
|
||||
|
|
@ -66,11 +66,11 @@ the list of bridges to program just before programming
|
|||
(:c:member:`fpga_region->get_bridges`). The FPGA bridge framework supplies the
|
||||
following APIs to handle building or tearing down that list.
|
||||
|
||||
* :c:func:`fpga_bridge_get_to_list` — Get a ref of an FPGA bridge, add it to a
|
||||
* fpga_bridge_get_to_list() — Get a ref of an FPGA bridge, add it to a
|
||||
list
|
||||
* :c:func:`of_fpga_bridge_get_to_list` — Get a ref of an FPGA bridge, add it to a
|
||||
* of_fpga_bridge_get_to_list() — Get a ref of an FPGA bridge, add it to a
|
||||
list, given a device node
|
||||
* :c:func:`fpga_bridges_put` — Given a list of bridges, put them
|
||||
* fpga_bridges_put() — Given a list of bridges, put them
|
||||
|
||||
.. kernel-doc:: include/linux/fpga/fpga-region.h
|
||||
:functions: fpga_region
|
||||
|
|
|
|||
|
|
@ -11,10 +11,10 @@ Industrial I/O Devices
|
|||
----------------------
|
||||
|
||||
* struct :c:type:`iio_dev` - industrial I/O device
|
||||
* :c:func:`iio_device_alloc()` - allocate an :c:type:`iio_dev` from a driver
|
||||
* :c:func:`iio_device_free()` - free an :c:type:`iio_dev` from a driver
|
||||
* :c:func:`iio_device_register()` - register a device with the IIO subsystem
|
||||
* :c:func:`iio_device_unregister()` - unregister a device from the IIO
|
||||
* iio_device_alloc() - allocate an :c:type:`iio_dev` from a driver
|
||||
* iio_device_free() - free an :c:type:`iio_dev` from a driver
|
||||
* iio_device_register() - register a device with the IIO subsystem
|
||||
* iio_device_unregister() - unregister a device from the IIO
|
||||
subsystem
|
||||
|
||||
An IIO device usually corresponds to a single hardware sensor and it
|
||||
|
|
@ -34,17 +34,17 @@ A typical IIO driver will register itself as an :doc:`I2C <../i2c>` or
|
|||
|
||||
At probe:
|
||||
|
||||
1. Call :c:func:`iio_device_alloc()`, which allocates memory for an IIO device.
|
||||
1. Call iio_device_alloc(), which allocates memory for an IIO device.
|
||||
2. Initialize IIO device fields with driver specific information (e.g.
|
||||
device name, device channels).
|
||||
3. Call :c:func:`iio_device_register()`, this registers the device with the
|
||||
3. Call iio_device_register(), this registers the device with the
|
||||
IIO core. After this call the device is ready to accept requests from user
|
||||
space applications.
|
||||
|
||||
At remove, we free the resources allocated in probe in reverse order:
|
||||
|
||||
1. :c:func:`iio_device_unregister()`, unregister the device from the IIO core.
|
||||
2. :c:func:`iio_device_free()`, free the memory allocated for the IIO device.
|
||||
1. iio_device_unregister(), unregister the device from the IIO core.
|
||||
2. iio_device_free(), free the memory allocated for the IIO device.
|
||||
|
||||
IIO device sysfs interface
|
||||
==========================
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ NVMe Fault Injection
|
|||
Linux's fault injection framework provides a systematic way to support
|
||||
error injection via debugfs in the /sys/kernel/debug directory. When
|
||||
enabled, the default NVME_SC_INVALID_OPCODE with no retry will be
|
||||
injected into the nvme_end_request. Users can change the default status
|
||||
injected into the nvme_try_complete_req. Users can change the default status
|
||||
code and no retry flag via the debugfs. The list of Generic Command
|
||||
Status can be found in include/linux/nvme.h
|
||||
|
||||
|
|
|
|||
|
|
@ -110,13 +110,15 @@ The Amiga protection flags RWEDRWEDHSPARWED are handled as follows:
|
|||
|
||||
- R maps to r for user, group and others. On directories, R implies x.
|
||||
|
||||
- If both W and D are allowed, w will be set.
|
||||
- W maps to w.
|
||||
|
||||
- E maps to x.
|
||||
|
||||
- H and P are always retained and ignored under Linux.
|
||||
- D is ignored.
|
||||
|
||||
- A is always reset when a file is written to.
|
||||
- H, S and P are always retained and ignored under Linux.
|
||||
|
||||
- A is cleared when a file is written to.
|
||||
|
||||
User id and group id will be used unless set[gu]id are given as mount
|
||||
options. Since most of the Amiga file systems are single user systems
|
||||
|
|
@ -128,11 +130,13 @@ Linux -> Amiga:
|
|||
|
||||
The Linux rwxrwxrwx file mode is handled as follows:
|
||||
|
||||
- r permission will set R for user, group and others.
|
||||
- r permission will allow R for user, group and others.
|
||||
|
||||
- w permission will set W and D for user, group and others.
|
||||
- w permission will allow W for user, group and others.
|
||||
|
||||
- x permission of the user will set E for plain files.
|
||||
- x permission of the user will allow E for plain files.
|
||||
|
||||
- D will be allowed for user, group and others.
|
||||
|
||||
- All other flags (suid, sgid, ...) are ignored and will
|
||||
not be retained.
|
||||
|
|
|
|||
|
|
@ -68,7 +68,7 @@ See below for all known bank addresses, numbers of sensors in that bank,
|
|||
number of bytes data per sensor and contents/meaning of those bytes.
|
||||
|
||||
Although both this document and the kernel driver have kept the sensor
|
||||
terminoligy for the addressing within a bank this is not 100% correct, in
|
||||
terminology for the addressing within a bank this is not 100% correct, in
|
||||
bank 0x24 for example the addressing within the bank selects a PWM output not
|
||||
a sensor.
|
||||
|
||||
|
|
@ -155,7 +155,7 @@ After wider testing of the Linux kernel driver some variants of the uGuru have
|
|||
turned up which do not hold 0x08 at DATA within 250 reads after writing the
|
||||
bank address. With these versions this happens quite frequent, using larger
|
||||
timeouts doesn't help, they just go offline for a second or 2, doing some
|
||||
internal callibration or whatever. Your code should be prepared to handle
|
||||
internal calibration or whatever. Your code should be prepared to handle
|
||||
this and in case of no response in this specific case just goto sleep for a
|
||||
while and then retry.
|
||||
|
||||
|
|
@ -331,6 +331,6 @@ the voltage / clock programming out, I tried reading and only reading banks
|
|||
0-0x30 with the reading code used for the sensor banks (0x20-0x28) and this
|
||||
resulted in a _permanent_ reprogramming of the voltages, luckily I had the
|
||||
sensors part configured so that it would shutdown my system on any out of spec
|
||||
voltages which proprably safed my computer (after a reboot I managed to
|
||||
voltages which probably safed my computer (after a reboot I managed to
|
||||
immediately enter the bios and reload the defaults). This probably means that
|
||||
the read/write cycle for the non sensor part is different from the sensor part.
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ Supported chips:
|
|||
Note:
|
||||
The uGuru is a microcontroller with onboard firmware which programs
|
||||
it to behave as a hwmon IC. There are many different revisions of the
|
||||
firmware and thus effectivly many different revisions of the uGuru.
|
||||
firmware and thus effectively many different revisions of the uGuru.
|
||||
Below is an incomplete list with which revisions are used for which
|
||||
Motherboards:
|
||||
|
||||
|
|
@ -33,7 +33,7 @@ Supported chips:
|
|||
sensortype (Volt or Temp) for bank1 sensors, for revision 1 uGuru's
|
||||
this does not always work. For these uGuru's the autodetection can
|
||||
be overridden with the bank1_types module param. For all 3 known
|
||||
revison 1 motherboards the correct use of this param is:
|
||||
revision 1 motherboards the correct use of this param is:
|
||||
bank1_types=1,1,0,0,0,0,0,2,0,0,0,0,2,0,0,1
|
||||
You may also need to specify the fan_sensors option for these boards
|
||||
fan_sensors=5
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ Supported chips:
|
|||
Note:
|
||||
The uGuru is a microcontroller with onboard firmware which programs
|
||||
it to behave as a hwmon IC. There are many different revisions of the
|
||||
firmware and thus effectivly many different revisions of the uGuru.
|
||||
firmware and thus effectively many different revisions of the uGuru.
|
||||
Below is an incomplete list with which revisions are used for which
|
||||
Motherboards:
|
||||
|
||||
|
|
@ -24,7 +24,7 @@ Supported chips:
|
|||
- uGuru 3.0.0.0 ~ 3.0.x.x (AW8, AL8, AT8, NI8 SLI, AT8 32X, AN8 32X,
|
||||
AW9D-MAX)
|
||||
|
||||
The abituguru3 driver is only for revison 3.0.x.x motherboards,
|
||||
The abituguru3 driver is only for revision 3.0.x.x motherboards,
|
||||
this driver will not work on older motherboards. For older
|
||||
motherboards use the abituguru (without the 3 !) driver.
|
||||
|
||||
|
|
|
|||
|
|
@ -23,8 +23,8 @@ supports C and the GNU C extensions required by the kernel, and is pronounced
|
|||
Clang
|
||||
-----
|
||||
|
||||
The compiler used can be swapped out via `CC=` command line argument to `make`.
|
||||
`CC=` should be set when selecting a config and during a build.
|
||||
The compiler used can be swapped out via ``CC=`` command line argument to ``make``.
|
||||
``CC=`` should be set when selecting a config and during a build. ::
|
||||
|
||||
make CC=clang defconfig
|
||||
|
||||
|
|
@ -34,33 +34,33 @@ Cross Compiling
|
|||
---------------
|
||||
|
||||
A single Clang compiler binary will typically contain all supported backends,
|
||||
which can help simplify cross compiling.
|
||||
which can help simplify cross compiling. ::
|
||||
|
||||
ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- make CC=clang
|
||||
|
||||
`CROSS_COMPILE` is not used to prefix the Clang compiler binary, instead
|
||||
`CROSS_COMPILE` is used to set a command line flag: `--target <triple>`. For
|
||||
example:
|
||||
``CROSS_COMPILE`` is not used to prefix the Clang compiler binary, instead
|
||||
``CROSS_COMPILE`` is used to set a command line flag: ``--target <triple>``. For
|
||||
example: ::
|
||||
|
||||
clang --target aarch64-linux-gnu foo.c
|
||||
|
||||
LLVM Utilities
|
||||
--------------
|
||||
|
||||
LLVM has substitutes for GNU binutils utilities. Kbuild supports `LLVM=1`
|
||||
to enable them.
|
||||
LLVM has substitutes for GNU binutils utilities. Kbuild supports ``LLVM=1``
|
||||
to enable them. ::
|
||||
|
||||
make LLVM=1
|
||||
|
||||
They can be enabled individually. The full list of the parameters:
|
||||
They can be enabled individually. The full list of the parameters: ::
|
||||
|
||||
make CC=clang LD=ld.lld AR=llvm-ar NM=llvm-nm STRIP=llvm-strip \\
|
||||
OBJCOPY=llvm-objcopy OBJDUMP=llvm-objdump OBJSIZE=llvm-size \\
|
||||
READELF=llvm-readelf HOSTCC=clang HOSTCXX=clang++ HOSTAR=llvm-ar \\
|
||||
make CC=clang LD=ld.lld AR=llvm-ar NM=llvm-nm STRIP=llvm-strip \
|
||||
OBJCOPY=llvm-objcopy OBJDUMP=llvm-objdump OBJSIZE=llvm-size \
|
||||
READELF=llvm-readelf HOSTCC=clang HOSTCXX=clang++ HOSTAR=llvm-ar \
|
||||
HOSTLD=ld.lld
|
||||
|
||||
Currently, the integrated assembler is disabled by default. You can pass
|
||||
`LLVM_IAS=1` to enable it.
|
||||
``LLVM_IAS=1`` to enable it.
|
||||
|
||||
Getting Help
|
||||
------------
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ This document describes the Linux kernel Makefiles.
|
|||
--- 3.5 Library file goals - lib-y
|
||||
--- 3.6 Descending down in directories
|
||||
--- 3.7 Compilation flags
|
||||
--- 3.8 Command line dependency
|
||||
--- 3.8 <deleted>
|
||||
--- 3.9 Dependency tracking
|
||||
--- 3.10 Special Rules
|
||||
--- 3.11 $(CC) support functions
|
||||
|
|
@ -39,8 +39,8 @@ This document describes the Linux kernel Makefiles.
|
|||
|
||||
=== 7 Architecture Makefiles
|
||||
--- 7.1 Set variables to tweak the build to the architecture
|
||||
--- 7.2 Add prerequisites to archheaders:
|
||||
--- 7.3 Add prerequisites to archprepare:
|
||||
--- 7.2 Add prerequisites to archheaders
|
||||
--- 7.3 Add prerequisites to archprepare
|
||||
--- 7.4 List directories to visit when descending
|
||||
--- 7.5 Architecture-specific boot images
|
||||
--- 7.6 Building non-kbuild targets
|
||||
|
|
@ -129,7 +129,7 @@ The preferred name for the kbuild files are 'Makefile' but 'Kbuild' can
|
|||
be used and if both a 'Makefile' and a 'Kbuild' file exists, then the 'Kbuild'
|
||||
file will be used.
|
||||
|
||||
Section 3.1 "Goal definitions" is a quick intro, further chapters provide
|
||||
Section 3.1 "Goal definitions" is a quick intro; further chapters provide
|
||||
more details, with real examples.
|
||||
|
||||
3.1 Goal definitions
|
||||
|
|
@ -965,7 +965,7 @@ When kbuild executes, the following steps are followed (roughly):
|
|||
KBUILD_LDFLAGS := -m elf_s390
|
||||
|
||||
Note: ldflags-y can be used to further customise
|
||||
the flags used. See chapter 3.7.
|
||||
the flags used. See section 3.7.
|
||||
|
||||
LDFLAGS_vmlinux
|
||||
Options for $(LD) when linking vmlinux
|
||||
|
|
@ -1121,7 +1121,7 @@ When kbuild executes, the following steps are followed (roughly):
|
|||
|
||||
In this example, the file target maketools will be processed
|
||||
before descending down in the subdirectories.
|
||||
See also chapter XXX-TODO that describe how kbuild supports
|
||||
See also chapter XXX-TODO that describes how kbuild supports
|
||||
generating offset header files.
|
||||
|
||||
|
||||
|
|
@ -1261,7 +1261,7 @@ When kbuild executes, the following steps are followed (roughly):
|
|||
always be built.
|
||||
Assignments to $(targets) are without $(obj)/ prefix.
|
||||
if_changed may be used in conjunction with custom commands as
|
||||
defined in 6.8 "Custom kbuild commands".
|
||||
defined in 7.8 "Custom kbuild commands".
|
||||
|
||||
Note: It is a typical mistake to forget the FORCE prerequisite.
|
||||
Another common pitfall is that whitespace is sometimes
|
||||
|
|
@ -1411,7 +1411,7 @@ When kbuild executes, the following steps are followed (roughly):
|
|||
that may be shared between individual architectures.
|
||||
The recommended approach how to use a generic header file is
|
||||
to list the file in the Kbuild file.
|
||||
See "7.2 generic-y" for further info on syntax etc.
|
||||
See "8.2 generic-y" for further info on syntax etc.
|
||||
|
||||
7.11 Post-link pass
|
||||
-------------------
|
||||
|
|
@ -1601,4 +1601,4 @@ is the right choice.
|
|||
|
||||
- Describe how kbuild supports shipped files with _shipped.
|
||||
- Generating offset header files.
|
||||
- Add more variables to section 7?
|
||||
- Add more variables to chapters 7 or 9?
|
||||
|
|
|
|||
|
|
@ -164,14 +164,14 @@ by disabling preemption or interrupts.
|
|||
On non-PREEMPT_RT kernels local_lock operations map to the preemption and
|
||||
interrupt disabling and enabling primitives:
|
||||
|
||||
=========================== ======================
|
||||
local_lock(&llock) preempt_disable()
|
||||
local_unlock(&llock) preempt_enable()
|
||||
local_lock_irq(&llock) local_irq_disable()
|
||||
local_unlock_irq(&llock) local_irq_enable()
|
||||
local_lock_save(&llock) local_irq_save()
|
||||
local_lock_restore(&llock) local_irq_save()
|
||||
=========================== ======================
|
||||
=============================== ======================
|
||||
local_lock(&llock) preempt_disable()
|
||||
local_unlock(&llock) preempt_enable()
|
||||
local_lock_irq(&llock) local_irq_disable()
|
||||
local_unlock_irq(&llock) local_irq_enable()
|
||||
local_lock_irqsave(&llock) local_irq_save()
|
||||
local_unlock_irqrestore(&llock) local_irq_restore()
|
||||
=============================== ======================
|
||||
|
||||
The named scope of local_lock has two advantages over the regular
|
||||
primitives:
|
||||
|
|
@ -353,14 +353,14 @@ protection scope. So the following substitution is wrong::
|
|||
{
|
||||
local_irq_save(flags); -> local_lock_irqsave(&local_lock_1, flags);
|
||||
func3();
|
||||
local_irq_restore(flags); -> local_lock_irqrestore(&local_lock_1, flags);
|
||||
local_irq_restore(flags); -> local_unlock_irqrestore(&local_lock_1, flags);
|
||||
}
|
||||
|
||||
func2()
|
||||
{
|
||||
local_irq_save(flags); -> local_lock_irqsave(&local_lock_2, flags);
|
||||
func3();
|
||||
local_irq_restore(flags); -> local_lock_irqrestore(&local_lock_2, flags);
|
||||
local_irq_restore(flags); -> local_unlock_irqrestore(&local_lock_2, flags);
|
||||
}
|
||||
|
||||
func3()
|
||||
|
|
@ -379,14 +379,14 @@ PREEMPT_RT-specific semantics of spinlock_t. The correct substitution is::
|
|||
{
|
||||
local_irq_save(flags); -> local_lock_irqsave(&local_lock, flags);
|
||||
func3();
|
||||
local_irq_restore(flags); -> local_lock_irqrestore(&local_lock, flags);
|
||||
local_irq_restore(flags); -> local_unlock_irqrestore(&local_lock, flags);
|
||||
}
|
||||
|
||||
func2()
|
||||
{
|
||||
local_irq_save(flags); -> local_lock_irqsave(&local_lock, flags);
|
||||
func3();
|
||||
local_irq_restore(flags); -> local_lock_irqrestore(&local_lock, flags);
|
||||
local_irq_restore(flags); -> local_unlock_irqrestore(&local_lock, flags);
|
||||
}
|
||||
|
||||
func3()
|
||||
|
|
|
|||
|
|
@ -101,3 +101,4 @@ to do something different in the near future.
|
|||
|
||||
../doc-guide/maintainer-profile
|
||||
../nvdimm/maintainer-entry-profile
|
||||
../riscv/patch-acceptance
|
||||
|
|
|
|||
|
|
@ -180,7 +180,7 @@ The configuration can only be set up via VLAN tagging and bridge setup.
|
|||
|
||||
# bring up the slave interfaces
|
||||
ip link set lan1 up
|
||||
ip link set lan1 up
|
||||
ip link set lan2 up
|
||||
ip link set lan3 up
|
||||
|
||||
# create bridge
|
||||
|
|
|
|||
|
|
@ -49,16 +49,18 @@ Register preservation rules
|
|||
Register preservation rules match the ELF ABI calling sequence with the
|
||||
following differences:
|
||||
|
||||
=========== ============= ========================================
|
||||
--- For the sc instruction, differences with the ELF ABI ---
|
||||
=========== ============= ========================================
|
||||
r0 Volatile (System call number.)
|
||||
r3 Volatile (Parameter 1, and return value.)
|
||||
r4-r8 Volatile (Parameters 2-6.)
|
||||
cr0 Volatile (cr0.SO is the return error condition.)
|
||||
cr1, cr5-7 Nonvolatile
|
||||
lr Nonvolatile
|
||||
=========== ============= ========================================
|
||||
|
||||
--- For the scv 0 instruction, differences with the ELF ABI ---
|
||||
=========== ============= ========================================
|
||||
r0 Volatile (System call number.)
|
||||
r3 Volatile (Parameter 1, and return value.)
|
||||
r4-r8 Volatile (Parameters 2-6.)
|
||||
|
|
|
|||
|
|
@ -142,7 +142,7 @@ only NUL-terminated strings. The safe replacement is strscpy().
|
|||
(Users of strscpy() still needing NUL-padding should instead
|
||||
use strscpy_pad().)
|
||||
|
||||
If a caller is using non-NUL-terminated strings, strncpy()() can
|
||||
If a caller is using non-NUL-terminated strings, strncpy() can
|
||||
still be used, but destinations should be marked with the `__nonstring
|
||||
<https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html>`_
|
||||
attribute to avoid future compiler warnings.
|
||||
|
|
|
|||
|
|
@ -332,7 +332,7 @@ WO 9901953 (A1)
|
|||
|
||||
|
||||
US Patents (https://www.uspto.gov/)
|
||||
----------------------------------
|
||||
-----------------------------------
|
||||
|
||||
US 5925841
|
||||
Digital Sampling Instrument employing cache memory (Jul. 20, 1999)
|
||||
|
|
|
|||
|
|
@ -337,7 +337,7 @@ WO 9901953 (A1)
|
|||
|
||||
|
||||
US Patents (https://www.uspto.gov/)
|
||||
----------------------------------
|
||||
-----------------------------------
|
||||
|
||||
US 5925841
|
||||
Digital Sampling Instrument employing cache memory (Jul. 20, 1999)
|
||||
|
|
|
|||
|
|
@ -143,7 +143,7 @@ timestamp shows when the information is put together by the driver
|
|||
before returning from the ``STATUS`` and ``STATUS_EXT`` ioctl. in most cases
|
||||
this driver_timestamp will be identical to the regular system tstamp.
|
||||
|
||||
Examples of typestamping with HDaudio:
|
||||
Examples of timestamping with HDAudio:
|
||||
|
||||
1. DMA timestamp, no compensation for DMA+analog delay
|
||||
::
|
||||
|
|
|
|||
|
|
@ -130,7 +130,7 @@ chi usa solo stringe terminate. La versione sicura da usare è
|
|||
strscpy(). (chi usa strscpy() e necessita di estendere la
|
||||
terminazione con NUL deve aggiungere una chiamata a memset())
|
||||
|
||||
Se il chiamate no usa stringhe terminate con NUL, allore strncpy()()
|
||||
Se il chiamate no usa stringhe terminate con NUL, allore strncpy()
|
||||
può continuare ad essere usata, ma i buffer di destinazione devono essere
|
||||
marchiati con l'attributo `__nonstring <https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html>`_
|
||||
per evitare avvisi durante la compilazione.
|
||||
|
|
|
|||
|
|
@ -6130,7 +6130,7 @@ HvCallSendSyntheticClusterIpi, HvCallSendSyntheticClusterIpiEx.
|
|||
8.21 KVM_CAP_HYPERV_DIRECT_TLBFLUSH
|
||||
-----------------------------------
|
||||
|
||||
:Architecture: x86
|
||||
:Architectures: x86
|
||||
|
||||
This capability indicates that KVM running on top of Hyper-V hypervisor
|
||||
enables Direct TLB flush for its guests meaning that TLB flush
|
||||
|
|
@ -6143,19 +6143,33 @@ in CPUID and only exposes Hyper-V identification. In this case, guest
|
|||
thinks it's running on Hyper-V and only use Hyper-V hypercalls.
|
||||
|
||||
8.22 KVM_CAP_S390_VCPU_RESETS
|
||||
-----------------------------
|
||||
|
||||
Architectures: s390
|
||||
:Architectures: s390
|
||||
|
||||
This capability indicates that the KVM_S390_NORMAL_RESET and
|
||||
KVM_S390_CLEAR_RESET ioctls are available.
|
||||
|
||||
8.23 KVM_CAP_S390_PROTECTED
|
||||
---------------------------
|
||||
|
||||
Architecture: s390
|
||||
|
||||
:Architectures: s390
|
||||
|
||||
This capability indicates that the Ultravisor has been initialized and
|
||||
KVM can therefore start protected VMs.
|
||||
This capability governs the KVM_S390_PV_COMMAND ioctl and the
|
||||
KVM_MP_STATE_LOAD MP_STATE. KVM_SET_MP_STATE can fail for protected
|
||||
guests when the state change is invalid.
|
||||
|
||||
8.24 KVM_CAP_STEAL_TIME
|
||||
-----------------------
|
||||
|
||||
:Architectures: arm64, x86
|
||||
|
||||
This capability indicates that KVM supports steal time accounting.
|
||||
When steal time accounting is supported it may be enabled with
|
||||
architecture-specific interfaces. This capability and the architecture-
|
||||
specific interfaces must be consistent, i.e. if one says the feature
|
||||
is supported, than the other should as well and vice versa. For arm64
|
||||
see Documentation/virt/kvm/devices/vcpu.rst "KVM_ARM_VCPU_PVTIME_CTRL".
|
||||
For x86 see Documentation/virt/kvm/msr.rst "MSR_KVM_STEAL_TIME".
|
||||
|
|
|
|||
85
MAINTAINERS
85
MAINTAINERS
|
|
@ -1694,7 +1694,6 @@ F: arch/arm/mach-cns3xxx/
|
|||
|
||||
ARM/CAVIUM THUNDER NETWORK DRIVER
|
||||
M: Sunil Goutham <sgoutham@marvell.com>
|
||||
M: Robert Richter <rrichter@marvell.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Supported
|
||||
F: drivers/net/ethernet/cavium/thunder/
|
||||
|
|
@ -3205,6 +3204,7 @@ S: Maintained
|
|||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git
|
||||
F: block/
|
||||
F: drivers/block/
|
||||
F: include/linux/blk*
|
||||
F: kernel/trace/blktrace.c
|
||||
F: lib/sbitmap.c
|
||||
|
||||
|
|
@ -3388,6 +3388,7 @@ M: Florian Fainelli <f.fainelli@gmail.com>
|
|||
L: netdev@vger.kernel.org
|
||||
L: openwrt-devel@lists.openwrt.org (subscribers-only)
|
||||
S: Supported
|
||||
F: Documentation/devicetree/bindings/net/dsa/b53.txt
|
||||
F: drivers/net/dsa/b53/*
|
||||
F: include/linux/platform_data/b53.h
|
||||
|
||||
|
|
@ -3573,13 +3574,28 @@ L: bcm-kernel-feedback-list@broadcom.com
|
|||
S: Maintained
|
||||
F: drivers/phy/broadcom/phy-brcm-usb*
|
||||
|
||||
BROADCOM ETHERNET PHY DRIVERS
|
||||
M: Florian Fainelli <f.fainelli@gmail.com>
|
||||
L: bcm-kernel-feedback-list@broadcom.com
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
F: Documentation/devicetree/bindings/net/broadcom-bcm87xx.txt
|
||||
F: drivers/net/phy/bcm*.[ch]
|
||||
F: drivers/net/phy/broadcom.c
|
||||
F: include/linux/brcmphy.h
|
||||
|
||||
BROADCOM GENET ETHERNET DRIVER
|
||||
M: Doug Berger <opendmb@gmail.com>
|
||||
M: Florian Fainelli <f.fainelli@gmail.com>
|
||||
L: bcm-kernel-feedback-list@broadcom.com
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
F: Documentation/devicetree/bindings/net/brcm,bcmgenet.txt
|
||||
F: Documentation/devicetree/bindings/net/brcm,unimac-mdio.txt
|
||||
F: drivers/net/ethernet/broadcom/genet/
|
||||
F: drivers/net/mdio/mdio-bcm-unimac.c
|
||||
F: include/linux/platform_data/bcmgenet.h
|
||||
F: include/linux/platform_data/mdio-bcm-unimac.h
|
||||
|
||||
BROADCOM IPROC ARM ARCHITECTURE
|
||||
M: Ray Jui <rjui@broadcom.com>
|
||||
|
|
@ -3931,8 +3947,8 @@ W: https://wireless.wiki.kernel.org/en/users/Drivers/carl9170
|
|||
F: drivers/net/wireless/ath/carl9170/
|
||||
|
||||
CAVIUM I2C DRIVER
|
||||
M: Robert Richter <rrichter@marvell.com>
|
||||
S: Supported
|
||||
M: Robert Richter <rric@kernel.org>
|
||||
S: Odd Fixes
|
||||
W: http://www.marvell.com
|
||||
F: drivers/i2c/busses/i2c-octeon*
|
||||
F: drivers/i2c/busses/i2c-thunderx*
|
||||
|
|
@ -3947,8 +3963,8 @@ W: http://www.marvell.com
|
|||
F: drivers/net/ethernet/cavium/liquidio/
|
||||
|
||||
CAVIUM MMC DRIVER
|
||||
M: Robert Richter <rrichter@marvell.com>
|
||||
S: Supported
|
||||
M: Robert Richter <rric@kernel.org>
|
||||
S: Odd Fixes
|
||||
W: http://www.marvell.com
|
||||
F: drivers/mmc/host/cavium*
|
||||
|
||||
|
|
@ -3960,9 +3976,9 @@ W: http://www.marvell.com
|
|||
F: drivers/crypto/cavium/cpt/
|
||||
|
||||
CAVIUM THUNDERX2 ARM64 SOC
|
||||
M: Robert Richter <rrichter@marvell.com>
|
||||
M: Robert Richter <rric@kernel.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
S: Odd Fixes
|
||||
F: Documentation/devicetree/bindings/arm/cavium-thunder2.txt
|
||||
F: arch/arm64/boot/dts/cavium/thunder2-99xx*
|
||||
|
||||
|
|
@ -4241,6 +4257,8 @@ S: Maintained
|
|||
F: .clang-format
|
||||
|
||||
CLANG/LLVM BUILD SUPPORT
|
||||
M: Nathan Chancellor <natechancellor@gmail.com>
|
||||
M: Nick Desaulniers <ndesaulniers@google.com>
|
||||
L: clang-built-linux@googlegroups.com
|
||||
S: Supported
|
||||
W: https://clangbuiltlinux.github.io/
|
||||
|
|
@ -5245,6 +5263,7 @@ DOCUMENTATION
|
|||
M: Jonathan Corbet <corbet@lwn.net>
|
||||
L: linux-doc@vger.kernel.org
|
||||
S: Maintained
|
||||
P: Documentation/doc-guide/maintainer-profile.rst
|
||||
T: git git://git.lwn.net/linux.git docs-next
|
||||
F: Documentation/
|
||||
F: scripts/documentation-file-ref-check
|
||||
|
|
@ -6179,16 +6198,15 @@ F: drivers/edac/highbank*
|
|||
|
||||
EDAC-CAVIUM OCTEON
|
||||
M: Ralf Baechle <ralf@linux-mips.org>
|
||||
M: Robert Richter <rrichter@marvell.com>
|
||||
L: linux-edac@vger.kernel.org
|
||||
L: linux-mips@vger.kernel.org
|
||||
S: Supported
|
||||
F: drivers/edac/octeon_edac*
|
||||
|
||||
EDAC-CAVIUM THUNDERX
|
||||
M: Robert Richter <rrichter@marvell.com>
|
||||
M: Robert Richter <rric@kernel.org>
|
||||
L: linux-edac@vger.kernel.org
|
||||
S: Supported
|
||||
S: Odd Fixes
|
||||
F: drivers/edac/thunderx_edac*
|
||||
|
||||
EDAC-CORE
|
||||
|
|
@ -6196,7 +6214,7 @@ M: Borislav Petkov <bp@alien8.de>
|
|||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
M: Tony Luck <tony.luck@intel.com>
|
||||
R: James Morse <james.morse@arm.com>
|
||||
R: Robert Richter <rrichter@marvell.com>
|
||||
R: Robert Richter <rric@kernel.org>
|
||||
L: linux-edac@vger.kernel.org
|
||||
S: Supported
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras.git edac-for-next
|
||||
|
|
@ -6500,7 +6518,6 @@ F: net/bridge/
|
|||
|
||||
ETHERNET PHY LIBRARY
|
||||
M: Andrew Lunn <andrew@lunn.ch>
|
||||
M: Florian Fainelli <f.fainelli@gmail.com>
|
||||
M: Heiner Kallweit <hkallweit1@gmail.com>
|
||||
R: Russell King <linux@armlinux.org.uk>
|
||||
L: netdev@vger.kernel.org
|
||||
|
|
@ -6890,6 +6907,14 @@ L: linuxppc-dev@lists.ozlabs.org
|
|||
S: Maintained
|
||||
F: drivers/dma/fsldma.*
|
||||
|
||||
FREESCALE DSPI DRIVER
|
||||
M: Vladimir Oltean <olteanv@gmail.com>
|
||||
L: linux-spi@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
|
||||
F: drivers/spi/spi-fsl-dspi.c
|
||||
F: include/linux/spi/spi-fsl-dspi.h
|
||||
|
||||
FREESCALE ENETC ETHERNET DRIVERS
|
||||
M: Claudiu Manoil <claudiu.manoil@nxp.com>
|
||||
L: netdev@vger.kernel.org
|
||||
|
|
@ -8261,7 +8286,7 @@ IA64 (Itanium) PLATFORM
|
|||
M: Tony Luck <tony.luck@intel.com>
|
||||
M: Fenghua Yu <fenghua.yu@intel.com>
|
||||
L: linux-ia64@vger.kernel.org
|
||||
S: Maintained
|
||||
S: Odd Fixes
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux.git
|
||||
F: Documentation/ia64/
|
||||
F: arch/ia64/
|
||||
|
|
@ -9781,7 +9806,7 @@ F: drivers/scsi/53c700*
|
|||
|
||||
LEAKING_ADDRESSES
|
||||
M: Tobin C. Harding <me@tobin.cc>
|
||||
M: Tycho Andersen <tycho@tycho.ws>
|
||||
M: Tycho Andersen <tycho@tycho.pizza>
|
||||
L: kernel-hardening@lists.openwall.com
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tobin/leaks.git
|
||||
|
|
@ -13435,10 +13460,10 @@ F: Documentation/devicetree/bindings/pci/axis,artpec*
|
|||
F: drivers/pci/controller/dwc/*artpec*
|
||||
|
||||
PCIE DRIVER FOR CAVIUM THUNDERX
|
||||
M: Robert Richter <rrichter@marvell.com>
|
||||
M: Robert Richter <rric@kernel.org>
|
||||
L: linux-pci@vger.kernel.org
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Supported
|
||||
S: Odd Fixes
|
||||
F: drivers/pci/controller/pci-thunder-*
|
||||
|
||||
PCIE DRIVER FOR HISILICON
|
||||
|
|
@ -13575,12 +13600,18 @@ F: kernel/events/*
|
|||
F: tools/lib/perf/
|
||||
F: tools/perf/
|
||||
|
||||
PERFORMANCE EVENTS SUBSYSTEM ARM64 PMU EVENTS
|
||||
PERFORMANCE EVENTS TOOLING ARM64
|
||||
R: John Garry <john.garry@huawei.com>
|
||||
R: Will Deacon <will@kernel.org>
|
||||
R: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||||
R: Leo Yan <leo.yan@linaro.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Supported
|
||||
F: tools/build/feature/test-libopencsd.c
|
||||
F: tools/perf/arch/arm*/
|
||||
F: tools/perf/pmu-events/arch/arm64/
|
||||
F: tools/perf/util/arm-spe*
|
||||
F: tools/perf/util/cs-etm*
|
||||
|
||||
PERSONALITY HANDLING
|
||||
M: Christoph Hellwig <hch@infradead.org>
|
||||
|
|
@ -14371,7 +14402,7 @@ M: Rob Clark <robdclark@gmail.com>
|
|||
L: iommu@lists.linux-foundation.org
|
||||
L: linux-arm-msm@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/iommu/qcom_iommu.c
|
||||
F: drivers/iommu/arm/arm-smmu/qcom_iommu.c
|
||||
|
||||
QUALCOMM IPCC MAILBOX DRIVER
|
||||
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
|
@ -15552,6 +15583,7 @@ F: include/uapi/linux/sed*
|
|||
SECURITY CONTACT
|
||||
M: Security Officers <security@kernel.org>
|
||||
S: Supported
|
||||
F: Documentation/admin-guide/security-bugs.rst
|
||||
|
||||
SECURITY SUBSYSTEM
|
||||
M: James Morris <jmorris@namei.org>
|
||||
|
|
@ -17122,8 +17154,8 @@ S: Maintained
|
|||
F: Documentation/devicetree/bindings/arm/keystone/ti,k3-sci-common.yaml
|
||||
F: Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
|
||||
F: Documentation/devicetree/bindings/clock/ti,sci-clk.txt
|
||||
F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.txt
|
||||
F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt
|
||||
F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml
|
||||
F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
|
||||
F: Documentation/devicetree/bindings/reset/ti,sci-reset.txt
|
||||
F: Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
|
||||
F: drivers/clk/keystone/sci-clk.c
|
||||
|
|
@ -17220,8 +17252,8 @@ S: Maintained
|
|||
F: drivers/net/thunderbolt.c
|
||||
|
||||
THUNDERX GPIO DRIVER
|
||||
M: Robert Richter <rrichter@marvell.com>
|
||||
S: Maintained
|
||||
M: Robert Richter <rric@kernel.org>
|
||||
S: Odd Fixes
|
||||
F: drivers/gpio/gpio-thunderx.c
|
||||
|
||||
TI AM437X VPFE DRIVER
|
||||
|
|
@ -18880,6 +18912,15 @@ S: Maintained
|
|||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/core
|
||||
F: arch/x86/platform
|
||||
|
||||
X86 PLATFORM UV HPE SUPERDOME FLEX
|
||||
M: Steve Wahl <steve.wahl@hpe.com>
|
||||
R: Dimitri Sivanich <dimitri.sivanich@hpe.com>
|
||||
R: Russ Anderson <russ.anderson@hpe.com>
|
||||
S: Supported
|
||||
F: arch/x86/include/asm/uv/
|
||||
F: arch/x86/kernel/apic/x2apic_uv_x.c
|
||||
F: arch/x86/platform/uv/
|
||||
|
||||
X86 VDSO
|
||||
M: Andy Lutomirski <luto@kernel.org>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
|
|
|
|||
6
Makefile
6
Makefile
|
|
@ -2,7 +2,7 @@
|
|||
VERSION = 5
|
||||
PATCHLEVEL = 9
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc2
|
||||
EXTRAVERSION = -rc5
|
||||
NAME = Kleptomaniac Octopus
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
@ -882,10 +882,6 @@ KBUILD_CFLAGS_KERNEL += -ffunction-sections -fdata-sections
|
|||
LDFLAGS_vmlinux += --gc-sections
|
||||
endif
|
||||
|
||||
ifdef CONFIG_LIVEPATCH
|
||||
KBUILD_CFLAGS += $(call cc-option, -flive-patching=inline-clone)
|
||||
endif
|
||||
|
||||
ifdef CONFIG_SHADOW_CALL_STACK
|
||||
CC_FLAGS_SCS := -fsanitize=shadow-call-stack
|
||||
KBUILD_CFLAGS += $(CC_FLAGS_SCS)
|
||||
|
|
|
|||
|
|
@ -212,7 +212,7 @@ apply_relocate_add(Elf64_Shdr *sechdrs, const char *strtab,
|
|||
STO_ALPHA_STD_GPLOAD)
|
||||
/* Omit the prologue. */
|
||||
value += 8;
|
||||
/* FALLTHRU */
|
||||
fallthrough;
|
||||
case R_ALPHA_BRADDR:
|
||||
value -= (u64)location + 4;
|
||||
if (value & 3)
|
||||
|
|
|
|||
|
|
@ -453,7 +453,7 @@ syscall_restart(unsigned long r0, unsigned long r19,
|
|||
regs->r0 = EINTR;
|
||||
break;
|
||||
}
|
||||
/* fallthrough */
|
||||
fallthrough;
|
||||
case ERESTARTNOINTR:
|
||||
regs->r0 = r0; /* reset v0 and a3 and replay syscall */
|
||||
regs->r19 = r19;
|
||||
|
|
|
|||
|
|
@ -883,7 +883,7 @@ do_entUnaUser(void __user * va, unsigned long opcode,
|
|||
|
||||
case 0x26: /* sts */
|
||||
fake_reg = s_reg_to_mem(alpha_read_fp_reg(reg));
|
||||
/* FALLTHRU */
|
||||
fallthrough;
|
||||
|
||||
case 0x2c: /* stl */
|
||||
__asm__ __volatile__(
|
||||
|
|
@ -911,7 +911,7 @@ do_entUnaUser(void __user * va, unsigned long opcode,
|
|||
|
||||
case 0x27: /* stt */
|
||||
fake_reg = alpha_read_fp_reg(reg);
|
||||
/* FALLTHRU */
|
||||
fallthrough;
|
||||
|
||||
case 0x2d: /* stq */
|
||||
__asm__ __volatile__(
|
||||
|
|
|
|||
|
|
@ -88,6 +88,8 @@
|
|||
|
||||
arcpct: pct {
|
||||
compatible = "snps,archs-pct";
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <20>;
|
||||
};
|
||||
|
||||
/* TIMER0 with interrupt for clockevent */
|
||||
|
|
@ -208,7 +210,7 @@
|
|||
reg = <0x8000 0x2000>;
|
||||
interrupts = <10>;
|
||||
interrupt-names = "macirq";
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-id";
|
||||
snps,pbl = <32>;
|
||||
snps,multicast-filter-bins = <256>;
|
||||
clocks = <&gmacclk>;
|
||||
|
|
@ -226,7 +228,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
phy0: ethernet-phy@0 {
|
||||
phy0: ethernet-phy@0 { /* Micrel KSZ9031 */
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -18,10 +18,10 @@
|
|||
* vineetg: April 2010
|
||||
* -Switched pgtable_t from being struct page * to unsigned long
|
||||
* =Needed so that Page Table allocator (pte_alloc_one) is not forced to
|
||||
* to deal with struct page. Thay way in future we can make it allocate
|
||||
* deal with struct page. That way in future we can make it allocate
|
||||
* multiple PG Tbls in one Page Frame
|
||||
* =sweet side effect is avoiding calls to ugly page_address( ) from the
|
||||
* pg-tlb allocator sub-sys (pte_alloc_one, ptr_free, pmd_populate
|
||||
* pg-tlb allocator sub-sys (pte_alloc_one, ptr_free, pmd_populate)
|
||||
*
|
||||
* Amit Bhor, Sameer Dhavale: Codito Technologies 2004
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -339,7 +339,7 @@ void __kprobes disasm_instr(unsigned long addr, struct disasm_state *state,
|
|||
|
||||
case op_LDWX_S: /* LDWX_S c, [b, u6] */
|
||||
state->x = 1;
|
||||
/* intentional fall-through */
|
||||
fallthrough;
|
||||
|
||||
case op_LDW_S: /* LDW_S c, [b, u6] */
|
||||
state->zz = 2;
|
||||
|
|
|
|||
|
|
@ -562,7 +562,7 @@ static int arc_pmu_device_probe(struct platform_device *pdev)
|
|||
{
|
||||
struct arc_reg_pct_build pct_bcr;
|
||||
struct arc_reg_cc_build cc_bcr;
|
||||
int i, has_interrupts;
|
||||
int i, has_interrupts, irq;
|
||||
int counter_size; /* in bits */
|
||||
|
||||
union cc_name {
|
||||
|
|
@ -637,13 +637,7 @@ static int arc_pmu_device_probe(struct platform_device *pdev)
|
|||
.attr_groups = arc_pmu->attr_groups,
|
||||
};
|
||||
|
||||
if (has_interrupts) {
|
||||
int irq = platform_get_irq(pdev, 0);
|
||||
|
||||
if (irq < 0) {
|
||||
pr_err("Cannot get IRQ number for the platform\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
if (has_interrupts && (irq = platform_get_irq(pdev, 0) >= 0)) {
|
||||
|
||||
arc_pmu->irq = irq;
|
||||
|
||||
|
|
@ -652,9 +646,9 @@ static int arc_pmu_device_probe(struct platform_device *pdev)
|
|||
this_cpu_ptr(&arc_pmu_cpu));
|
||||
|
||||
on_each_cpu(arc_cpu_pmu_irq_init, &irq, 1);
|
||||
|
||||
} else
|
||||
} else {
|
||||
arc_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
|
||||
}
|
||||
|
||||
/*
|
||||
* perf parser doesn't really like '-' symbol in events name, so let's
|
||||
|
|
|
|||
|
|
@ -321,7 +321,7 @@ static void arc_restart_syscall(struct k_sigaction *ka, struct pt_regs *regs)
|
|||
regs->r0 = -EINTR;
|
||||
break;
|
||||
}
|
||||
/* fallthrough */
|
||||
fallthrough;
|
||||
|
||||
case -ERESTARTNOINTR:
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -18,44 +18,37 @@
|
|||
|
||||
#define ARC_PATH_MAX 256
|
||||
|
||||
/*
|
||||
* Common routine to print scratch regs (r0-r12) or callee regs (r13-r25)
|
||||
* -Prints 3 regs per line and a CR.
|
||||
* -To continue, callee regs right after scratch, special handling of CR
|
||||
*/
|
||||
static noinline void print_reg_file(long *reg_rev, int start_num)
|
||||
static noinline void print_regs_scratch(struct pt_regs *regs)
|
||||
{
|
||||
unsigned int i;
|
||||
char buf[512];
|
||||
int n = 0, len = sizeof(buf);
|
||||
pr_cont("BTA: 0x%08lx\n SP: 0x%08lx FP: 0x%08lx BLK: %pS\n",
|
||||
regs->bta, regs->sp, regs->fp, (void *)regs->blink);
|
||||
pr_cont("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n",
|
||||
regs->lp_start, regs->lp_end, regs->lp_count);
|
||||
|
||||
for (i = start_num; i < start_num + 13; i++) {
|
||||
n += scnprintf(buf + n, len - n, "r%02u: 0x%08lx\t",
|
||||
i, (unsigned long)*reg_rev);
|
||||
|
||||
if (((i + 1) % 3) == 0)
|
||||
n += scnprintf(buf + n, len - n, "\n");
|
||||
|
||||
/* because pt_regs has regs reversed: r12..r0, r25..r13 */
|
||||
if (is_isa_arcv2() && start_num == 0)
|
||||
reg_rev++;
|
||||
else
|
||||
reg_rev--;
|
||||
}
|
||||
|
||||
if (start_num != 0)
|
||||
n += scnprintf(buf + n, len - n, "\n\n");
|
||||
|
||||
/* To continue printing callee regs on same line as scratch regs */
|
||||
if (start_num == 0)
|
||||
pr_info("%s", buf);
|
||||
else
|
||||
pr_cont("%s\n", buf);
|
||||
pr_info("r00: 0x%08lx\tr01: 0x%08lx\tr02: 0x%08lx\n" \
|
||||
"r03: 0x%08lx\tr04: 0x%08lx\tr05: 0x%08lx\n" \
|
||||
"r06: 0x%08lx\tr07: 0x%08lx\tr08: 0x%08lx\n" \
|
||||
"r09: 0x%08lx\tr10: 0x%08lx\tr11: 0x%08lx\n" \
|
||||
"r12: 0x%08lx\t",
|
||||
regs->r0, regs->r1, regs->r2,
|
||||
regs->r3, regs->r4, regs->r5,
|
||||
regs->r6, regs->r7, regs->r8,
|
||||
regs->r9, regs->r10, regs->r11,
|
||||
regs->r12);
|
||||
}
|
||||
|
||||
static void show_callee_regs(struct callee_regs *cregs)
|
||||
static void print_regs_callee(struct callee_regs *regs)
|
||||
{
|
||||
print_reg_file(&(cregs->r13), 13);
|
||||
pr_cont("r13: 0x%08lx\tr14: 0x%08lx\n" \
|
||||
"r15: 0x%08lx\tr16: 0x%08lx\tr17: 0x%08lx\n" \
|
||||
"r18: 0x%08lx\tr19: 0x%08lx\tr20: 0x%08lx\n" \
|
||||
"r21: 0x%08lx\tr22: 0x%08lx\tr23: 0x%08lx\n" \
|
||||
"r24: 0x%08lx\tr25: 0x%08lx\n",
|
||||
regs->r13, regs->r14,
|
||||
regs->r15, regs->r16, regs->r17,
|
||||
regs->r18, regs->r19, regs->r20,
|
||||
regs->r21, regs->r22, regs->r23,
|
||||
regs->r24, regs->r25);
|
||||
}
|
||||
|
||||
static void print_task_path_n_nm(struct task_struct *tsk)
|
||||
|
|
@ -175,7 +168,7 @@ static void show_ecr_verbose(struct pt_regs *regs)
|
|||
void show_regs(struct pt_regs *regs)
|
||||
{
|
||||
struct task_struct *tsk = current;
|
||||
struct callee_regs *cregs;
|
||||
struct callee_regs *cregs = (struct callee_regs *)tsk->thread.callee_reg;
|
||||
|
||||
/*
|
||||
* generic code calls us with preemption disabled, but some calls
|
||||
|
|
@ -204,25 +197,15 @@ void show_regs(struct pt_regs *regs)
|
|||
STS_BIT(regs, A2), STS_BIT(regs, A1),
|
||||
STS_BIT(regs, E2), STS_BIT(regs, E1));
|
||||
#else
|
||||
pr_cont(" [%2s%2s%2s%2s]",
|
||||
pr_cont(" [%2s%2s%2s%2s] ",
|
||||
STS_BIT(regs, IE),
|
||||
(regs->status32 & STATUS_U_MASK) ? "U " : "K ",
|
||||
STS_BIT(regs, DE), STS_BIT(regs, AE));
|
||||
#endif
|
||||
pr_cont(" BTA: 0x%08lx\n SP: 0x%08lx FP: 0x%08lx BLK: %pS\n",
|
||||
regs->bta, regs->sp, regs->fp, (void *)regs->blink);
|
||||
pr_info("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n",
|
||||
regs->lp_start, regs->lp_end, regs->lp_count);
|
||||
|
||||
/* print regs->r0 thru regs->r12
|
||||
* Sequential printing was generating horrible code
|
||||
*/
|
||||
print_reg_file(&(regs->r0), 0);
|
||||
|
||||
/* If Callee regs were saved, display them too */
|
||||
cregs = (struct callee_regs *)current->thread.callee_reg;
|
||||
print_regs_scratch(regs);
|
||||
if (cregs)
|
||||
show_callee_regs(cregs);
|
||||
print_regs_callee(cregs);
|
||||
|
||||
preempt_disable();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -572,7 +572,7 @@ static unsigned long read_pointer(const u8 **pLoc, const void *end,
|
|||
#else
|
||||
BUILD_BUG_ON(sizeof(u32) != sizeof(value));
|
||||
#endif
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
case DW_EH_PE_native:
|
||||
if (end < (const void *)(ptr.pul + 1))
|
||||
return 0;
|
||||
|
|
@ -827,7 +827,7 @@ static int processCFI(const u8 *start, const u8 *end, unsigned long targetLoc,
|
|||
case DW_CFA_def_cfa:
|
||||
state->cfa.reg = get_uleb128(&ptr.p8, end);
|
||||
unw_debug("cfa_def_cfa: r%lu ", state->cfa.reg);
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case DW_CFA_def_cfa_offset:
|
||||
state->cfa.offs = get_uleb128(&ptr.p8, end);
|
||||
unw_debug("cfa_def_cfa_offset: 0x%lx ",
|
||||
|
|
@ -835,7 +835,7 @@ static int processCFI(const u8 *start, const u8 *end, unsigned long targetLoc,
|
|||
break;
|
||||
case DW_CFA_def_cfa_sf:
|
||||
state->cfa.reg = get_uleb128(&ptr.p8, end);
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case DW_CFA_def_cfa_offset_sf:
|
||||
state->cfa.offs = get_sleb128(&ptr.p8, end)
|
||||
* state->dataAlign;
|
||||
|
|
|
|||
|
|
@ -26,8 +26,8 @@ static unsigned long low_mem_sz;
|
|||
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
static unsigned long min_high_pfn, max_high_pfn;
|
||||
static u64 high_mem_start;
|
||||
static u64 high_mem_sz;
|
||||
static phys_addr_t high_mem_start;
|
||||
static phys_addr_t high_mem_sz;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DISCONTIGMEM
|
||||
|
|
@ -69,6 +69,7 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size)
|
|||
high_mem_sz = size;
|
||||
in_use = 1;
|
||||
memblock_add_node(base, size, 1);
|
||||
memblock_reserve(base, size);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -157,7 +158,7 @@ void __init setup_arch_memory(void)
|
|||
min_high_pfn = PFN_DOWN(high_mem_start);
|
||||
max_high_pfn = PFN_DOWN(high_mem_start + high_mem_sz);
|
||||
|
||||
max_zone_pfn[ZONE_HIGHMEM] = max_high_pfn;
|
||||
max_zone_pfn[ZONE_HIGHMEM] = min_low_pfn;
|
||||
|
||||
high_memory = (void *)(min_high_pfn << PAGE_SHIFT);
|
||||
kmap_init();
|
||||
|
|
@ -166,6 +167,17 @@ void __init setup_arch_memory(void)
|
|||
free_area_init(max_zone_pfn);
|
||||
}
|
||||
|
||||
static void __init highmem_init(void)
|
||||
{
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
unsigned long tmp;
|
||||
|
||||
memblock_free(high_mem_start, high_mem_sz);
|
||||
for (tmp = min_high_pfn; tmp < max_high_pfn; tmp++)
|
||||
free_highmem_page(pfn_to_page(tmp));
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* mem_init - initializes memory
|
||||
*
|
||||
|
|
@ -174,14 +186,7 @@ void __init setup_arch_memory(void)
|
|||
*/
|
||||
void __init mem_init(void)
|
||||
{
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
unsigned long tmp;
|
||||
|
||||
reset_all_zones_managed_pages();
|
||||
for (tmp = min_high_pfn; tmp < max_high_pfn; tmp++)
|
||||
free_highmem_page(pfn_to_page(tmp));
|
||||
#endif
|
||||
|
||||
memblock_free_all();
|
||||
highmem_init();
|
||||
mem_init_print_info(NULL);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -33,7 +33,6 @@
|
|||
#define CTOP_AUX_DPC (CTOP_AUX_BASE + 0x02C)
|
||||
#define CTOP_AUX_LPC (CTOP_AUX_BASE + 0x030)
|
||||
#define CTOP_AUX_EFLAGS (CTOP_AUX_BASE + 0x080)
|
||||
#define CTOP_AUX_IACK (CTOP_AUX_BASE + 0x088)
|
||||
#define CTOP_AUX_GPA1 (CTOP_AUX_BASE + 0x08C)
|
||||
#define CTOP_AUX_UDMC (CTOP_AUX_BASE + 0x300)
|
||||
|
||||
|
|
|
|||
|
|
@ -217,7 +217,7 @@
|
|||
};
|
||||
|
||||
qspi: spi@27200 {
|
||||
compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
|
||||
compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
|
||||
reg = <0x027200 0x184>,
|
||||
<0x027000 0x124>,
|
||||
<0x11c408 0x004>,
|
||||
|
|
|
|||
|
|
@ -284,7 +284,7 @@
|
|||
};
|
||||
|
||||
qspi: spi@27200 {
|
||||
compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
|
||||
compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
|
||||
reg = <0x027200 0x184>,
|
||||
<0x027000 0x124>,
|
||||
<0x11c408 0x004>,
|
||||
|
|
|
|||
|
|
@ -488,7 +488,7 @@
|
|||
};
|
||||
|
||||
spi@18029200 {
|
||||
compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
|
||||
compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
|
||||
reg = <0x18029200 0x184>,
|
||||
<0x18029000 0x124>,
|
||||
<0x1811b408 0x004>,
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
|
||||
backlight: backlight-lvds {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm3 0 20000>;
|
||||
pwms = <&pwm3 0 20000 0>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <6>;
|
||||
power-supply = <®_lcd>;
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@
|
|||
};
|
||||
|
||||
/* PRTWD2 rev 1 bitbang I2C for Ethernet Switch */
|
||||
i2c@4 {
|
||||
i2c {
|
||||
compatible = "i2c-gpio";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c4>;
|
||||
|
|
|
|||
|
|
@ -22,8 +22,6 @@
|
|||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
user-pb {
|
||||
label = "user_pb";
|
||||
|
|
|
|||
|
|
@ -1026,7 +1026,7 @@
|
|||
#define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15 0x01B0 0x04F8 0x0000 0x7 0x0
|
||||
#define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x01B4 0x04FC 0x0000 0x0 0x0
|
||||
#define MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x01B4 0x04FC 0x0840 0x1 0x4
|
||||
#define MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX 0x01B4 0x04FC 0x0000 0x0 0x0
|
||||
#define MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX 0x01B4 0x04FC 0x0000 0x1 0x0
|
||||
#define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4 0x04FC 0x0730 0x2 0x1
|
||||
#define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4 0x04FC 0x0780 0x3 0x2
|
||||
#define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16 0x01B4 0x04FC 0x06DC 0x4 0x1
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@
|
|||
<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
|
||||
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
|
||||
assigned-clock-rates = <0>, <100000000>;
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <&fec1_phy>;
|
||||
status = "okay";
|
||||
|
||||
|
|
|
|||
|
|
@ -394,7 +394,7 @@
|
|||
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
|
||||
<&pcc3 IMX7ULP_CLK_PCTLC>;
|
||||
clock-names = "gpio", "port";
|
||||
gpio-ranges = <&iomuxc1 0 0 32>;
|
||||
gpio-ranges = <&iomuxc1 0 0 20>;
|
||||
};
|
||||
|
||||
gpio_ptd: gpio@40af0000 {
|
||||
|
|
@ -408,7 +408,7 @@
|
|||
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
|
||||
<&pcc3 IMX7ULP_CLK_PCTLD>;
|
||||
clock-names = "gpio", "port";
|
||||
gpio-ranges = <&iomuxc1 0 32 32>;
|
||||
gpio-ranges = <&iomuxc1 0 32 12>;
|
||||
};
|
||||
|
||||
gpio_pte: gpio@40b00000 {
|
||||
|
|
@ -422,7 +422,7 @@
|
|||
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
|
||||
<&pcc3 IMX7ULP_CLK_PCTLE>;
|
||||
clock-names = "gpio", "port";
|
||||
gpio-ranges = <&iomuxc1 0 64 32>;
|
||||
gpio-ranges = <&iomuxc1 0 64 16>;
|
||||
};
|
||||
|
||||
gpio_ptf: gpio@40b10000 {
|
||||
|
|
@ -436,7 +436,7 @@
|
|||
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
|
||||
<&pcc3 IMX7ULP_CLK_PCTLF>;
|
||||
clock-names = "gpio", "port";
|
||||
gpio-ranges = <&iomuxc1 0 96 32>;
|
||||
gpio-ranges = <&iomuxc1 0 96 20>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -51,6 +51,8 @@
|
|||
|
||||
&mcbsp2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcbsp2_pins>;
|
||||
};
|
||||
|
||||
&charger {
|
||||
|
|
@ -102,35 +104,18 @@
|
|||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
lcd0: display@0 {
|
||||
compatible = "panel-dpi";
|
||||
label = "28";
|
||||
status = "okay";
|
||||
/* default-on; */
|
||||
lcd0: display {
|
||||
/* This isn't the exact LCD, but the timings meet spec */
|
||||
compatible = "logicpd,type28";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcd_enable_pin>;
|
||||
enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd INI */
|
||||
backlight = <&bl>;
|
||||
enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;
|
||||
port {
|
||||
lcd_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
};
|
||||
};
|
||||
|
||||
panel-timing {
|
||||
clock-frequency = <9000000>;
|
||||
hactive = <480>;
|
||||
vactive = <272>;
|
||||
hfront-porch = <3>;
|
||||
hback-porch = <2>;
|
||||
hsync-len = <42>;
|
||||
vback-porch = <3>;
|
||||
vfront-porch = <2>;
|
||||
vsync-len = <11>;
|
||||
hsync-active = <1>;
|
||||
vsync-active = <1>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
bl: backlight {
|
||||
|
|
|
|||
|
|
@ -81,6 +81,8 @@
|
|||
};
|
||||
|
||||
&mcbsp2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcbsp2_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -182,7 +182,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x1550000 0x0 0x10000>,
|
||||
<0x0 0x40000000 0x0 0x40000000>;
|
||||
<0x0 0x40000000 0x0 0x20000000>;
|
||||
reg-names = "QuadSPI", "QuadSPI-memory";
|
||||
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "qspi_en", "qspi";
|
||||
|
|
|
|||
|
|
@ -488,11 +488,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
target-module@5000 {
|
||||
target-module@4000 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x5000 0x4>,
|
||||
<0x5010 0x4>,
|
||||
<0x5014 0x4>;
|
||||
reg = <0x4000 0x4>,
|
||||
<0x4010 0x4>,
|
||||
<0x4014 0x4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
|
|
@ -504,7 +504,7 @@
|
|||
ti,syss-mask = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x5000 0x1000>;
|
||||
ranges = <0 0x4000 0x1000>;
|
||||
|
||||
dsi1: encoder@0 {
|
||||
compatible = "ti,omap5-dsi";
|
||||
|
|
@ -514,8 +514,9 @@
|
|||
reg-names = "proto", "phy", "pll";
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
|
||||
clock-names = "fck";
|
||||
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
|
||||
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
|
||||
clock-names = "fck", "sys_clk";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -545,8 +546,9 @@
|
|||
reg-names = "proto", "phy", "pll";
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
|
||||
clock-names = "fck";
|
||||
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
|
||||
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
|
||||
clock-names = "fck", "sys_clk";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -821,7 +821,7 @@
|
|||
timer3: timer3@ffd00100 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xffd01000 0x100>;
|
||||
reg = <0xffd00100 0x100>;
|
||||
clocks = <&l4_sys_free_clk>;
|
||||
clock-names = "timer";
|
||||
resets = <&rst L4SYSTIMER1_RESET>;
|
||||
|
|
|
|||
|
|
@ -495,7 +495,7 @@
|
|||
};
|
||||
|
||||
ocotp: ocotp@400a5000 {
|
||||
compatible = "fsl,vf610-ocotp";
|
||||
compatible = "fsl,vf610-ocotp", "syscon";
|
||||
reg = <0x400a5000 0x1000>;
|
||||
clocks = <&clks VF610_CLK_OCOTP>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,13 +1,11 @@
|
|||
CONFIG_SYSVIPC=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_ARCH_MULTI_V4T=y
|
||||
CONFIG_ARCH_MULTI_V5=y
|
||||
# CONFIG_ARCH_MULTI_V7 is not set
|
||||
|
|
@ -15,19 +13,17 @@ CONFIG_ARCH_INTEGRATOR=y
|
|||
CONFIG_ARCH_INTEGRATOR_AP=y
|
||||
CONFIG_INTEGRATOR_IMPD1=y
|
||||
CONFIG_ARCH_INTEGRATOR_CP=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
# CONFIG_ATAGS is not set
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_CMDLINE="console=ttyAM0,38400n8 root=/dev/nfs ip=bootp"
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
||||
CONFIG_CPU_FREQ_GOV_USERSPACE=y
|
||||
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
|
||||
CONFIG_CPUFREQ_DT=y
|
||||
CONFIG_CMA=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
|
@ -37,6 +33,7 @@ CONFIG_IP_PNP=y
|
|||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_PCI=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_AFS_PARTS=y
|
||||
|
|
@ -52,9 +49,12 @@ CONFIG_BLK_DEV_RAM_SIZE=8192
|
|||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E100=y
|
||||
CONFIG_SMC91X=y
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
# CONFIG_KEYBOARD_ATKBD is not set
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
# CONFIG_SERIO_SERPORT is not set
|
||||
CONFIG_DRM=y
|
||||
CONFIG_DRM_DISPLAY_CONNECTOR=y
|
||||
CONFIG_DRM_SIMPLE_BRIDGE=y
|
||||
CONFIG_DRM_PL111=y
|
||||
CONFIG_FB_MODE_HELPERS=y
|
||||
|
|
|
|||
|
|
@ -547,7 +547,7 @@ static int arch_build_bp_info(struct perf_event *bp,
|
|||
if ((hw->ctrl.type != ARM_BREAKPOINT_EXECUTE)
|
||||
&& max_watchpoint_len >= 8)
|
||||
break;
|
||||
/* Else, fall through */
|
||||
fallthrough;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
@ -612,12 +612,12 @@ int hw_breakpoint_arch_parse(struct perf_event *bp,
|
|||
/* Allow halfword watchpoints and breakpoints. */
|
||||
if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2)
|
||||
break;
|
||||
/* Else, fall through */
|
||||
fallthrough;
|
||||
case 3:
|
||||
/* Allow single byte watchpoint. */
|
||||
if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1)
|
||||
break;
|
||||
/* Else, fall through */
|
||||
fallthrough;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
|
|
@ -884,7 +884,7 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
|
|||
break;
|
||||
case ARM_ENTRY_ASYNC_WATCHPOINT:
|
||||
WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n");
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
case ARM_ENTRY_SYNC_WATCHPOINT:
|
||||
watchpoint_handler(addr, fsr, regs);
|
||||
break;
|
||||
|
|
@ -933,7 +933,7 @@ static bool core_has_os_save_restore(void)
|
|||
ARM_DBG_READ(c1, c1, 4, oslsr);
|
||||
if (oslsr & ARM_OSLSR_OSLM0)
|
||||
return true;
|
||||
/* Else, fall through */
|
||||
fallthrough;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -596,7 +596,7 @@ static int do_signal(struct pt_regs *regs, int syscall)
|
|||
switch (retval) {
|
||||
case -ERESTART_RESTARTBLOCK:
|
||||
restart -= 2;
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
case -ERESTARTNOHAND:
|
||||
case -ERESTARTSYS:
|
||||
case -ERESTARTNOINTR:
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ static int crunch_do(struct notifier_block *self, unsigned long cmd, void *t)
|
|||
* FALLTHROUGH: Ensure we don't try to overwrite our newly
|
||||
* initialised state information on the first fault.
|
||||
*/
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
|
||||
case THREAD_NOTIFY_EXIT:
|
||||
crunch_task_release(thread);
|
||||
|
|
|
|||
|
|
@ -123,19 +123,19 @@ void mmp2_pm_enter_lowpower_mode(int state)
|
|||
case POWER_MODE_SYS_SLEEP:
|
||||
apcr |= MPMU_PCR_PJ_SLPEN; /* set the SLPEN bit */
|
||||
apcr |= MPMU_PCR_PJ_VCTCXOSD; /* set VCTCXOSD */
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case POWER_MODE_CHIP_SLEEP:
|
||||
apcr |= MPMU_PCR_PJ_SLPEN;
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case POWER_MODE_APPS_SLEEP:
|
||||
apcr |= MPMU_PCR_PJ_APBSD; /* set APBSD */
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case POWER_MODE_APPS_IDLE:
|
||||
apcr |= MPMU_PCR_PJ_AXISD; /* set AXISDD bit */
|
||||
apcr |= MPMU_PCR_PJ_DDRCORSD; /* set DDRCORSD bit */
|
||||
idle_cfg |= APMU_PJ_IDLE_CFG_PJ_PWRDWN; /* PJ power down */
|
||||
apcr |= MPMU_PCR_PJ_SPSD;
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case POWER_MODE_CORE_EXTIDLE:
|
||||
idle_cfg |= APMU_PJ_IDLE_CFG_PJ_IDLE; /* set the IDLE bit */
|
||||
idle_cfg &= ~APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK;
|
||||
|
|
|
|||
|
|
@ -145,23 +145,23 @@ void pxa910_pm_enter_lowpower_mode(int state)
|
|||
case POWER_MODE_UDR:
|
||||
/* only shutdown APB in UDR */
|
||||
apcr |= MPMU_APCR_STBYEN | MPMU_APCR_APBSD;
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case POWER_MODE_SYS_SLEEP:
|
||||
apcr |= MPMU_APCR_SLPEN; /* set the SLPEN bit */
|
||||
apcr |= MPMU_APCR_VCTCXOSD; /* set VCTCXOSD */
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case POWER_MODE_APPS_SLEEP:
|
||||
apcr |= MPMU_APCR_DDRCORSD; /* set DDRCORSD */
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case POWER_MODE_APPS_IDLE:
|
||||
apcr |= MPMU_APCR_AXISD; /* set AXISDD bit */
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case POWER_MODE_CORE_EXTIDLE:
|
||||
idle_cfg |= APMU_MOH_IDLE_CFG_MOH_IDLE;
|
||||
idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWRDWN;
|
||||
idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWR_SW(3)
|
||||
| APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(3);
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case POWER_MODE_CORE_INTIDLE:
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -396,7 +396,6 @@ void __init omap3xxx_check_revision(void)
|
|||
cpu_rev = "3.1";
|
||||
break;
|
||||
case 7:
|
||||
/* FALLTHROUGH */
|
||||
default:
|
||||
/* Use the latest known revision as default */
|
||||
omap_revision = OMAP3430_REV_ES3_1_2;
|
||||
|
|
@ -416,7 +415,6 @@ void __init omap3xxx_check_revision(void)
|
|||
cpu_rev = "1.0";
|
||||
break;
|
||||
case 1:
|
||||
/* FALLTHROUGH */
|
||||
default:
|
||||
omap_revision = AM35XX_REV_ES1_1;
|
||||
cpu_rev = "1.1";
|
||||
|
|
@ -435,7 +433,6 @@ void __init omap3xxx_check_revision(void)
|
|||
cpu_rev = "1.1";
|
||||
break;
|
||||
case 2:
|
||||
/* FALLTHROUGH */
|
||||
default:
|
||||
omap_revision = OMAP3630_REV_ES1_2;
|
||||
cpu_rev = "1.2";
|
||||
|
|
@ -456,7 +453,6 @@ void __init omap3xxx_check_revision(void)
|
|||
cpu_rev = "2.0";
|
||||
break;
|
||||
case 3:
|
||||
/* FALLTHROUGH */
|
||||
default:
|
||||
omap_revision = TI8168_REV_ES2_1;
|
||||
cpu_rev = "2.1";
|
||||
|
|
@ -473,7 +469,6 @@ void __init omap3xxx_check_revision(void)
|
|||
cpu_rev = "2.0";
|
||||
break;
|
||||
case 2:
|
||||
/* FALLTHROUGH */
|
||||
default:
|
||||
omap_revision = AM335X_REV_ES2_1;
|
||||
cpu_rev = "2.1";
|
||||
|
|
@ -491,7 +486,6 @@ void __init omap3xxx_check_revision(void)
|
|||
cpu_rev = "1.1";
|
||||
break;
|
||||
case 2:
|
||||
/* FALLTHROUGH */
|
||||
default:
|
||||
omap_revision = AM437X_REV_ES1_2;
|
||||
cpu_rev = "1.2";
|
||||
|
|
@ -502,7 +496,6 @@ void __init omap3xxx_check_revision(void)
|
|||
case 0xb968:
|
||||
switch (rev) {
|
||||
case 0:
|
||||
/* FALLTHROUGH */
|
||||
case 1:
|
||||
omap_revision = TI8148_REV_ES1_0;
|
||||
cpu_rev = "1.0";
|
||||
|
|
@ -512,7 +505,6 @@ void __init omap3xxx_check_revision(void)
|
|||
cpu_rev = "2.0";
|
||||
break;
|
||||
case 3:
|
||||
/* FALLTHROUGH */
|
||||
default:
|
||||
omap_revision = TI8148_REV_ES2_1;
|
||||
cpu_rev = "2.1";
|
||||
|
|
|
|||
|
|
@ -74,7 +74,7 @@ static struct powerdomain *_get_pwrdm(struct device *dev)
|
|||
return pwrdm;
|
||||
|
||||
clk = of_clk_get(dev->of_node->parent, 0);
|
||||
if (!clk) {
|
||||
if (IS_ERR(clk)) {
|
||||
dev_err(dev, "no fck found\n");
|
||||
return NULL;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -240,7 +240,7 @@ static int _omap_device_notifier_call(struct notifier_block *nb,
|
|||
if (pdev->dev.of_node)
|
||||
omap_device_build_from_dt(pdev);
|
||||
omap_auxdata_legacy_init(dev);
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
default:
|
||||
od = to_omap_device(pdev);
|
||||
if (od)
|
||||
|
|
|
|||
|
|
@ -298,11 +298,7 @@ static void omap3_pm_idle(void)
|
|||
if (omap_irq_pending())
|
||||
return;
|
||||
|
||||
trace_cpu_idle_rcuidle(1, smp_processor_id());
|
||||
|
||||
omap_sram_idle();
|
||||
|
||||
trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SUSPEND
|
||||
|
|
|
|||
|
|
@ -624,7 +624,7 @@ static void __init dns323_init(void)
|
|||
dns323ab_leds[0].active_low = 1;
|
||||
gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
|
||||
gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
case DNS323_REV_B1:
|
||||
i2c_register_board_info(0, dns323ab_i2c_devices,
|
||||
ARRAY_SIZE(dns323ab_i2c_devices));
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ static int __init parse_tag_acorn(const struct tag *tag)
|
|||
switch (tag->u.acorn.vram_pages) {
|
||||
case 512:
|
||||
vram_size += PAGE_SIZE * 256;
|
||||
/* Fall through - ??? */
|
||||
fallthrough; /* ??? */
|
||||
case 256:
|
||||
vram_size += PAGE_SIZE * 256;
|
||||
default:
|
||||
|
|
|
|||
|
|
@ -70,7 +70,7 @@ static void __init tegra_cpu_reset_handler_enable(void)
|
|||
switch (err) {
|
||||
case -ENOSYS:
|
||||
tegra_cpu_reset_handler_set(reset_address);
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case 0:
|
||||
is_enabled = true;
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -694,7 +694,7 @@ thumb2arm(u16 tinstr)
|
|||
return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |
|
||||
(tinstr & 255); /* register_list */
|
||||
}
|
||||
/* Else, fall through - for illegal instruction case */
|
||||
fallthrough; /* for illegal instruction case */
|
||||
|
||||
default:
|
||||
return BAD_INSTR;
|
||||
|
|
@ -750,7 +750,7 @@ do_alignment_t32_to_handler(u32 *pinstr, struct pt_regs *regs,
|
|||
case 0xe8e0:
|
||||
case 0xe9e0:
|
||||
poffset->un = (tinst2 & 0xff) << 2;
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
|
||||
case 0xe940:
|
||||
case 0xe9c0:
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@ static void cpu_v7_spectre_init(void)
|
|||
/* Other ARM CPUs require no workaround */
|
||||
if (read_cpuid_implementor() == ARM_CPU_IMP_ARM)
|
||||
break;
|
||||
/* fallthrough */
|
||||
fallthrough;
|
||||
/* Cortex A57/A72 require firmware workaround */
|
||||
case ARM_CPU_PART_CORTEX_A57:
|
||||
case ARM_CPU_PART_CORTEX_A72: {
|
||||
|
|
|
|||
|
|
@ -309,14 +309,14 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
|
|||
* not supported by current hardware on OMAP1
|
||||
* w |= (0x03 << 7);
|
||||
*/
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case OMAP_DMA_DATA_BURST_16:
|
||||
if (dma_omap2plus()) {
|
||||
burst = 0x3;
|
||||
break;
|
||||
}
|
||||
/* OMAP1 don't support burst 16 */
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
|
|
@ -393,7 +393,7 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
|
|||
break;
|
||||
}
|
||||
/* OMAP1 don't support burst 16 */
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
default:
|
||||
printk(KERN_ERR "Invalid DMA burst mode\n");
|
||||
BUG();
|
||||
|
|
|
|||
|
|
@ -307,7 +307,7 @@ static bool __kprobes decode_regs(probes_opcode_t *pinsn, u32 regs, bool modify)
|
|||
case REG_TYPE_NOPCWB:
|
||||
if (!is_writeback(insn))
|
||||
break; /* No writeback, so any register is OK */
|
||||
/* fall through... */
|
||||
fallthrough;
|
||||
case REG_TYPE_NOPC:
|
||||
case REG_TYPE_NOPCX:
|
||||
/* Reject PC (R15) */
|
||||
|
|
|
|||
|
|
@ -280,7 +280,7 @@ void __kprobes kprobe_handler(struct pt_regs *regs)
|
|||
/* A nested probe was hit in FIQ, it is a BUG */
|
||||
pr_warn("Unrecoverable kprobe detected.\n");
|
||||
dump_kprobe(p);
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
default:
|
||||
/* impossible cases */
|
||||
BUG();
|
||||
|
|
|
|||
|
|
@ -82,8 +82,8 @@ endif
|
|||
# compiler to generate them and consequently to break the single image contract
|
||||
# we pass it only to the assembler. This option is utilized only in case of non
|
||||
# integrated assemblers.
|
||||
ifneq ($(CONFIG_AS_HAS_ARMV8_4), y)
|
||||
branch-prot-flags-$(CONFIG_AS_HAS_PAC) += -Wa,-march=armv8.3-a
|
||||
ifeq ($(CONFIG_AS_HAS_PAC), y)
|
||||
asm-arch := armv8.3-a
|
||||
endif
|
||||
endif
|
||||
|
||||
|
|
@ -91,7 +91,12 @@ KBUILD_CFLAGS += $(branch-prot-flags-y)
|
|||
|
||||
ifeq ($(CONFIG_AS_HAS_ARMV8_4), y)
|
||||
# make sure to pass the newest target architecture to -march.
|
||||
KBUILD_CFLAGS += -Wa,-march=armv8.4-a
|
||||
asm-arch := armv8.4-a
|
||||
endif
|
||||
|
||||
ifdef asm-arch
|
||||
KBUILD_CFLAGS += -Wa,-march=$(asm-arch) \
|
||||
-DARM64_ASM_ARCH='"$(asm-arch)"'
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_SHADOW_CALL_STACK), y)
|
||||
|
|
@ -165,7 +170,8 @@ zinstall install:
|
|||
PHONY += vdso_install
|
||||
vdso_install:
|
||||
$(Q)$(MAKE) $(build)=arch/arm64/kernel/vdso $@
|
||||
$(Q)$(MAKE) $(build)=arch/arm64/kernel/vdso32 $@
|
||||
$(if $(CONFIG_COMPAT_VDSO), \
|
||||
$(Q)$(MAKE) $(build)=arch/arm64/kernel/vdso32 $@)
|
||||
|
||||
# We use MRPROPER_FILES and CLEAN_FILES now
|
||||
archclean:
|
||||
|
|
|
|||
|
|
@ -745,7 +745,7 @@
|
|||
};
|
||||
|
||||
qspi: spi@66470200 {
|
||||
compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi";
|
||||
compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";
|
||||
reg = <0x66470200 0x184>,
|
||||
<0x66470000 0x124>,
|
||||
<0x67017408 0x004>,
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb
|
|||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
|
||||
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
|
||||
dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
|
||||
dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
|
||||
|
|
|
|||
|
|
@ -702,7 +702,7 @@
|
|||
reg = <0x30bd0000 0x10000>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
|
||||
<&clk IMX8MP_CLK_SDMA1_ROOT>;
|
||||
<&clk IMX8MP_CLK_AHB>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
|
||||
|
|
|
|||
|
|
@ -423,7 +423,7 @@
|
|||
tmu: tmu@30260000 {
|
||||
compatible = "fsl,imx8mq-tmu";
|
||||
reg = <0x30260000 0x10000>;
|
||||
interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
|
||||
little-endian;
|
||||
fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
|
||||
|
|
|
|||
|
|
@ -686,6 +686,8 @@
|
|||
clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
|
||||
<&topckgen CLK_TOP_MSDC50_0_SEL>;
|
||||
clock-names = "source", "hclk";
|
||||
resets = <&pericfg MT7622_PERI_MSDC0_SW_RST>;
|
||||
reset-names = "hrst";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -337,8 +337,9 @@
|
|||
compatible = "nvidia,tegra186-sdhci";
|
||||
reg = <0x0 0x03400000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
|
||||
clock-names = "sdhci";
|
||||
clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
|
||||
<&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
|
||||
clock-names = "sdhci", "tmclk";
|
||||
resets = <&bpmp TEGRA186_RESET_SDMMC1>;
|
||||
reset-names = "sdhci";
|
||||
interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
|
||||
|
|
@ -366,8 +367,9 @@
|
|||
compatible = "nvidia,tegra186-sdhci";
|
||||
reg = <0x0 0x03420000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
|
||||
clock-names = "sdhci";
|
||||
clocks = <&bpmp TEGRA186_CLK_SDMMC2>,
|
||||
<&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
|
||||
clock-names = "sdhci", "tmclk";
|
||||
resets = <&bpmp TEGRA186_RESET_SDMMC2>;
|
||||
reset-names = "sdhci";
|
||||
interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>,
|
||||
|
|
@ -390,8 +392,9 @@
|
|||
compatible = "nvidia,tegra186-sdhci";
|
||||
reg = <0x0 0x03440000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
|
||||
clock-names = "sdhci";
|
||||
clocks = <&bpmp TEGRA186_CLK_SDMMC3>,
|
||||
<&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
|
||||
clock-names = "sdhci", "tmclk";
|
||||
resets = <&bpmp TEGRA186_RESET_SDMMC3>;
|
||||
reset-names = "sdhci";
|
||||
interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>,
|
||||
|
|
@ -416,8 +419,9 @@
|
|||
compatible = "nvidia,tegra186-sdhci";
|
||||
reg = <0x0 0x03460000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
|
||||
clock-names = "sdhci";
|
||||
clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
|
||||
<&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
|
||||
clock-names = "sdhci", "tmclk";
|
||||
assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
|
||||
<&bpmp TEGRA186_CLK_PLLC4_VCO>;
|
||||
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
|
||||
|
|
|
|||
|
|
@ -460,8 +460,9 @@
|
|||
compatible = "nvidia,tegra194-sdhci";
|
||||
reg = <0x03400000 0x10000>;
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA194_CLK_SDMMC1>;
|
||||
clock-names = "sdhci";
|
||||
clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
|
||||
<&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
|
||||
clock-names = "sdhci", "tmclk";
|
||||
resets = <&bpmp TEGRA194_RESET_SDMMC1>;
|
||||
reset-names = "sdhci";
|
||||
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
|
||||
|
|
@ -485,8 +486,9 @@
|
|||
compatible = "nvidia,tegra194-sdhci";
|
||||
reg = <0x03440000 0x10000>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA194_CLK_SDMMC3>;
|
||||
clock-names = "sdhci";
|
||||
clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
|
||||
<&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
|
||||
clock-names = "sdhci", "tmclk";
|
||||
resets = <&bpmp TEGRA194_RESET_SDMMC3>;
|
||||
reset-names = "sdhci";
|
||||
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
|
||||
|
|
@ -511,8 +513,9 @@
|
|||
compatible = "nvidia,tegra194-sdhci";
|
||||
reg = <0x03460000 0x10000>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA194_CLK_SDMMC4>;
|
||||
clock-names = "sdhci";
|
||||
clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
|
||||
<&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
|
||||
clock-names = "sdhci", "tmclk";
|
||||
assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
|
||||
<&bpmp TEGRA194_CLK_PLLC4>;
|
||||
assigned-clock-parents =
|
||||
|
|
|
|||
|
|
@ -1194,8 +1194,9 @@
|
|||
compatible = "nvidia,tegra210-sdhci";
|
||||
reg = <0x0 0x700b0000 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
|
||||
clock-names = "sdhci";
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
|
||||
<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
|
||||
clock-names = "sdhci", "tmclk";
|
||||
resets = <&tegra_car 14>;
|
||||
reset-names = "sdhci";
|
||||
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
|
||||
|
|
@ -1222,8 +1223,9 @@
|
|||
compatible = "nvidia,tegra210-sdhci";
|
||||
reg = <0x0 0x700b0200 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
|
||||
clock-names = "sdhci";
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC2>,
|
||||
<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
|
||||
clock-names = "sdhci", "tmclk";
|
||||
resets = <&tegra_car 9>;
|
||||
reset-names = "sdhci";
|
||||
pinctrl-names = "sdmmc-1v8-drv";
|
||||
|
|
@ -1239,8 +1241,9 @@
|
|||
compatible = "nvidia,tegra210-sdhci";
|
||||
reg = <0x0 0x700b0400 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
|
||||
clock-names = "sdhci";
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC3>,
|
||||
<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
|
||||
clock-names = "sdhci", "tmclk";
|
||||
resets = <&tegra_car 69>;
|
||||
reset-names = "sdhci";
|
||||
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
|
||||
|
|
@ -1262,8 +1265,9 @@
|
|||
compatible = "nvidia,tegra210-sdhci";
|
||||
reg = <0x0 0x700b0600 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
|
||||
clock-names = "sdhci";
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
|
||||
<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
|
||||
clock-names = "sdhci", "tmclk";
|
||||
resets = <&tegra_car 15>;
|
||||
reset-names = "sdhci";
|
||||
pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
|
||||
|
|
|
|||
|
|
@ -417,10 +417,10 @@
|
|||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dst-id = <56>;
|
||||
ti,sci-rm-range-girq = <0x1>;
|
||||
ti,sci-dev-id = <100>;
|
||||
ti,interrupt-ranges = <0 392 32>;
|
||||
};
|
||||
|
||||
main_navss {
|
||||
|
|
@ -438,10 +438,11 @@
|
|||
ti,intr-trigger-type = <4>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dst-id = <56>;
|
||||
ti,sci-rm-range-girq = <0x0>, <0x2>;
|
||||
ti,sci-dev-id = <182>;
|
||||
ti,interrupt-ranges = <0 64 64>,
|
||||
<64 448 64>;
|
||||
};
|
||||
|
||||
inta_main_udmass: interrupt-controller@33d00000 {
|
||||
|
|
@ -452,8 +453,7 @@
|
|||
msi-controller;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <179>;
|
||||
ti,sci-rm-range-vint = <0x0>;
|
||||
ti,sci-rm-range-global-event = <0x1>;
|
||||
ti,interrupt-ranges = <0 0 256>;
|
||||
};
|
||||
|
||||
secure_proxy_main: mailbox@32c00000 {
|
||||
|
|
@ -589,7 +589,7 @@
|
|||
<0x0 0x33000000 0x0 0x40000>;
|
||||
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
|
||||
ti,num-rings = <818>;
|
||||
ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
|
||||
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
|
||||
ti,dma-ring-reset-quirk;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <187>;
|
||||
|
|
@ -609,11 +609,11 @@
|
|||
ti,sci-dev-id = <188>;
|
||||
ti,ringacc = <&ringacc>;
|
||||
|
||||
ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
|
||||
<0x2>; /* TX_CHAN */
|
||||
ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
|
||||
<0x5>; /* RX_CHAN */
|
||||
ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
|
||||
ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
|
||||
<0xd>; /* TX_CHAN */
|
||||
ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
|
||||
<0xa>; /* RX_CHAN */
|
||||
ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
|
||||
};
|
||||
|
||||
cpts@310d0000 {
|
||||
|
|
@ -622,7 +622,7 @@
|
|||
reg-names = "cpts";
|
||||
clocks = <&main_cpts_mux>;
|
||||
clock-names = "cpts";
|
||||
interrupts-extended = <&intr_main_navss 163 0>;
|
||||
interrupts-extended = <&intr_main_navss 391>;
|
||||
interrupt-names = "cpts";
|
||||
ti,cpts-periodic-outputs = <6>;
|
||||
ti,cpts-ext-ts-inputs = <8>;
|
||||
|
|
@ -645,8 +645,7 @@
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&intr_main_gpio>;
|
||||
interrupts = <57 256>, <57 257>, <57 258>, <57 259>, <57 260>,
|
||||
<57 261>;
|
||||
interrupts = <192>, <193>, <194>, <195>, <196>, <197>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <96>;
|
||||
|
|
@ -661,8 +660,7 @@
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&intr_main_gpio>;
|
||||
interrupts = <58 256>, <58 257>, <58 258>, <58 259>, <58 260>,
|
||||
<58 261>;
|
||||
interrupts = <200>, <201>, <202>, <203>, <204>, <205>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <90>;
|
||||
|
|
|
|||
|
|
@ -134,7 +134,7 @@
|
|||
<0x0 0x2a500000 0x0 0x40000>;
|
||||
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
|
||||
ti,num-rings = <286>;
|
||||
ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
|
||||
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
|
||||
ti,dma-ring-reset-quirk;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <195>;
|
||||
|
|
@ -154,11 +154,11 @@
|
|||
ti,sci-dev-id = <194>;
|
||||
ti,ringacc = <&mcu_ringacc>;
|
||||
|
||||
ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
|
||||
<0x2>; /* TX_CHAN */
|
||||
ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
|
||||
<0x4>; /* RX_CHAN */
|
||||
ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
|
||||
ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
|
||||
<0xd>; /* TX_CHAN */
|
||||
ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
|
||||
<0xa>; /* RX_CHAN */
|
||||
ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -74,10 +74,10 @@
|
|||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dst-id = <56>;
|
||||
ti,sci-rm-range-girq = <0x4>;
|
||||
ti,sci-dev-id = <156>;
|
||||
ti,interrupt-ranges = <0 712 16>;
|
||||
};
|
||||
|
||||
wkup_gpio0: wkup_gpio0@42110000 {
|
||||
|
|
@ -86,7 +86,7 @@
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&intr_wkup_gpio>;
|
||||
interrupts = <59 128>, <59 129>, <59 130>, <59 131>;
|
||||
interrupts = <60>, <61>, <62>, <63>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <56>;
|
||||
|
|
|
|||
|
|
@ -384,7 +384,7 @@
|
|||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
interrupts = <164 0>;
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
|
|
@ -393,7 +393,7 @@
|
|||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
interrupts = <165 0>;
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
|
|
|
|||
|
|
@ -287,7 +287,7 @@
|
|||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
interrupts = <214 0>;
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
|
|
@ -301,7 +301,7 @@
|
|||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
interrupts = <215 0>;
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
|
|
@ -315,7 +315,7 @@
|
|||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
interrupts = <216 0>;
|
||||
interrupts = <428>;
|
||||
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
|
|
@ -329,7 +329,7 @@
|
|||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
interrupts = <217 0>;
|
||||
interrupts = <424>;
|
||||
|
||||
mbox_c66_0: mbox-c66-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
|
|
@ -343,7 +343,7 @@
|
|||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
interrupts = <218 0>;
|
||||
interrupts = <420>;
|
||||
|
||||
mbox_c71_0: mbox-c71-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue