libata-sff: reorder SFF/BMDMA functions
Reorder functions such that SFF and BMDMA functions are grouped. While at it, s/BMDMA/SFF in a few comments where it actually meant SFF. Signed-off-by: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>hifive-unleashed-5.1
Tejun Heo
Jeff Garzik
parent
6bc0d390dd
commit
9f2f72107f
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@ -71,26 +71,6 @@ const struct ata_port_operations ata_sff_port_ops = {
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};
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EXPORT_SYMBOL_GPL(ata_sff_port_ops);
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const struct ata_port_operations ata_bmdma_port_ops = {
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.inherits = &ata_sff_port_ops,
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.mode_filter = ata_bmdma_mode_filter,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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};
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EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
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const struct ata_port_operations ata_bmdma32_port_ops = {
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.inherits = &ata_bmdma_port_ops,
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.sff_data_xfer = ata_sff_data_xfer32,
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.port_start = ata_sff_port_start32,
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};
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EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
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/**
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* ata_fill_sg - Fill PCI IDE PRD table
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* @qc: Metadata associated with taskfile to be transferred
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@ -1750,7 +1730,7 @@ unsigned int ata_sff_host_intr(struct ata_port *ap,
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goto idle_irq;
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}
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/* ack bmdma irq events */
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/* clear irq events */
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ap->ops->sff_irq_clear(ap);
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ata_sff_hsm_move(ap, qc, status, 0);
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@ -1904,7 +1884,7 @@ EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt);
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* ata_sff_freeze - Freeze SFF controller port
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* @ap: port to freeze
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*
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* Freeze BMDMA controller port.
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* Freeze SFF controller port.
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*
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* LOCKING:
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* Inherited from caller.
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@ -2533,208 +2513,8 @@ void ata_sff_std_ports(struct ata_ioports *ioaddr)
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}
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EXPORT_SYMBOL_GPL(ata_sff_std_ports);
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unsigned long ata_bmdma_mode_filter(struct ata_device *adev,
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unsigned long xfer_mask)
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{
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/* Filter out DMA modes if the device has been configured by
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the BIOS as PIO only */
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if (adev->link->ap->ioaddr.bmdma_addr == NULL)
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xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
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return xfer_mask;
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}
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EXPORT_SYMBOL_GPL(ata_bmdma_mode_filter);
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/**
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* ata_bmdma_setup - Set up PCI IDE BMDMA transaction
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* @qc: Info associated with this ATA transaction.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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void ata_bmdma_setup(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
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u8 dmactl;
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/* load PRD table addr. */
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mb(); /* make sure PRD table writes are visible to controller */
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iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
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/* specify data direction, triple-check start bit is clear */
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dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
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if (!rw)
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dmactl |= ATA_DMA_WR;
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iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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/* issue r/w command */
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ap->ops->sff_exec_command(ap, &qc->tf);
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}
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EXPORT_SYMBOL_GPL(ata_bmdma_setup);
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/**
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* ata_bmdma_start - Start a PCI IDE BMDMA transaction
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* @qc: Info associated with this ATA transaction.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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void ata_bmdma_start(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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u8 dmactl;
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/* start host DMA transaction */
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dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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/* Strictly, one may wish to issue an ioread8() here, to
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* flush the mmio write. However, control also passes
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* to the hardware at this point, and it will interrupt
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* us when we are to resume control. So, in effect,
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* we don't care when the mmio write flushes.
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* Further, a read of the DMA status register _immediately_
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* following the write may not be what certain flaky hardware
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* is expected, so I think it is best to not add a readb()
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* without first all the MMIO ATA cards/mobos.
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* Or maybe I'm just being paranoid.
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*
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* FIXME: The posting of this write means I/O starts are
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* unneccessarily delayed for MMIO
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*/
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}
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EXPORT_SYMBOL_GPL(ata_bmdma_start);
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/**
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* ata_bmdma_stop - Stop PCI IDE BMDMA transfer
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* @qc: Command we are ending DMA for
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*
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* Clears the ATA_DMA_START flag in the dma control register
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*
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* May be used as the bmdma_stop() entry in ata_port_operations.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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void ata_bmdma_stop(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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void __iomem *mmio = ap->ioaddr.bmdma_addr;
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/* clear start/stop bit */
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iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
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mmio + ATA_DMA_CMD);
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/* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
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ata_sff_dma_pause(ap);
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}
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EXPORT_SYMBOL_GPL(ata_bmdma_stop);
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/**
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* ata_bmdma_status - Read PCI IDE BMDMA status
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* @ap: Port associated with this ATA transaction.
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*
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* Read and return BMDMA status register.
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*
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* May be used as the bmdma_status() entry in ata_port_operations.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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u8 ata_bmdma_status(struct ata_port *ap)
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{
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return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
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}
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EXPORT_SYMBOL_GPL(ata_bmdma_status);
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#ifdef CONFIG_PCI
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/**
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* ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
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* @pdev: PCI device
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*
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* Some PCI ATA devices report simplex mode but in fact can be told to
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* enter non simplex mode. This implements the necessary logic to
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* perform the task on such devices. Calling it on other devices will
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* have -undefined- behaviour.
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*/
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int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
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{
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unsigned long bmdma = pci_resource_start(pdev, 4);
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u8 simplex;
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if (bmdma == 0)
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return -ENOENT;
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simplex = inb(bmdma + 0x02);
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outb(simplex & 0x60, bmdma + 0x02);
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simplex = inb(bmdma + 0x02);
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if (simplex & 0x80)
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return -EOPNOTSUPP;
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return 0;
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}
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EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
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/**
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* ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
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* @host: target ATA host
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*
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* Acquire PCI BMDMA resources and initialize @host accordingly.
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*
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* LOCKING:
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* Inherited from calling layer (may sleep).
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*
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* RETURNS:
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* 0 on success, -errno otherwise.
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*/
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int ata_pci_bmdma_init(struct ata_host *host)
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{
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struct device *gdev = host->dev;
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struct pci_dev *pdev = to_pci_dev(gdev);
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int i, rc;
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/* No BAR4 allocation: No DMA */
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if (pci_resource_start(pdev, 4) == 0)
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return 0;
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/* TODO: If we get no DMA mask we should fall back to PIO */
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rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
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if (rc)
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return rc;
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rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
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if (rc)
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return rc;
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/* request and iomap DMA region */
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rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
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if (rc) {
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dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n");
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return -ENOMEM;
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}
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host->iomap = pcim_iomap_table(pdev);
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for (i = 0; i < 2; i++) {
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struct ata_port *ap = host->ports[i];
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void __iomem *bmdma = host->iomap[4] + 8 * i;
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if (ata_port_is_dummy(ap))
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continue;
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ap->ioaddr.bmdma_addr = bmdma;
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if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
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(ioread8(bmdma + 2) & 0x80))
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host->flags |= ATA_HOST_SIMPLEX;
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ata_port_desc(ap, "bmdma 0x%llx",
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(unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
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static int ata_resources_present(struct pci_dev *pdev, int port)
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{
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int i;
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@ -3059,3 +2839,227 @@ out:
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EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
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#endif /* CONFIG_PCI */
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const struct ata_port_operations ata_bmdma_port_ops = {
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.inherits = &ata_sff_port_ops,
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.mode_filter = ata_bmdma_mode_filter,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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};
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EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
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const struct ata_port_operations ata_bmdma32_port_ops = {
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.inherits = &ata_bmdma_port_ops,
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.sff_data_xfer = ata_sff_data_xfer32,
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.port_start = ata_sff_port_start32,
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};
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EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
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unsigned long ata_bmdma_mode_filter(struct ata_device *adev,
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unsigned long xfer_mask)
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{
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/* Filter out DMA modes if the device has been configured by
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the BIOS as PIO only */
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if (adev->link->ap->ioaddr.bmdma_addr == NULL)
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xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
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return xfer_mask;
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}
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EXPORT_SYMBOL_GPL(ata_bmdma_mode_filter);
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/**
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* ata_bmdma_setup - Set up PCI IDE BMDMA transaction
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* @qc: Info associated with this ATA transaction.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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void ata_bmdma_setup(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
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u8 dmactl;
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/* load PRD table addr. */
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mb(); /* make sure PRD table writes are visible to controller */
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iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
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/* specify data direction, triple-check start bit is clear */
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dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
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if (!rw)
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dmactl |= ATA_DMA_WR;
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iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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/* issue r/w command */
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ap->ops->sff_exec_command(ap, &qc->tf);
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}
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EXPORT_SYMBOL_GPL(ata_bmdma_setup);
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/**
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* ata_bmdma_start - Start a PCI IDE BMDMA transaction
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* @qc: Info associated with this ATA transaction.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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void ata_bmdma_start(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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u8 dmactl;
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/* start host DMA transaction */
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dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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/* Strictly, one may wish to issue an ioread8() here, to
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* flush the mmio write. However, control also passes
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* to the hardware at this point, and it will interrupt
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* us when we are to resume control. So, in effect,
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* we don't care when the mmio write flushes.
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* Further, a read of the DMA status register _immediately_
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* following the write may not be what certain flaky hardware
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* is expected, so I think it is best to not add a readb()
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* without first all the MMIO ATA cards/mobos.
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* Or maybe I'm just being paranoid.
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*
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* FIXME: The posting of this write means I/O starts are
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* unneccessarily delayed for MMIO
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*/
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}
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EXPORT_SYMBOL_GPL(ata_bmdma_start);
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/**
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* ata_bmdma_stop - Stop PCI IDE BMDMA transfer
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* @qc: Command we are ending DMA for
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*
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* Clears the ATA_DMA_START flag in the dma control register
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*
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* May be used as the bmdma_stop() entry in ata_port_operations.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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void ata_bmdma_stop(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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void __iomem *mmio = ap->ioaddr.bmdma_addr;
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/* clear start/stop bit */
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iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
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mmio + ATA_DMA_CMD);
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/* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
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ata_sff_dma_pause(ap);
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}
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EXPORT_SYMBOL_GPL(ata_bmdma_stop);
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/**
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* ata_bmdma_status - Read PCI IDE BMDMA status
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* @ap: Port associated with this ATA transaction.
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*
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* Read and return BMDMA status register.
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*
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* May be used as the bmdma_status() entry in ata_port_operations.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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u8 ata_bmdma_status(struct ata_port *ap)
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{
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return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
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}
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EXPORT_SYMBOL_GPL(ata_bmdma_status);
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#ifdef CONFIG_PCI
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/**
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* ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
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* @pdev: PCI device
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*
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* Some PCI ATA devices report simplex mode but in fact can be told to
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* enter non simplex mode. This implements the necessary logic to
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* perform the task on such devices. Calling it on other devices will
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* have -undefined- behaviour.
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*/
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int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
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{
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unsigned long bmdma = pci_resource_start(pdev, 4);
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u8 simplex;
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if (bmdma == 0)
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return -ENOENT;
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simplex = inb(bmdma + 0x02);
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outb(simplex & 0x60, bmdma + 0x02);
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simplex = inb(bmdma + 0x02);
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if (simplex & 0x80)
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return -EOPNOTSUPP;
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return 0;
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}
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EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
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/**
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* ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
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* @host: target ATA host
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*
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* Acquire PCI BMDMA resources and initialize @host accordingly.
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*
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* LOCKING:
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* Inherited from calling layer (may sleep).
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*
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* RETURNS:
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* 0 on success, -errno otherwise.
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*/
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int ata_pci_bmdma_init(struct ata_host *host)
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{
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struct device *gdev = host->dev;
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struct pci_dev *pdev = to_pci_dev(gdev);
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int i, rc;
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/* No BAR4 allocation: No DMA */
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if (pci_resource_start(pdev, 4) == 0)
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return 0;
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/* TODO: If we get no DMA mask we should fall back to PIO */
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rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
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if (rc)
|
||||
return rc;
|
||||
rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
/* request and iomap DMA region */
|
||||
rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
|
||||
if (rc) {
|
||||
dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
host->iomap = pcim_iomap_table(pdev);
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
struct ata_port *ap = host->ports[i];
|
||||
void __iomem *bmdma = host->iomap[4] + 8 * i;
|
||||
|
||||
if (ata_port_is_dummy(ap))
|
||||
continue;
|
||||
|
||||
ap->ioaddr.bmdma_addr = bmdma;
|
||||
if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
|
||||
(ioread8(bmdma + 2) & 0x80))
|
||||
host->flags |= ATA_HOST_SIMPLEX;
|
||||
|
||||
ata_port_desc(ap, "bmdma 0x%llx",
|
||||
(unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
|
|
|||
|
|
@ -1619,16 +1619,7 @@ extern void ata_sff_post_internal_cmd(struct ata_queued_cmd *qc);
|
|||
extern int ata_sff_port_start(struct ata_port *ap);
|
||||
extern int ata_sff_port_start32(struct ata_port *ap);
|
||||
extern void ata_sff_std_ports(struct ata_ioports *ioaddr);
|
||||
extern unsigned long ata_bmdma_mode_filter(struct ata_device *dev,
|
||||
unsigned long xfer_mask);
|
||||
extern void ata_bmdma_setup(struct ata_queued_cmd *qc);
|
||||
extern void ata_bmdma_start(struct ata_queued_cmd *qc);
|
||||
extern void ata_bmdma_stop(struct ata_queued_cmd *qc);
|
||||
extern u8 ata_bmdma_status(struct ata_port *ap);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
extern int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev);
|
||||
extern int ata_pci_bmdma_init(struct ata_host *host);
|
||||
extern int ata_pci_sff_init_host(struct ata_host *host);
|
||||
extern int ata_pci_sff_prepare_host(struct pci_dev *pdev,
|
||||
const struct ata_port_info * const * ppi,
|
||||
|
|
@ -1641,6 +1632,18 @@ extern int ata_pci_sff_init_one(struct pci_dev *pdev,
|
|||
struct scsi_host_template *sht, void *host_priv, int hflags);
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
extern unsigned long ata_bmdma_mode_filter(struct ata_device *dev,
|
||||
unsigned long xfer_mask);
|
||||
extern void ata_bmdma_setup(struct ata_queued_cmd *qc);
|
||||
extern void ata_bmdma_start(struct ata_queued_cmd *qc);
|
||||
extern void ata_bmdma_stop(struct ata_queued_cmd *qc);
|
||||
extern u8 ata_bmdma_status(struct ata_port *ap);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
extern int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev);
|
||||
extern int ata_pci_bmdma_init(struct ata_host *host);
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
/**
|
||||
* ata_sff_busy_wait - Wait for a port status register
|
||||
* @ap: Port to wait for.
|
||||
|
|
|
|||
Loading…
Reference in New Issue