gpio: msm: Remove unused driver
Remove this driver now that Bjorn has introduced a pinctrl driver for msm8660 and the dts files have been updated with the pinctrl compatibles. Cc: Andy Gross <agross@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>hifive-unleashed-5.1
Stephen Boyd
Linus Walleij
parent
fa9795d112
commit
9f35382803
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@ -1,26 +0,0 @@
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MSM GPIO controller bindings
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Required properties:
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- compatible:
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- "qcom,msm-gpio" for MSM controllers
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- #gpio-cells : Should be two.
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- first cell is the pin number
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- second cell is used to specify optional parameters (unused)
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- gpio-controller : Marks the device node as a GPIO controller.
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- #interrupt-cells : Should be 2.
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- interrupt-controller: Mark the device node as an interrupt controller
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- interrupts : Specify the TLMM summary interrupt number
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- ngpio : Specify the number of MSM GPIOs
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Example:
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msmgpio: gpio@fd510000 {
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compatible = "qcom,msm-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0xfd510000 0x4000>;
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interrupts = <0 208 0>;
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ngpio = <150>;
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};
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@ -297,14 +297,6 @@ config GPIO_MPC8XXX
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Say Y here if you're going to use hardware that connects to the
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MPC512x/831x/834x/837x/8572/8610 GPIOs.
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config GPIO_MSM_V2
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tristate "Qualcomm MSM GPIO v2"
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depends on GPIOLIB && OF && ARCH_QCOM
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help
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Say yes here to support the GPIO interface on ARM v7 based
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Qualcomm MSM chips. Most of the pins on the MSM can be
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selected for GPIO, and are controlled by this driver.
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config GPIO_MVEBU
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def_bool y
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depends on PLAT_ORION
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@ -64,7 +64,6 @@ obj-$(CONFIG_GPIO_MOXART) += gpio-moxart.o
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obj-$(CONFIG_GPIO_MPC5200) += gpio-mpc5200.o
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obj-$(CONFIG_GPIO_MPC8XXX) += gpio-mpc8xxx.o
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obj-$(CONFIG_GPIO_MSIC) += gpio-msic.o
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obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o
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obj-$(CONFIG_GPIO_MVEBU) += gpio-mvebu.o
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obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o
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obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o
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@ -1,453 +0,0 @@
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/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/bitmap.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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#define MAX_NR_GPIO 300
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/* Bits of interest in the GPIO_IN_OUT register.
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*/
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enum {
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GPIO_IN = 0,
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GPIO_OUT = 1
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};
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/* Bits of interest in the GPIO_INTR_STATUS register.
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*/
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enum {
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INTR_STATUS = 0,
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};
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/* Bits of interest in the GPIO_CFG register.
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*/
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enum {
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GPIO_OE = 9,
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};
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/* Bits of interest in the GPIO_INTR_CFG register.
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* When a GPIO triggers, two separate decisions are made, controlled
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* by two separate flags.
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*
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* - First, INTR_RAW_STATUS_EN controls whether or not the GPIO_INTR_STATUS
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* register for that GPIO will be updated to reflect the triggering of that
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* gpio. If this bit is 0, this register will not be updated.
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* - Second, INTR_ENABLE controls whether an interrupt is triggered.
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*
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* If INTR_ENABLE is set and INTR_RAW_STATUS_EN is NOT set, an interrupt
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* can be triggered but the status register will not reflect it.
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*/
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enum {
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INTR_ENABLE = 0,
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INTR_POL_CTL = 1,
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INTR_DECT_CTL = 2,
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INTR_RAW_STATUS_EN = 3,
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};
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/* Codes of interest in GPIO_INTR_CFG_SU.
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*/
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enum {
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TARGET_PROC_SCORPION = 4,
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TARGET_PROC_NONE = 7,
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};
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/**
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* struct msm_gpio_dev: the MSM8660 SoC GPIO device structure
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*
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* @enabled_irqs: a bitmap used to optimize the summary-irq handler. By
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* keeping track of which gpios are unmasked as irq sources, we avoid
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* having to do readl calls on hundreds of iomapped registers each time
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* the summary interrupt fires in order to locate the active interrupts.
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*
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* @wake_irqs: a bitmap for tracking which interrupt lines are enabled
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* as wakeup sources. When the device is suspended, interrupts which are
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* not wakeup sources are disabled.
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*
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* @dual_edge_irqs: a bitmap used to track which irqs are configured
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* as dual-edge, as this is not supported by the hardware and requires
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* some special handling in the driver.
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*/
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struct msm_gpio_dev {
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struct gpio_chip gpio_chip;
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DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
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DECLARE_BITMAP(wake_irqs, MAX_NR_GPIO);
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DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
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struct irq_domain *domain;
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int summary_irq;
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void __iomem *msm_tlmm_base;
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};
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static struct msm_gpio_dev msm_gpio;
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#define GPIO_INTR_CFG_SU(gpio) (msm_gpio.msm_tlmm_base + 0x0400 + \
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(0x04 * (gpio)))
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#define GPIO_CONFIG(gpio) (msm_gpio.msm_tlmm_base + 0x1000 + \
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(0x10 * (gpio)))
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#define GPIO_IN_OUT(gpio) (msm_gpio.msm_tlmm_base + 0x1004 + \
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(0x10 * (gpio)))
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#define GPIO_INTR_CFG(gpio) (msm_gpio.msm_tlmm_base + 0x1008 + \
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(0x10 * (gpio)))
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#define GPIO_INTR_STATUS(gpio) (msm_gpio.msm_tlmm_base + 0x100c + \
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(0x10 * (gpio)))
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static DEFINE_SPINLOCK(tlmm_lock);
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static inline struct msm_gpio_dev *to_msm_gpio_dev(struct gpio_chip *chip)
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{
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return container_of(chip, struct msm_gpio_dev, gpio_chip);
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}
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static inline void set_gpio_bits(unsigned n, void __iomem *reg)
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{
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writel(readl(reg) | n, reg);
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}
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static inline void clear_gpio_bits(unsigned n, void __iomem *reg)
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{
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writel(readl(reg) & ~n, reg);
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}
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static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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return readl(GPIO_IN_OUT(offset)) & BIT(GPIO_IN);
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}
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static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
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{
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writel(val ? BIT(GPIO_OUT) : 0, GPIO_IN_OUT(offset));
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}
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static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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unsigned long irq_flags;
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spin_lock_irqsave(&tlmm_lock, irq_flags);
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clear_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset));
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spin_unlock_irqrestore(&tlmm_lock, irq_flags);
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return 0;
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}
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static int msm_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset,
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int val)
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{
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unsigned long irq_flags;
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spin_lock_irqsave(&tlmm_lock, irq_flags);
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msm_gpio_set(chip, offset, val);
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set_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset));
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spin_unlock_irqrestore(&tlmm_lock, irq_flags);
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return 0;
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}
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static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
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{
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return 0;
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}
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static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
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{
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return;
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}
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static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct msm_gpio_dev *g_dev = to_msm_gpio_dev(chip);
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struct irq_domain *domain = g_dev->domain;
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return irq_create_mapping(domain, offset);
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}
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/* For dual-edge interrupts in software, since the hardware has no
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* such support:
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*
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* At appropriate moments, this function may be called to flip the polarity
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* settings of both-edge irq lines to try and catch the next edge.
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*
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* The attempt is considered successful if:
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* - the status bit goes high, indicating that an edge was caught, or
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* - the input value of the gpio doesn't change during the attempt.
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* If the value changes twice during the process, that would cause the first
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* test to fail but would force the second, as two opposite
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* transitions would cause a detection no matter the polarity setting.
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*
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* The do-loop tries to sledge-hammer closed the timing hole between
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* the initial value-read and the polarity-write - if the line value changes
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* during that window, an interrupt is lost, the new polarity setting is
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* incorrect, and the first success test will fail, causing a retry.
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*
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* Algorithm comes from Google's msmgpio driver, see mach-msm/gpio.c.
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*/
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static void msm_gpio_update_dual_edge_pos(unsigned gpio)
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{
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int loop_limit = 100;
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unsigned val, val2, intstat;
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do {
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val = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN);
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if (val)
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clear_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio));
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else
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set_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio));
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val2 = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN);
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intstat = readl(GPIO_INTR_STATUS(gpio)) & BIT(INTR_STATUS);
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if (intstat || val == val2)
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return;
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} while (loop_limit-- > 0);
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pr_err("%s: dual-edge irq failed to stabilize, "
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"interrupts dropped. %#08x != %#08x\n",
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__func__, val, val2);
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}
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static void msm_gpio_irq_ack(struct irq_data *d)
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{
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int gpio = d->hwirq;
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writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio));
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if (test_bit(gpio, msm_gpio.dual_edge_irqs))
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msm_gpio_update_dual_edge_pos(gpio);
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}
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static void msm_gpio_irq_mask(struct irq_data *d)
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{
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unsigned long irq_flags;
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int gpio = d->hwirq;
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spin_lock_irqsave(&tlmm_lock, irq_flags);
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writel(TARGET_PROC_NONE, GPIO_INTR_CFG_SU(gpio));
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clear_gpio_bits(BIT(INTR_RAW_STATUS_EN) | BIT(INTR_ENABLE), GPIO_INTR_CFG(gpio));
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__clear_bit(gpio, msm_gpio.enabled_irqs);
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spin_unlock_irqrestore(&tlmm_lock, irq_flags);
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}
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static void msm_gpio_irq_unmask(struct irq_data *d)
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{
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unsigned long irq_flags;
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int gpio = d->hwirq;
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spin_lock_irqsave(&tlmm_lock, irq_flags);
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__set_bit(gpio, msm_gpio.enabled_irqs);
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set_gpio_bits(BIT(INTR_RAW_STATUS_EN) | BIT(INTR_ENABLE), GPIO_INTR_CFG(gpio));
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writel(TARGET_PROC_SCORPION, GPIO_INTR_CFG_SU(gpio));
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spin_unlock_irqrestore(&tlmm_lock, irq_flags);
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}
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static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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unsigned long irq_flags;
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int gpio = d->hwirq;
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uint32_t bits;
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spin_lock_irqsave(&tlmm_lock, irq_flags);
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bits = readl(GPIO_INTR_CFG(gpio));
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if (flow_type & IRQ_TYPE_EDGE_BOTH) {
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bits |= BIT(INTR_DECT_CTL);
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irq_set_handler_locked(d, handle_edge_irq);
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if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
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__set_bit(gpio, msm_gpio.dual_edge_irqs);
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else
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__clear_bit(gpio, msm_gpio.dual_edge_irqs);
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} else {
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bits &= ~BIT(INTR_DECT_CTL);
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irq_set_handler_locked(d, handle_level_irq);
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__clear_bit(gpio, msm_gpio.dual_edge_irqs);
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}
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if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH))
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bits |= BIT(INTR_POL_CTL);
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else
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bits &= ~BIT(INTR_POL_CTL);
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writel(bits, GPIO_INTR_CFG(gpio));
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if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
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msm_gpio_update_dual_edge_pos(gpio);
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spin_unlock_irqrestore(&tlmm_lock, irq_flags);
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return 0;
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}
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/*
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* When the summary IRQ is raised, any number of GPIO lines may be high.
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* It is the job of the summary handler to find all those GPIO lines
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* which have been set as summary IRQ lines and which are triggered,
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* and to call their interrupt handlers.
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*/
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static void msm_summary_irq_handler(struct irq_desc *desc)
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{
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unsigned long i;
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struct irq_chip *chip = irq_desc_get_chip(desc);
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chained_irq_enter(chip, desc);
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for_each_set_bit(i, msm_gpio.enabled_irqs, MAX_NR_GPIO) {
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if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS))
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generic_handle_irq(irq_find_mapping(msm_gpio.domain,
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i));
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}
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chained_irq_exit(chip, desc);
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}
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static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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int gpio = d->hwirq;
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if (on) {
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if (bitmap_empty(msm_gpio.wake_irqs, MAX_NR_GPIO))
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irq_set_irq_wake(msm_gpio.summary_irq, 1);
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set_bit(gpio, msm_gpio.wake_irqs);
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} else {
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clear_bit(gpio, msm_gpio.wake_irqs);
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if (bitmap_empty(msm_gpio.wake_irqs, MAX_NR_GPIO))
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irq_set_irq_wake(msm_gpio.summary_irq, 0);
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}
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return 0;
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}
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static struct irq_chip msm_gpio_irq_chip = {
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.name = "msmgpio",
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.irq_mask = msm_gpio_irq_mask,
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.irq_unmask = msm_gpio_irq_unmask,
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.irq_ack = msm_gpio_irq_ack,
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.irq_set_type = msm_gpio_irq_set_type,
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.irq_set_wake = msm_gpio_irq_set_wake,
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};
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static struct lock_class_key msm_gpio_lock_class;
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static int msm_gpio_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_lockdep_class(irq, &msm_gpio_lock_class);
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irq_set_chip_and_handler(irq, &msm_gpio_irq_chip,
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handle_level_irq);
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return 0;
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}
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static const struct irq_domain_ops msm_gpio_irq_domain_ops = {
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.xlate = irq_domain_xlate_twocell,
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.map = msm_gpio_irq_domain_map,
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};
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static int msm_gpio_probe(struct platform_device *pdev)
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{
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int ret, ngpio;
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struct resource *res;
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if (of_property_read_u32(pdev->dev.of_node, "ngpio", &ngpio)) {
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dev_err(&pdev->dev, "%s: ngpio property missing\n", __func__);
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return -EINVAL;
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}
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if (ngpio > MAX_NR_GPIO)
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WARN(1, "ngpio exceeds the MAX_NR_GPIO. Increase MAX_NR_GPIO\n");
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bitmap_zero(msm_gpio.enabled_irqs, MAX_NR_GPIO);
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bitmap_zero(msm_gpio.wake_irqs, MAX_NR_GPIO);
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bitmap_zero(msm_gpio.dual_edge_irqs, MAX_NR_GPIO);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
msm_gpio.msm_tlmm_base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(msm_gpio.msm_tlmm_base))
|
||||
return PTR_ERR(msm_gpio.msm_tlmm_base);
|
||||
|
||||
msm_gpio.gpio_chip.ngpio = ngpio;
|
||||
msm_gpio.gpio_chip.label = pdev->name;
|
||||
msm_gpio.gpio_chip.dev = &pdev->dev;
|
||||
msm_gpio.gpio_chip.base = 0;
|
||||
msm_gpio.gpio_chip.direction_input = msm_gpio_direction_input;
|
||||
msm_gpio.gpio_chip.direction_output = msm_gpio_direction_output;
|
||||
msm_gpio.gpio_chip.get = msm_gpio_get;
|
||||
msm_gpio.gpio_chip.set = msm_gpio_set;
|
||||
msm_gpio.gpio_chip.to_irq = msm_gpio_to_irq;
|
||||
msm_gpio.gpio_chip.request = msm_gpio_request;
|
||||
msm_gpio.gpio_chip.free = msm_gpio_free;
|
||||
|
||||
ret = gpiochip_add(&msm_gpio.gpio_chip);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "gpiochip_add failed with error %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
msm_gpio.summary_irq = platform_get_irq(pdev, 0);
|
||||
if (msm_gpio.summary_irq < 0) {
|
||||
dev_err(&pdev->dev, "No Summary irq defined for msmgpio\n");
|
||||
return msm_gpio.summary_irq;
|
||||
}
|
||||
|
||||
msm_gpio.domain = irq_domain_add_linear(pdev->dev.of_node, ngpio,
|
||||
&msm_gpio_irq_domain_ops,
|
||||
&msm_gpio);
|
||||
if (!msm_gpio.domain)
|
||||
return -ENODEV;
|
||||
|
||||
irq_set_chained_handler(msm_gpio.summary_irq, msm_summary_irq_handler);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id msm_gpio_of_match[] = {
|
||||
{ .compatible = "qcom,msm-gpio", },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, msm_gpio_of_match);
|
||||
|
||||
static int msm_gpio_remove(struct platform_device *dev)
|
||||
{
|
||||
gpiochip_remove(&msm_gpio.gpio_chip);
|
||||
|
||||
irq_set_handler(msm_gpio.summary_irq, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver msm_gpio_driver = {
|
||||
.probe = msm_gpio_probe,
|
||||
.remove = msm_gpio_remove,
|
||||
.driver = {
|
||||
.name = "msmgpio",
|
||||
.of_match_table = msm_gpio_of_match,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(msm_gpio_driver)
|
||||
|
||||
MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>");
|
||||
MODULE_DESCRIPTION("Driver for Qualcomm MSM TLMMv2 SoC GPIOs");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:msmgpio");
|
||||
Loading…
Reference in New Issue