MIPS: PMC MSP71XX gpio drivers
This new gpio driver for PMC-Sierra's MSP71xx SoC allows standard api calls for access to the general and extended gpio's. Signed-off-by: Patrick Glass <patrickglass@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100755 arch/mips/pmc-sierra/msp71xx/gpio.c create mode 100755 arch/mips/pmc-sierra/msp71xx/gpio_extended.c create mode 100755 include/asm-mips/pmc-sierra/msp71xx/gpio.hhifive-unleashed-5.1
Patrick Glass
Ralf Baechle
parent
5d9a76cd0e
commit
9fa32c6b02
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@ -3,6 +3,7 @@
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#
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obj-y += msp_prom.o msp_setup.o msp_irq.o \
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msp_time.o msp_serial.o msp_elb.o
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obj-$(CONFIG_HAVE_GPIO_LIB) += gpio.o gpio_extended.o
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obj-$(CONFIG_PMC_MSP7120_GW) += msp_hwbutton.o
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obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o
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obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o
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@ -0,0 +1,218 @@
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/*
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* @file /arch/mips/pmc-sierra/msp71xx/gpio.c
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*
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* Generic PMC MSP71xx GPIO handling. These base gpio are controlled by two
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* types of registers. The data register sets the output level when in output
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* mode and when in input mode will contain the value at the input. The config
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* register sets the various modes for each gpio.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* @author Patrick Glass <patrickglass@gmail.com>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/gpio.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#define MSP71XX_CFG_OFFSET(gpio) (4 * (gpio))
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#define CONF_MASK 0x0F
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#define MSP71XX_GPIO_INPUT 0x01
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#define MSP71XX_GPIO_OUTPUT 0x08
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#define MSP71XX_GPIO_BASE 0x0B8400000L
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#define to_msp71xx_gpio_chip(c) container_of(c, struct msp71xx_gpio_chip, chip)
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static spinlock_t gpio_lock;
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/*
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* struct msp71xx_gpio_chip - container for gpio chip and registers
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* @chip: chip structure for the specified gpio bank
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* @data_reg: register for reading and writing the gpio pin value
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* @config_reg: register to set the mode for the gpio pin bank
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* @out_drive_reg: register to set the output drive mode for the gpio pin bank
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*/
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struct msp71xx_gpio_chip {
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struct gpio_chip chip;
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void __iomem *data_reg;
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void __iomem *config_reg;
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void __iomem *out_drive_reg;
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};
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/*
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* msp71xx_gpio_get() - return the chip's gpio value
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* @chip: chip structure which controls the specified gpio
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* @offset: gpio whose value will be returned
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*
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* It will return 0 if gpio value is low and other if high.
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*/
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static int msp71xx_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip);
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return __raw_readl(msp_chip->data_reg) & (1 << offset);
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}
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/*
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* msp71xx_gpio_set() - set the output value for the gpio
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* @chip: chip structure who controls the specified gpio
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* @offset: gpio whose value will be assigned
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* @value: logic level to assign to the gpio initially
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*
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* This will set the gpio bit specified to the desired value. It will set the
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* gpio pin low if value is 0 otherwise it will be high.
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*/
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static void msp71xx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip);
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unsigned long flags;
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u32 data;
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spin_lock_irqsave(&gpio_lock, flags);
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data = __raw_readl(msp_chip->data_reg);
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if (value)
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data |= (1 << offset);
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else
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data &= ~(1 << offset);
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__raw_writel(data, msp_chip->data_reg);
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spin_unlock_irqrestore(&gpio_lock, flags);
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}
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/*
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* msp71xx_set_gpio_mode() - declare the mode for a gpio
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* @chip: chip structure which controls the specified gpio
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* @offset: gpio whose value will be assigned
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* @mode: desired configuration for the gpio (see datasheet)
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*
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* It will set the gpio pin config to the @mode value passed in.
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*/
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static int msp71xx_set_gpio_mode(struct gpio_chip *chip,
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unsigned offset, int mode)
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{
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struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip);
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const unsigned bit_offset = MSP71XX_CFG_OFFSET(offset);
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unsigned long flags;
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u32 cfg;
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spin_lock_irqsave(&gpio_lock, flags);
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cfg = __raw_readl(msp_chip->config_reg);
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cfg &= ~(CONF_MASK << bit_offset);
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cfg |= (mode << bit_offset);
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__raw_writel(cfg, msp_chip->config_reg);
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spin_unlock_irqrestore(&gpio_lock, flags);
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return 0;
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}
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/*
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* msp71xx_direction_output() - declare the direction mode for a gpio
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* @chip: chip structure which controls the specified gpio
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* @offset: gpio whose value will be assigned
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* @value: logic level to assign to the gpio initially
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*
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* This call will set the mode for the @gpio to output. It will set the
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* gpio pin low if value is 0 otherwise it will be high.
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*/
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static int msp71xx_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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msp71xx_gpio_set(chip, offset, value);
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return msp71xx_set_gpio_mode(chip, offset, MSP71XX_GPIO_OUTPUT);
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}
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/*
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* msp71xx_direction_input() - declare the direction mode for a gpio
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* @chip: chip structure which controls the specified gpio
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* @offset: gpio whose to which the value will be assigned
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*
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* This call will set the mode for the @gpio to input.
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*/
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static int msp71xx_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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return msp71xx_set_gpio_mode(chip, offset, MSP71XX_GPIO_INPUT);
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}
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/*
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* msp71xx_set_output_drive() - declare the output drive for the gpio line
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* @gpio: gpio pin whose output drive you wish to modify
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* @value: zero for active drain 1 for open drain drive
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*
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* This call will set the output drive mode for the @gpio to output.
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*/
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int msp71xx_set_output_drive(unsigned gpio, int value)
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{
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unsigned long flags;
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u32 data;
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if (gpio > 15 || gpio < 0)
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return -EINVAL;
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spin_lock_irqsave(&gpio_lock, flags);
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data = __raw_readl((void __iomem *)(MSP71XX_GPIO_BASE + 0x190));
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if (value)
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data |= (1 << gpio);
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else
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data &= ~(1 << gpio);
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__raw_writel(data, (void __iomem *)(MSP71XX_GPIO_BASE + 0x190));
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spin_unlock_irqrestore(&gpio_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(msp71xx_set_output_drive);
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#define MSP71XX_GPIO_BANK(name, dr, cr, base_gpio, num_gpio) \
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{ \
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.chip = { \
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.label = name, \
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.direction_input = msp71xx_direction_input, \
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.direction_output = msp71xx_direction_output, \
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.get = msp71xx_gpio_get, \
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.set = msp71xx_gpio_set, \
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.base = base_gpio, \
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.ngpio = num_gpio \
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}, \
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.data_reg = (void __iomem *)(MSP71XX_GPIO_BASE + dr), \
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.config_reg = (void __iomem *)(MSP71XX_GPIO_BASE + cr), \
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.out_drive_reg = (void __iomem *)(MSP71XX_GPIO_BASE + 0x190), \
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}
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/*
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* struct msp71xx_gpio_banks[] - container array of gpio banks
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* @chip: chip structure for the specified gpio bank
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* @data_reg: register for reading and writing the gpio pin value
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* @config_reg: register to set the mode for the gpio pin bank
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*
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* This array structure defines the gpio banks for the PMC MIPS Processor.
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* We specify the bank name, the data register, the config register, base
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* starting gpio number, and the number of gpios exposed by the bank.
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*/
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static struct msp71xx_gpio_chip msp71xx_gpio_banks[] = {
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MSP71XX_GPIO_BANK("GPIO_1_0", 0x170, 0x180, 0, 2),
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MSP71XX_GPIO_BANK("GPIO_5_2", 0x174, 0x184, 2, 4),
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MSP71XX_GPIO_BANK("GPIO_9_6", 0x178, 0x188, 6, 4),
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MSP71XX_GPIO_BANK("GPIO_15_10", 0x17C, 0x18C, 10, 6),
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};
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void __init msp71xx_init_gpio(void)
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{
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int i;
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spin_lock_init(&gpio_lock);
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for (i = 0; i < ARRAY_SIZE(msp71xx_gpio_banks); i++)
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gpiochip_add(&msp71xx_gpio_banks[i].chip);
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}
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/*
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* @file /arch/mips/pmc-sierra/msp71xx/gpio_extended.c
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*
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* Generic PMC MSP71xx EXTENDED (EXD) GPIO handling. The extended gpio is
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* a set of hardware registers that have no need for explicit locking as
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* it is handled by unique method of writing individual set/clr bits.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* @author Patrick Glass <patrickglass@gmail.com>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#define MSP71XX_DATA_OFFSET(gpio) (2 * (gpio))
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#define MSP71XX_READ_OFFSET(gpio) (MSP71XX_DATA_OFFSET(gpio) + 1)
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#define MSP71XX_CFG_OUT_OFFSET(gpio) (MSP71XX_DATA_OFFSET(gpio) + 16)
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#define MSP71XX_CFG_IN_OFFSET(gpio) (MSP71XX_CFG_OUT_OFFSET(gpio) + 1)
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#define MSP71XX_EXD_GPIO_BASE 0x0BC000000L
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#define to_msp71xx_exd_gpio_chip(c) \
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container_of(c, struct msp71xx_exd_gpio_chip, chip)
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/*
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* struct msp71xx_exd_gpio_chip - container for gpio chip and registers
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* @chip: chip structure for the specified gpio bank
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* @reg: register for control and data of gpio pin
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*/
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struct msp71xx_exd_gpio_chip {
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struct gpio_chip chip;
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void __iomem *reg;
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};
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/*
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* msp71xx_exd_gpio_get() - return the chip's gpio value
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* @chip: chip structure which controls the specified gpio
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* @offset: gpio whose value will be returned
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*
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* It will return 0 if gpio value is low and other if high.
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*/
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static int msp71xx_exd_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct msp71xx_exd_gpio_chip *msp71xx_chip =
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to_msp71xx_exd_gpio_chip(chip);
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const unsigned bit = MSP71XX_READ_OFFSET(offset);
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return __raw_readl(msp71xx_chip->reg) & (1 << bit);
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}
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/*
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* msp71xx_exd_gpio_set() - set the output value for the gpio
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* @chip: chip structure who controls the specified gpio
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* @offset: gpio whose value will be assigned
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* @value: logic level to assign to the gpio initially
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*
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* This will set the gpio bit specified to the desired value. It will set the
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* gpio pin low if value is 0 otherwise it will be high.
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*/
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static void msp71xx_exd_gpio_set(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct msp71xx_exd_gpio_chip *msp71xx_chip =
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to_msp71xx_exd_gpio_chip(chip);
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const unsigned bit = MSP71XX_DATA_OFFSET(offset);
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__raw_writel(1 << (bit + (value ? 1 : 0)), msp71xx_chip->reg);
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}
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/*
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* msp71xx_exd_direction_output() - declare the direction mode for a gpio
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* @chip: chip structure which controls the specified gpio
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* @offset: gpio whose value will be assigned
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* @value: logic level to assign to the gpio initially
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*
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* This call will set the mode for the @gpio to output. It will set the
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* gpio pin low if value is 0 otherwise it will be high.
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*/
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static int msp71xx_exd_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct msp71xx_exd_gpio_chip *msp71xx_chip =
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to_msp71xx_exd_gpio_chip(chip);
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msp71xx_exd_gpio_set(chip, offset, value);
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__raw_writel(1 << MSP71XX_CFG_OUT_OFFSET(offset), msp71xx_chip->reg);
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return 0;
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}
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/*
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* msp71xx_exd_direction_input() - declare the direction mode for a gpio
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* @chip: chip structure which controls the specified gpio
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* @offset: gpio whose to which the value will be assigned
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*
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* This call will set the mode for the @gpio to input.
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*/
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static int msp71xx_exd_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct msp71xx_exd_gpio_chip *msp71xx_chip =
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to_msp71xx_exd_gpio_chip(chip);
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__raw_writel(1 << MSP71XX_CFG_IN_OFFSET(offset), msp71xx_chip->reg);
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return 0;
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}
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#define MSP71XX_EXD_GPIO_BANK(name, exd_reg, base_gpio, num_gpio) \
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{ \
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.chip = { \
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.label = name, \
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.direction_input = msp71xx_exd_direction_input, \
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.direction_output = msp71xx_exd_direction_output, \
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.get = msp71xx_exd_gpio_get, \
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.set = msp71xx_exd_gpio_set, \
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.base = base_gpio, \
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.ngpio = num_gpio, \
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}, \
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.reg = (void __iomem *)(MSP71XX_EXD_GPIO_BASE + exd_reg), \
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}
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/*
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* struct msp71xx_exd_gpio_banks[] - container array of gpio banks
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* @chip: chip structure for the specified gpio bank
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* @reg: register for reading and writing the gpio pin value
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*
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* This array structure defines the extended gpio banks for the
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* PMC MIPS Processor. We specify the bank name, the data/config
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* register,the base starting gpio number, and the number of
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* gpios exposed by the bank of gpios.
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*/
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static struct msp71xx_exd_gpio_chip msp71xx_exd_gpio_banks[] = {
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MSP71XX_EXD_GPIO_BANK("GPIO_23_16", 0x188, 16, 8),
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MSP71XX_EXD_GPIO_BANK("GPIO_27_24", 0x18C, 24, 4),
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};
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void __init msp71xx_init_gpio_extended(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(msp71xx_exd_gpio_banks); i++)
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gpiochip_add(&msp71xx_exd_gpio_banks[i].chip);
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}
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@ -0,0 +1,46 @@
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/*
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* include/asm-mips/pmc-sierra/msp71xx/gpio.h
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* @author Patrick Glass <patrickglass@gmail.com>
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*/
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#ifndef __PMC_MSP71XX_GPIO_H
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#define __PMC_MSP71XX_GPIO_H
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/* Max number of gpio's is 28 on chip plus 3 banks of I2C IO Expanders */
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#define ARCH_NR_GPIOS (28 + (3 * 8))
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/* new generic GPIO API - see Documentation/gpio.txt */
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#include <asm-generic/gpio.h>
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#define gpio_get_value __gpio_get_value
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#define gpio_set_value __gpio_set_value
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#define gpio_cansleep __gpio_cansleep
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/* Setup calls for the gpio and gpio extended */
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extern void msp71xx_init_gpio(void);
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extern void msp71xx_init_gpio_extended(void);
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extern int msp71xx_set_output_drive(unsigned gpio, int value);
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/* Custom output drive functionss */
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static inline int gpio_set_output_drive(unsigned gpio, int value)
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{
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return msp71xx_set_output_drive(gpio, value);
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}
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/* IRQ's are not supported for gpio lines */
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static inline int gpio_to_irq(unsigned gpio)
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{
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return -EINVAL;
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}
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static inline int irq_to_gpio(unsigned irq)
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{
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return -EINVAL;
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}
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#endif /* __PMC_MSP71XX_GPIO_H */
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