drm/i915: Remove manual breadcumb counting
Now that we know we measure the size of the engine->emit_breadcrumb() correctly, we can remove the previous manual counting. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190125120005.25191-1-chris@chris-wilson.co.ukhifive-unleashed-5.1
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e1a73a54a9
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9fa4973e91
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@ -650,7 +650,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct i915_gem_context *ctx)
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* around inside i915_request_add() there is sufficient space at
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* the beginning of the ring as well.
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*/
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rq->reserved_space = 2 * engine->emit_breadcrumb_sz * sizeof(u32);
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rq->reserved_space = 2 * engine->emit_breadcrumb_dw * sizeof(u32);
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/*
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* Record the position of the start of the request so that
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@ -901,7 +901,7 @@ void i915_request_add(struct i915_request *request)
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* GPU processing the request, we never over-estimate the
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* position of the ring's HEAD.
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*/
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cs = intel_ring_begin(request, engine->emit_breadcrumb_sz);
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cs = intel_ring_begin(request, engine->emit_breadcrumb_dw);
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GEM_BUG_ON(IS_ERR(cs));
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request->postfix = intel_ring_offset(request, cs);
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@ -611,7 +611,7 @@ struct measure_breadcrumb {
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u32 cs[1024];
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};
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static int measure_breadcrumb_sz(struct intel_engine_cs *engine)
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static int measure_breadcrumb_dw(struct intel_engine_cs *engine)
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{
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struct measure_breadcrumb *frame;
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unsigned int dw;
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@ -637,7 +637,6 @@ static int measure_breadcrumb_sz(struct intel_engine_cs *engine)
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frame->rq.timeline = &frame->timeline;
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dw = engine->emit_breadcrumb(&frame->rq, frame->cs) - frame->cs;
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GEM_BUG_ON(dw != engine->emit_breadcrumb_sz);
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i915_timeline_fini(&frame->timeline);
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kfree(frame);
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@ -698,11 +697,11 @@ int intel_engine_init_common(struct intel_engine_cs *engine)
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if (ret)
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goto err_breadcrumbs;
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ret = measure_breadcrumb_sz(engine);
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ret = measure_breadcrumb_dw(engine);
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if (ret < 0)
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goto err_status_page;
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engine->emit_breadcrumb_sz = ret;
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engine->emit_breadcrumb_dw = ret;
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return 0;
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@ -2075,7 +2075,6 @@ static u32 *gen8_emit_breadcrumb(struct i915_request *request, u32 *cs)
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return gen8_emit_wa_tail(request, cs);
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}
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static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS;
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static u32 *gen8_emit_breadcrumb_rcs(struct i915_request *request, u32 *cs)
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{
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@ -2099,7 +2098,6 @@ static u32 *gen8_emit_breadcrumb_rcs(struct i915_request *request, u32 *cs)
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return gen8_emit_wa_tail(request, cs);
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}
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static const int gen8_emit_breadcrumb_rcs_sz = 8 + WA_TAIL_DWORDS;
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static int gen8_init_rcs_context(struct i915_request *rq)
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{
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@ -2192,7 +2190,6 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
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engine->emit_flush = gen8_emit_flush;
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engine->emit_breadcrumb = gen8_emit_breadcrumb;
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engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz;
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engine->set_default_submission = intel_execlists_set_default_submission;
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@ -2298,7 +2295,6 @@ int logical_render_ring_init(struct intel_engine_cs *engine)
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engine->init_context = gen8_init_rcs_context;
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engine->emit_flush = gen8_emit_flush_render;
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engine->emit_breadcrumb = gen8_emit_breadcrumb_rcs;
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engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_rcs_sz;
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ret = logical_ring_init(engine);
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if (ret)
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@ -330,7 +330,6 @@ static u32 *gen6_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
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return cs;
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}
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static const int gen6_rcs_emit_breadcrumb_sz = 14;
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static int
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gen7_render_ring_cs_stall_wa(struct i915_request *rq)
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@ -432,7 +431,6 @@ static u32 *gen7_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
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return cs;
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}
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static const int gen7_rcs_emit_breadcrumb_sz = 6;
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static u32 *gen6_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
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{
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@ -446,7 +444,6 @@ static u32 *gen6_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
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return cs;
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}
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static const int gen6_xcs_emit_breadcrumb_sz = 4;
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#define GEN7_XCS_WA 32
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static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
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@ -475,7 +472,6 @@ static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
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return cs;
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}
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static const int gen7_xcs_emit_breadcrumb_sz = 8 + GEN7_XCS_WA * 3;
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#undef GEN7_XCS_WA
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static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
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@ -885,7 +881,6 @@ static u32 *i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs)
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return cs;
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}
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static const int i9xx_emit_breadcrumb_sz = 6;
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#define GEN5_WA_STORES 8 /* must be at least 1! */
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static u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)
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@ -908,7 +903,6 @@ static u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)
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return cs;
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}
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static const int gen5_emit_breadcrumb_sz = GEN5_WA_STORES * 3 + 2;
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#undef GEN5_WA_STORES
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static void
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@ -2206,11 +2200,8 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
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engine->request_alloc = ring_request_alloc;
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engine->emit_breadcrumb = i9xx_emit_breadcrumb;
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engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz;
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if (IS_GEN(dev_priv, 5)) {
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if (IS_GEN(dev_priv, 5))
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engine->emit_breadcrumb = gen5_emit_breadcrumb;
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engine->emit_breadcrumb_sz = gen5_emit_breadcrumb_sz;
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}
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engine->set_default_submission = i9xx_set_default_submission;
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@ -2240,12 +2231,10 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
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engine->init_context = intel_rcs_ctx_init;
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engine->emit_flush = gen7_render_ring_flush;
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engine->emit_breadcrumb = gen7_rcs_emit_breadcrumb;
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engine->emit_breadcrumb_sz = gen7_rcs_emit_breadcrumb_sz;
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} else if (IS_GEN(dev_priv, 6)) {
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engine->init_context = intel_rcs_ctx_init;
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engine->emit_flush = gen6_render_ring_flush;
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engine->emit_breadcrumb = gen6_rcs_emit_breadcrumb;
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engine->emit_breadcrumb_sz = gen6_rcs_emit_breadcrumb_sz;
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} else if (IS_GEN(dev_priv, 5)) {
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engine->emit_flush = gen4_render_ring_flush;
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} else {
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@ -2281,13 +2270,10 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
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engine->emit_flush = gen6_bsd_ring_flush;
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engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
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if (IS_GEN(dev_priv, 6)) {
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if (IS_GEN(dev_priv, 6))
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engine->emit_breadcrumb = gen6_xcs_emit_breadcrumb;
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engine->emit_breadcrumb_sz = gen6_xcs_emit_breadcrumb_sz;
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} else {
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else
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engine->emit_breadcrumb = gen7_xcs_emit_breadcrumb;
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engine->emit_breadcrumb_sz = gen7_xcs_emit_breadcrumb_sz;
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}
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} else {
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engine->emit_flush = bsd_ring_flush;
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if (IS_GEN(dev_priv, 5))
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@ -2310,13 +2296,10 @@ int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
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engine->emit_flush = gen6_ring_flush;
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engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
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if (IS_GEN(dev_priv, 6)) {
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if (IS_GEN(dev_priv, 6))
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engine->emit_breadcrumb = gen6_xcs_emit_breadcrumb;
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engine->emit_breadcrumb_sz = gen6_xcs_emit_breadcrumb_sz;
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} else {
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else
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engine->emit_breadcrumb = gen7_xcs_emit_breadcrumb;
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engine->emit_breadcrumb_sz = gen7_xcs_emit_breadcrumb_sz;
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}
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return intel_init_ring_buffer(engine);
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}
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@ -2335,7 +2318,6 @@ int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
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engine->irq_disable = hsw_vebox_irq_disable;
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engine->emit_breadcrumb = gen7_xcs_emit_breadcrumb;
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engine->emit_breadcrumb_sz = gen7_xcs_emit_breadcrumb_sz;
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return intel_init_ring_buffer(engine);
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}
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@ -471,7 +471,7 @@ struct intel_engine_cs {
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#define I915_DISPATCH_SECURE BIT(0)
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#define I915_DISPATCH_PINNED BIT(1)
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u32 *(*emit_breadcrumb)(struct i915_request *rq, u32 *cs);
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int emit_breadcrumb_sz;
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int emit_breadcrumb_dw;
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/* Pass the request to the hardware queue (e.g. directly into
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* the legacy ringbuffer or to the end of an execlist).
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