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Pin control fixes for v5.2: 

- Interrupt clearing fix for the Intel pin controllers affecting
   touchpads on some laptops.
 - Compile Kconfig fix for the STMFX expander pin controller.
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Merge tag 'pinctrl-v5.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:
 "The commits that stand out are the Intel fixes that arrived during the
  merge window and I got relayed by pull request from Andy.

  Apart from that a minor Kconfig noise.

   - Interrupt clearing fix for the Intel pin controllers affecting
     touchpads on some laptops.

   - Compile Kconfig fix for the STMFX expander pin controller"

* tag 'pinctrl-v5.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: stmfx: Fix compile issue when CONFIG_OF_GPIO is not defined
  pinctrl: intel: Clear interrupt status in mask/unmask callback
  pinctrl: intel: Use GENMASK() consistently
hifive-unleashed-5.2
Linus Torvalds 2019-05-28 09:35:04 -07:00
parent ca6584a331 b1fa7d8592
commit 9fb67d643f
2 changed files with 11 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/pinctrl/Kconfig
View File

@ -277,7 +277,7 @@ config PINCTRL_ST
config PINCTRL_STMFX
tristate "STMicroelectronics STMFX GPIO expander pinctrl driver"
depends on I2C
depends on OF || COMPILE_TEST
depends on OF_GPIO
select GENERIC_PINCONF
select GPIOLIB_IRQCHIP
select MFD_STMFX

45
drivers/pinctrl/intel/pinctrl-intel.c
View File

@ -33,13 +33,13 @@
#define PADOWN_BITS 4
#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
#define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
#define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p))
#define PADOWN_GPP(p) ((p) / 8)
/* Offset from pad_regs */
#define PADCFG0 0x000
#define PADCFG0_RXEVCFG_SHIFT 25
#define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT)
#define PADCFG0_RXEVCFG_MASK GENMASK(26, 25)
#define PADCFG0_RXEVCFG_LEVEL 0
#define PADCFG0_RXEVCFG_EDGE 1
#define PADCFG0_RXEVCFG_DISABLED 2
@ -51,7 +51,7 @@
#define PADCFG0_GPIROUTSMI BIT(18)
#define PADCFG0_GPIROUTNMI BIT(17)
#define PADCFG0_PMODE_SHIFT 10
#define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT)
#define PADCFG0_PMODE_MASK GENMASK(13, 10)
#define PADCFG0_GPIORXDIS BIT(9)
#define PADCFG0_GPIOTXDIS BIT(8)
#define PADCFG0_GPIORXSTATE BIT(1)
@ -60,7 +60,7 @@
#define PADCFG1 0x004
#define PADCFG1_TERM_UP BIT(13)
#define PADCFG1_TERM_SHIFT 10
#define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT)
#define PADCFG1_TERM_MASK GENMASK(12, 10)
#define PADCFG1_TERM_20K 4
#define PADCFG1_TERM_2K 3
#define PADCFG1_TERM_5K 2
@ -914,35 +914,6 @@ static void intel_gpio_irq_ack(struct irq_data *d)
}
}
static void intel_gpio_irq_enable(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
const struct intel_community *community;
const struct intel_padgroup *padgrp;
int pin;
pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
if (pin >= 0) {
unsigned int gpp, gpp_offset, is_offset;
unsigned long flags;
u32 value;
gpp = padgrp->reg_num;
gpp_offset = padgroup_offset(padgrp, pin);
is_offset = community->is_offset + gpp * 4;
raw_spin_lock_irqsave(&pctrl->lock, flags);
/* Clear interrupt status first to avoid unexpected interrupt */
writel(BIT(gpp_offset), community->regs + is_offset);
value = readl(community->regs + community->ie_offset + gpp * 4);
value |= BIT(gpp_offset);
writel(value, community->regs + community->ie_offset + gpp * 4);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
}
static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
@ -955,15 +926,20 @@ static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
if (pin >= 0) {
unsigned int gpp, gpp_offset;
unsigned long flags;
void __iomem *reg;
void __iomem *reg, *is;
u32 value;
gpp = padgrp->reg_num;
gpp_offset = padgroup_offset(padgrp, pin);
reg = community->regs + community->ie_offset + gpp * 4;
is = community->regs + community->is_offset + gpp * 4;
raw_spin_lock_irqsave(&pctrl->lock, flags);
/* Clear interrupt status first to avoid unexpected interrupt */
writel(BIT(gpp_offset), is);
value = readl(reg);
if (mask)
value &= ~BIT(gpp_offset);
@ -1107,7 +1083,6 @@ static irqreturn_t intel_gpio_irq(int irq, void *data)
static struct irq_chip intel_gpio_irqchip = {
.name = "intel-gpio",
.irq_enable = intel_gpio_irq_enable,
.irq_ack = intel_gpio_irq_ack,
.irq_mask = intel_gpio_irq_mask,
.irq_unmask = intel_gpio_irq_unmask,